EEE 6323 Advanced VLSI Design - University of Florida...Advanced VLSI Design Section: 0564 ... • Some useful tutorials for Analog Artist, Layout, Printing schematics/ waveforms and

1

EEE 6323 Advanced VLSI Design

Section: 0564

Lecture 0: Introduction

•  Course Outline •  CMOS Trends and Scaling

2

Practical Information •  Instructor

–  Rizwan Bashirullah –  Office: 527 NEB, –  E-mail: [email protected] –  Tel: (352) 392-0622, –  Fax: (352) 392-8381

•  Admin –  Marcy Lee, 440 NEB –  [email protected]

Practical Information •  Class

–  Meeting time: •  Tuesdays 10:40-11:30am •  Thursdays 10:40-12:35pm

–  Location: •  NEB202

–  Website: •  http://www.icr.ece.ufl.edu/teaching/EEE6323-S15/

EEE6323.htm (password protected)

–  Instructor Office Hours: •  Tuesdays: 11:30am-12:20pm (except for faculty meetings)

3

Practical Information •  Teaching Assistants

–  Qiuzhong Wu •  Email: [email protected] •  Office hours:

–  Wednesdays 3:00pm-5:00pm •  Location:

–  NEB 556

Class Material

•  Required Textbooks –  Neil H.E. Weste, David Harris, “CMOS VLSI Design, A

Circuits and Systems Perspective,” 3rd Edition, Pearson, Addison-Wesley, 2005. ISBN 0-321-14901-7

–  Jan. M. Rabaey, A. Chandrakasan, and B. Nikolic, "Digital Integrated Circuits, A Design Perspective," 2nd Edition, Prentice Hall, 2003. ISBN 0-13-090996-3

–  In addition, handouts developed by instructor may be downloaded from class www site

4

Reference Material

•  Journal/Conference References –  Journal of Solid State Circuits (JSSC), –  TVLSI, CAS-I and II –  ISSCC, VLSI Symposium, CICC, ISCAS

•  Web Links –  IEEE Explorer

Tutorials •  Some useful tutorials for Analog Artist, Layout, Printing schematics/

waveforms and remote access can be downloaded via the class website. •  •  Additional links to tutorials for Linux, VHDL coding and Cadence can be

found here, •  For VHDL: http://esd.cs.ucr.edu/labs/tutorial/ •  For Cadence:

http://www.ee.virginia.edu/~mrs8n/cadence/Cadencetutorials.html •  For UNIX: http://www.ee.surrey.ac.uk/Teaching/Unix/

5

Course Goals

•  To develop a basic understanding of CMOS integrated circuit design

•  To develop proficiency in analysis, design and implementation of CMOS circuits

•  To develop a basic understanding of design considerations to maximize chip success

Course Topics •  CMOS Overview

–  Scaling Trends and Process Technology

•  Gates –  Transistor Models –  DC/Transient and Delay –  Logical Effort –  Circuit Simulation

•  Digital Flow –  Design methodology –  Synthesis, Place and Route,

verification •  Low power design

–  Power dissipation –  Low power techniques and trends

•  Circuit Families –  Static, Dynamic –  Variability and Circuit Pitfalls

•  Datapaths –  Adders –  Multipliers

•  Timing –  Clock Distribution and Generation –  Skew Tolerant Design –  Latches and Flip-flops –  PLL/DLL

•  Signaling and power –  Interconnects, Packaging and I/O –  Power Delivery and Decoupling

•  Memory

6

Digital IC Flow

•  RTL to layout –  Behavioral Language –  Synthesis –  Place and route –  Verification

-- right-shift arithmetic for 8-bit signed integer rsa: process (a, shamt) variable fill : std_logic_vector(1 downto 0); variable temp : std_logic_vector(4 downto 0); begin

for i in 0 to 3 loop fill(i):=‘1’ and a(3); end loop; if shamt(0)=‘1’ then temp := fill(0) & a(7 downto 1); end if; if shamt(1)=‘1’ then temp := fill(1 downto 0) & temp(7 downto 2); end if; if shamt(2)=‘1’ then out <= fill(3 downto 0) & temp(7 downto 4); end if;

end process;

Grading Policy

•  Problem Sets (5-6): 30% •  Midterms (2): 20% Each •  Final Project (1): 30%

Grading policy is subject to change

7

Past Projects

•  EPC Gen 2 RFID protocol or Smart Card •  MIPS •  FFT processor •  Digital PLL •  Biosignal Processor

Academic Honesty •  All students admitted to the University of Florida have signed a

statement of academic honesty committing themselves to be honest in all academic work and understanding that failure to comply with this commitment will result in disciplinary action.

•  This statement is a reminder to uphold your obligation as a

student at the University of Florida and to be honest in all work submitted and exams taken in this class and all others.

•  Students requesting classroom accommodation must first register with the Dean of Students Office. The Dean of Students Office will provide documentation to the student who must then provide documentation to the instructor when requesting accommodation.

8

Lecture 1: Introduction

•  Moore’s Law •  CMOS Trends

Moore’s Law 161514131211109876543210

1959

1960

1961

1962

1963

1964

1965

1966

1967

1968

1969

1970

1971

1972

1973

1974

1975

LOG 2

OF

THE

NUMB

ER O

FCO

MPON

ENTS

PER

INTE

GRAT

ED F

UNCT

ION

Electronics, April 19, 1965.

“Digital Integrated Circuits,” 2nd Ed. © 2003 Prentice Hall/Pearson

In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months. He made a prediction that semiconductor technology will double its effectiveness every 18 months

9

Moore’s law in Microprocessors

4004 8008 8080

8085 8086 286

386 486 Pentium® proc

P6

0.001

0.01

0.1

1

10

100

1000

1970 1980 1990 2000 2010 Year

Tran

sist

ors

(MT)

2X growth in 1.96 years!

Transistors on Lead Microprocessors double every 2 years

Courtesy, Intel “Digital Integrated Circuits,” 2nd Ed. © 2003 Prentice Hall/Pearson

Memory Trends

10.7

mm

11.7mm

2kB

buf

fer &

cac

he

Cha

rge

pum

p

16896 bit lines

32 word lines x 1024 blocks

From [Nakamura02]

1Gbit flash memory

10

Feature Size

[Source: Gordon Moore, Intel, ISSCC]

Human hair, 100µm

Amoeba, 15µm

Red blood cell, 7µm

AIDS virus, 0.1µm

Die Size Trends

11

Die Size Growth

4004 8008

8080 8085

8086 286 386

486 Pentium ® proc P6

1

10

100

1970 1980 1990 2000 2010 Year

Die

siz

e (m

m)

~7% growth per year ~2X growth in 10 years

Die size grows by 14% to satisfy Moore’s Law


Frequency

Lead Microprocessors frequency doubles every 2 years

P6 Pentium ® proc

486 386 286 8086 8085

8080 8008 4004 0.1

1

10

100

1000

10000

1970 1980 1990 2000 2010 Year

Freq

uenc

y (M

hz)

Doubles every 2 years


12

Processor Supply Voltage


Static Power •  VDD decreases

–  Save dynamic power –  Protect thin gate oxides and short channels –  No point in high value because of velocity sat.

•  Vt must decrease to maintain device performance

•  But this causes exponential increase in OFF leakage

•  Major challenge

Processor Power (Watts) – Active and Leakage


13

Power Dissipation

P6 Pentium ® proc

486 386

286 8086

8085 8080 8008

4004

0.1

1

10

100

1971 1974 1978 1985 1992 2000 Year

Pow

er (W

atts

)

Lead Microprocessors power continues to increase


Power density

4004 8008 8080

8085

8086

286 386 486

Pentium® proc P6

1

10

100

1000

10000

1970 1980 1990 2000 2010 Year

Pow

er D

ensi

ty (W

/cm

2)

Hot Plate

Nuclear Reactor

Rocket Nozzle

Power density too high to keep junctions at low temp


14

Technology trends…pushing the limits

[slide from Ed Schlesinger, CMU]

Multi-core: 80 Tile Processor

Intel

15

(b)1980’s

n+

LDD

Gate

TiSi2

(a) 1970’s

Si Substrate

Al Gate

S D

(c) 2003

Strained channel

Si1-xGex

Gate NiSi

Device Enhancements

Gate Silicide added

Channel Strained silicon

High-k gate

dielectric

New transistor structure Transistor

Source: Intel

Gate Stack •  Traditional Oxide Scaling

–  XG=LG/45 –  70nm node, XG~2nm (6-7 atomic layers) –  Increased gate leakage

•  Introduce High-k Gate dielectrics –  Thicker oxide to reduce leakage –  Use high dielectric constants to maintain same capacitance per unit area

•  hafnium oxides HfO2 kx~30-40 •  zirconium oxides ZrO2 kx~25

•  Equivalent Oxide Thickness (EOT) –  EOT=(kSiO2/kx)tx

kSiO2 ~3.9 tx = physical oxide thickness

16

Strained Silicon and Silicides •  Higher mobility

–  Increases drive current and transistor speed –  Implant SiGe to stretch the Si lattice –  Yields up to 70% increase in mobility or 30%

improvement in performance

•  Silicide –  Polysilicon gate and Source/Drain regions have

high resistance •  Deposit metal on polygate and/or S/D

regions to decrease resistance (Tantalum, molybdenum, titanium, cobalt)

–  Polycide: only the gate is silicided –  Salicide (self-aligned silicidization): both polygate

and S/D regions are silicided

LDD and Isolation •  LDD – Lightly doped drain

–  Reduces the electric field at the drain junction –  Improves device immunity to hot electron damage –  LDD is shallow and increases series resistance

(decreases performance) –  Silicon Nitride spacer along the edge of gate serves

to mask n+/p+ S/D regions

•  LOCal Oxidation of Silicon (LOCOS) to isolate devices –  LOCOS produces Bird’s beak caused by

lateral diffusion of SiO2 –  Limits packing density due to extended

transition between thin and thick oxides •  Shallow Trench Isolation (STI)

–  180nm and below –  Improved packing density

17

90nm Process Interconnects

Source: Intel

Metal lines Al Cu

Insulating dielectric

(low-k)

Interconnects

M7

M5

M4

M3 M2 M1

M6

Low-K Dielectrics and Copper Interconnects

•  Low-K is used for Inter Layer Dielectrics (ILD) to decrease interconnect capacitance –  SiO2 dielectric constant k=3.9-4.2 –  Addition of Fluorine to SiO2 forms fluorosilicate glass

(FSG) and decreases k to ~3.6 •  Replace Al interconnects with Cu

–  up to 40% decrease in resistance

18

Process enhancements

•  Isolation, Reliability, Gate stack, Strained Si •  Low-k and copper interconnects •  Other enhancements

–  Multiple Vt transistors •  Low-Vt and high-Vt

–  Multiple Oxide thickness •  Core logic vs IO logic

–  Thick metal options –  Triple Well process

Summary

•  Number of transistors doubles ~18-24mo •  Die size increase by 14% every 2 years •  Frequency doubles every 2 years

–  But power limit… •  Leakage power is increasing as TOX decreases

(20% or more)…new devices •  Supply voltages have been steadily decreasing

–  But will remain at 1V or so •  Minimizing Power is essential

–  Different architectures, slower speeds, power gating…

Documents

EEE 6323 Advanced VLSI Design - University of Florida...Advanced VLSI Design Section: 0564 ... • Some useful tutorials for Analog Artist, Layout, Printing schematics/ waveforms and