EEL 4712 – Digital Design

Test 1 – Fall Semester 2016 Name _______________________

1

1. VHDL analysis (timing diagrams). Given the following VHDL specification, complete the following timing diagram for output Q.

LIBRARY ieee ; USE ieee.std_logic_1164.all ;

ENTITY Prob1 IS PORT ( D, CLOCK, X1, X2 : IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR(0 TO 3) ) ; END Prob1 ;

ARCHITECTURE P1Arch OF Prob1 IS BEGIN PROCESS (D,CLOCK) BEGIN IF CLOCK='1' THEN Q(0) <= D; END IF; END PROCESS; PROCESS (D, CLOCK) BEGIN IF CLOCK='1' THEN Q(1) <= D; ELSE Q(1) <= ‘0’; END IF; END PROCESS; PROCESS (CLOCK, X1) BEGIN IF X1 = ‘0’ THEN Q(2) <= ‘0’; ELSIF CLOCK = ‘1’ THEN Q(2) <= D; END IF; END PROCESS; PROCESS (CLOCK, X1) BEGIN IF X1 = '0' THEN Q(3) <= '0'; ELSIF CLOCK'EVENT AND CLOCK='1' THEN IF X2 = '0' THEN Q(3) <= '0'; ELSE Q(3) <= D; END IF; END IF; END PROCESS; END P1Arch ;

X1

X2

D

CLOCK

X1

X2

Q(0)

Q(1)

Q(2)

Q(3)

18 pts.

Important Note:

Every flip-flop and latch starts off with an unknown value (use ??)

Please show propagation delays.

IMPORTANT: Throughout this test, please be neat and write (or draw) carefully. If we cannot read it with a reasonable effort, it is assumed to be wrong.

EEL 4712 – Digital Design

Test 1 – Fall Semester 2016 Name _______________________

2

2. Using the GENERIC feature of VHDL, complete the following code that will define a “generic” component named genMUXDff shown in Figure 3(a). The generic component has N “slices”, each of which contains a D flip-flop and a 2-to-1 MUX as shown in Figure 3(b). Also, the output ZFlag is true when all the D flip-flops contain ‘0’.

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all;

ENTITY genMUXDff IS

GENERIC (N: INTEGER :=8) END genMUXDff;

ARCHITECTURE genArch OF genMUXDff IS

SIGNAL

BEGIN

PROCESS ( ) -- All code must be inside a single

-- PROCESS block

X

Y

S

Z

ZFlag

N N

N

genMUXDff

Figure 3(a)

END PROCESS; END genArch;

0

1

D Q

X(0)

Y(0)

S

Z(0)

0

1

D Q

X(N-1)

Y(N-1)

S

Z(N-1)

Figure 3(b)

…

10 pts.

EEL 4712 – Digital Design

Test 1 – Fall Semester 2016 Name _______________________

3

3. Given the following “non-sense” VHDL code, draw the corresponding circuit.

ENTITY Test1P3 IS

PORT ( PB, CLK : IN STD_LOGIC; Z : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); END Test1P3;

ARCHITECTURE Behavior OF Test1P3 IS

SIGNAL Q : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL tempAND : STD_LOGIC;

COMPONENT MyComp

PORT ( A : IN STD_LOGIC; B : IN STD_LOGIC_VECTOR (2 DOWNTO 0); outData : OUT STD_LOGIC_VECTOR (2 DOWNTO 0));

END COMPONENT; BEGIN PROCESS(PB)

BEGIN IF ( CLK’EVENT AND CLK = '1' ) THEN

FOR i IN 0 TO 2 loop Q(i) <= Q(i+1); tempAND <= Q(i) AND tempAND; end loop;

Q(3) <= PB;

Z(0) <= tempAND;

END IF;

END PROCESS;

MyComp PORT MAP (PB,Q(2 DOWNTO 0), Z(3 DOWNTO 1));

Z(0) <= tempAND

END Behavior;

Draw your circuit here:

16 pts.

EEL 4712 – Digital Design

Test 1 – Fall Semester 2016 Name _______________________

4

4. Complete the VHDL code below to design an N-bit left-shift register. CLR LD SH Function

1 X X asynchronously clear shift register (X means “don’t care”) 0 1 X synchronously load D into the shift register 0 0 1 shift left (input X goes into right-most flipflop) 0 0 0 hold

ENTITY leftNshift IS PORT ( D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; Clock, CLR, LD, SH, X : IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;

END leftNshift ; ARCHITECTURE Behavior OF leftNshift IS BEGIN

16 pts.

EEL 4712 – Digital Design

Test 1 – Fall Semester 2016 Name _______________________

5

5. VHDL testbench analysis.

Please complete the test bench code on the next page using the following specifications:

Part A: Complete the PORT MAP statement to make the appropriate connections to the unit under test (UUT). (3 pts.)

Part B: Specify a statement to convert “value” to the appropriate signal type. (2 pts.)

Part C: What should be in this box? (1 pt.)

Part D: Specify the correct parameters for the function call to mux4to1Func. (4 pts.)

Part E: Complete the following timing diagram to show 8 iterations (i = 3 to 10) of the FOR LOOP from the code on the next page (6 pts.)

Do not draw waveforms; just put in the value 0 or 1 in the box. For example:

16 pts.

Name 0ns 50ns 100ns 150ns 200ns 250ns 300ns 350ns 400ns 450ns 500ns 550ns

S(1)

S(0)

t(0)

t(1)

t(2)

t(3)

Z

1

0

1

1

0

0

1

EEL 4712 – Digital Design

Test 1 – Fall Semester 2016 Name _______________________

6

5. (continued)

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.numeric_std.all;

ENTITY mux4to1WithAssert_tb IS

END mux4to1WithAssert_tb;

ARCHITECTURE behavior OF mux4to1WithAssert_tb IS

SIGNAL Z : STD_LOGIC;

SIGNSL t : STDLOGIC_VECTOR (0 TO 3);

SIGNAL s : STD_LOGIC_VECTOR (1 DOWNTO 0);

SIGNAL value : STD_LOGIC_VECTOR (5 DOWNTO 0);

BEGIN

UUT : ENTITY work.mux4to1

PORT MAP (

);

STIM_PROC: PROCESS

BEGIN

FOR i in 0 TO 63 LOOP

t(3) <= value(5);

t(2) <= value(4);

t(1) <= value(3);

t(0) <= value(2);

s(1) <= value(1);

s(0) <= value(0);

WAIT FOR 50 ns;

ASSERT( = mux4to1Func ( ))

REPORT "Error : output f incorrect for s1,s0 = " & STD_LOGIC'IMAGE

(value(1)) & STD_LOGIC'IMAGE (value(0)) & "and w = " & STD_LOGIC'IMAGE

(value(5)) & STD_LOGIC'IMAGE (value(4)) & STD_LOGIC'IMAGE (value(3)) &

STD_LOGIC'IMAGE (value(2)) SEVERITY WARNING;

END LOOP; -- i

WAIT FOR 500ns;

REPORT "SIMULATION FINISHED!";

WAIT;

END PROCESS;

END;

FUNCTION mux4to1Func (

SIGNAL sel : STD_LOGIC_VECTOR

(1 DOWNTO 0))

SIGNAL a,b,c,d:STD_LOGIC;

RETURN STD_LOGIC IS

BEGIN

CASE sel IS

WHEN "00" =>

RETURN d ;

WHEN "01" =>

RETURN c ;

WHEN "10" =>

RETURN b ;

WHEN OTHERS =>

RETURN a ;

END CASE ;

END mux4to1Func;

Part A

Part B

Part D Part C

COMPONENT mux4to1

PORT (w0,w1,w2,w3: IN STD_LOGIC;

s: IN STD_LOGIC_VECTOR

(1 DOWNTO 0) ;

f:OUT STD_LOGIC );

END mux4to1;

EEL 4712 – Digital Design

Test 1 – Fall Semester 2016 Name _______________________

7

6. VHDL specification. Complete the VHDL specification (below and on the next page) for the following circuit:

Notes:

REG is an 8-bit storage register with a synchronous CLR and synchronous LD inputs (LD has priority over CLR).

There are eight 2-to-1 MUX’s.

The INCR module is like a very simple ALU with only two functions:

If INC = 0, F <= X,

If INC = 1, F <= X + 1 (i.e., increment X).

All signals are active high.

(a) Complete the following Entity declaration for the Prob6 Module: (2 pts)

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_unsigned.all;

ENTITY Prob6 IS

-- Declare ZOut to be an OUT signal type.

PORT(

END Prob6;

(b) On the next page, complete the architecture section to specify the behavior of the Prob6 Module in behavioral VHDL. (22 pts)

DATA

CLR Q

LD

8

8

0 1

2-to-1

MUX’s

SEL

INCR

X F 8

8

INC

CLR

LD

CLOCK

InData

SEL

INC

ZOut

REG

Prob6 Module

8 Z

24 pts.

EEL 4712 – Digital Design

Test 1 – Fall Semester 2016 Name _______________________

8

6. (continued)

ARCHITECTURE behaviorArch OF Prob6 IS

SIGNAL

BEGIN

PROCESS -- You have to use this process for the REG module (8 pts)

BEGIN -- Also, you must use a WAIT UNTIL statement to specify the component REG

END PROCESS;

PROCESS -- Use this process for the MUX and INCR modules (16 pts) BEGIN -- Hint: you can specify both MUX and INCR modules in a single CASE statement

END PROCESS

END behaviorArch;

EEL 4712 – Digital Design

Test 1 – Fall Semester 2016 Name _______________________

9

ENTITY __entity_name IS PORT(__input_name, __input_name : IN STD_LOGIC; __input_vector_name : IN STD_LOGIC_VECTOR(__high downto __low); __bidir_name, __bidir_name : INOUT STD_LOGIC; __output_name, __output_name : OUT STD_LOGIC); END __entity_name; ARCHITECTURE a OF __entity_name IS SIGNAL __signal_name : STD_LOGIC; SIGNAL __signal_name : STD_LOGIC; BEGIN -- Process Statement -- Concurrent Signal Assignment -- Conditional Signal Assignment -- Selected Signal Assignment -- Component Instantiation Statement END a; SIGNAL __signal_name : __type_name; __instance_name: __component_name GENERIC MAP (__component_par =>__connect_par) PORT MAP (__component_port => __connect_port, __component_port => __connect_port);

WITH __expression SELECT __signal <= __expression WHEN __constant_value, __expression WHEN __constant_value, __expression WHEN __constant_value, __expression WHEN __constant_value; __signal <= __expression WHEN __boolean_expression ELSE __expression WHEN __boolean_expression ELSE __expression; IF __expression THEN __statement; __statement; ELSIF __expression THEN __statement; __statement; ELSE __statement; __statement; END IF; WAIT UNTIL __expression; CASE __expression IS WHEN __constant_value => __statement; __statement; WHEN __constant_value => __statement; __statement; WHEN OTHERS => __statement; __statement; END CASE;

Conditional assignment statement

SELECT assignment statement

<generate_label>: FOR <loop_id> IN <range> GENERATE -- Concurrent Statement(s) END GENERATE;

<optional_label>: FOR <loop_id> IN <range> LOOP -- Sequential Statement(s) END LOOP;

Generic-length zeroes:

Z <= (OTHERS => ‘0’);

IF X = (OTHERS => ‘0’)

EEL 4712 – Digital Design

Test 1 – Fall Semester 2016 Name _______________________

10

EEL 4712 – Digital Design

Test 1 – Fall Semester 2016 Name _______________________

11

IMPORTANT: Please be neat and write (or draw) carefully. If we cannot read it with a

reasonable effort, it is assumed wrong.

COVER SHEET:

Problem: Points:

1 (18 pts)

2 (10 pts)

3 (16 pts)

4 (16 pts)

5 (16 pts)

6 (24 pts)

Re-Grade Information:

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