ELECTRONICS LABORATORY EXPERIMENT 6

FET and FET BIASING PURPOSE In this lab, the nonlinear model parameters for a JFET will be determined experimentally, and JFET biasing circuits will be studied. THEORY There are three commonly used dc models for the JFET, which is a nonlinear three terminal semiconductor device. In these models VP is pinch-off (or threshold) voltage and IDSS is maximum drain current with VGS=0 V. These parameters differ from device to device. They are also affected by device temperature. Equivalent circuits for the models are given in Figure 3.1. The models correspond to the following modes:

a) VGS< VP Cutoff mode: IG=0 ID=0

b) 0 ≥ VGS ≥ VP , VDS < VGS -VP Triode mode or “ohmic” mode:

IG=0

If the voltage VDS is small the last term in brackets in the last equation above is neglected. If this is the case, the relationship between ID and VDS becomes “ohmic”:

ID ≈ DS

DS

RV

Where,

RDS = )(2

2

PGSDSS

P

VVIV

−

c) 0 ≥ VGS ≥VP , VDS > VGS -VP Constant current mode or “active” mode:

IG = 0

In an equivalent alternative notion, the transconductance parameter K and the threshold voltage VTR are used:

K= 2P

DSS

VI

VTR=VP

With these parameters, the drain current in triode and constant current modes is expressed as follows: VDS<VGS-VTR ID=K[2(VGS-VTR)VDS-VDS

2] VDS>VGS-VTR ID=K(VGS -VTR)2

Figure 3.1: N channel JFET equivalent circuits: a) Cutoff mode b) Triode mode c) constant current mode

In analog circuits, the JFET is operated in the constant current mode. For this purpose a biasing circuit is utilized. Three bias circuits are given in Figure 3.2 . The formation of the operating point for each bias circuit is also given in the figure. The JFETs in the circuits are operated in the constant current mode. The circuit in Figure 3.2a is the simplest biasing circuit; however, it uses two voltage sources. In this circuit VGS equals VGG, and for a given JFET, the drain current is determined uniquely. In such a circuit, the operating point of the JFET is affected greatly by the possible changes in the device parameters. The shaded region in Figure 3.2a indicates the area in which the transfer characteristics of the JFET may fall.

The self biasing circuit in Figure 3.2b uses single power supply.The voltage drop developed by the drain current across RS sets VGS. Possible shifts in the operating point due to the changes in device parameters are reduced. The voltage divider biasing circuit is a combination of the aforementioned two bias circuits. The voltage divider sets the gate voltage; the drain current develops the source voltage across RS and sets VS. The difference of these two voltages determine the voltage VGS. In this bias circuit, the possible range for the operating point is still narrower than that of the other circuits.(Figure 3.2c).

PRE-LAB a) Get a n-channel JFET (BF245, VP=-1.4 K=0.001326). b) Using your JFET, design three bias circuits that are given in the introduction so that in each circuit ID=1 mA VDS= 3 V . c) Using a simulation program find the operating point of each circuit that you designed. PROCEDURE 1) Using the circuit in Figure 3.3, measure IDSS and VP parameters for your JFET. Make sure that JFET operates in the constant current mode. 2) Build the circuits that you designed in the preliminary work section. Determine the operating point of the transistors experimentally and compare it with the theoretical operating points.