EEN1032: DIGITAL LOGIC DESIGN - Faculty of …foe.mmu.edu.my/v3/lab/lab sheet/TRIM3/BETA/EEE1036-DL1... · Web viewEEE1036: DIGITAL LOGIC DESIGN EXPERIMENT 2: Flip-flops and Their

EEE1036: Digital Logic Design, Lab Exp. DL2__________________________________________________________________________________________

EEE1036: DIGITAL LOGIC DESIGNEXPERIMENT 2: Flip-flops and Their Applications

Objective

The objective of this experiment is to introduce students to flip-flops and their applications.

Note: There are three parts in this experiment. They are: 1. JK flip-flop 2. Ripple binary counter using JK Flip-flop 3. Synchronous binary counter using JK Flip-flop

You are required to complete all of them.

Preparation Before starting the experiment, make sure that you have the following equipment and components.

Equipment 1. DC power supply - 1 2. Function Generator -1 3. Oscilloscope - 1

Components 1. Breadboard - 1 2. IC 7408 (quad AND gate) - 1 3. IC 7473 (dual J-K flip-flop) - 2 4. Resistor 1.2K - 35. Resistor 4.7K - 36. LED - 37. Function generator probe - 1 8. Oscilloscope probe - 1

Experiment 2A: Design of JK Flip-flop (30 minutes)

A sequential circuit has memory or storage capacity. The next outputs of a sequential circuit depend on its inputs as well as its present state (memory). Flip-flops are the basic building blocks of sequential circuits. Common flip-flop types are SR, D, JK and T. The JK flip-flop is regarded as the most versatile one. It can be used as SR, D or T flip-flop. A characteristic table of JK flip-flop is given in Table 2.1. A schematic symbol of JK flip-flop is given in Fig. 2.1

Table 2.1 JK flip-flop characteristic tableClock J K Present state Next state Mode of operation

0 x x Q0 Q0 hold↓↓↓↓

0 00 11 01 1

Q0

Q0

Q0

Q0

Q0 0 1

Q0’

hold resetset

toggle

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Fig 2.1 JK flip-flop

Experimental Procedures

This part of the experiment will examine the functional behavior of JK flip-flop. The experiment setup is shown in Fig 2.2.

Fig 2.2 JK flip-flop test setup

1. Get ready the power supply: Set the output voltage to +5V. Set the current adjustment knob to about ¼ turn from the min position. Consult the lab instructor if you have doubts.

2. Make sure that the power supply is turned off. Connect two jumper wires from the DC power supply's positive (red) and negative (black) terminals to +5V and GND lines on the breadboard, respectively.

3. Fix one 7473 IC onto the breadboard. Mind the IC placement; later, you will need to fix 2 more ICs onto the same breadboard.

4. Connect pin 4 of 7473 IC to +5V.5. Connect pin 11 of 7473 IC to GND. 6. Complete the circuit connections as shown in Fig 2.2. Use jumper wires as switches (S1,

S2 and Reset).

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J

K

QSET

CLR Q

2 Hz

2

1

3

14

12

Reset

+ 5 V

SYNC OUT output at the rear panel of function generator

Squared pulses from

CH2Oscilloscope

CH1Oscilloscope

4.7K

S2

+ 5 V

4.7K

7473

QCLR

SET Q

K

JS1

4.7K

1.2K

2 Hz2 Hz2 Hz2 Hz2 Hz2 Hz2 Hz2 Hz2 Hz2 Hz


Observations:I. Complete Table R2.1. Check your results against Table 2.1.

7. Get ready the function generator: Set the function generator to square pulse mode. Select the 10 Hz frequency range. Set the function generator's frequency to about 2 Hz.

8. Make sure that the function generator is turned off. Connect the function generator probe to the function generator’s SYNC OUT located at the rear panel (this output is TTL compatible).

9. Connect the positive (red) terminal of the probe to pin 1 of IC 7473.10. Connect the negative (black) terminal of the probe to GND. 11. Get ready the oscilloscope: Set the time base scale to 0.5 ms/div and the vertical scale to 5

V/div. Make sure that the knobs are at the CAL position.12. Connect the clock input and the flip-flop output to oscilloscope channel 1 (CH1) and

channel 2 (CH2), respectively, as indicated in Fig 2.2. 13. Verify your connections again. 14. Now you are ready for the experiment. Turn on the DC power supply. 15. Turn on the function generator.

Observations: II. Keep S1 and S2 in the OPEN (1) state. Increase the clock frequency to 1KHz.

Record the waveform of the flip-flop output Q (CH2) relative to the clock. Record also the waveform frequencies.

III. When is the flip-flop output Q changes state?IV. Hold the reset button in closed (0) position. Observe and record the change of the

waveform of the flip-flop output Q (CH2).

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J

K

QSET

CLR Q

Clock

‘1’

(a) (b)

Clock

Q


Experiment 2B: Application of Flip-Flop – Design of Binary Counter

A counter is a kind of sequential circuit. It counts the input pulses appearing at its input. Counters can be designed in many different ways. Two basic types that will be covered in this experiment are:

1. Ripple binary counter and 2. Synchronous binary counter

2B.1: Design of Ripple Binary Counter using JK Flip-flops (45 minutes)

In a ripple or asynchronous counter, the change of state of each stage is triggered by state change in its previous stage. Such counters are easy to design. Its main disadvantage is that it is a slow counter. Toggle (T) flip-flops are used to design the counter circuit. A T flip-flop can be constructed from a JK flip-flop by tying its JK inputs together to VCC, as shown in Fig 2.3.

Fig 2.3 (a) Toggle flip-flop and (b) output waveform

In this experiment, you will construct a 3-bit ripple binary counter. A 3-bit counter requires 3 T flip-flops. One 7473 IC contains 2 JK flip-flops. Therefore, you need two 7473 ICs. The circuit diagram is shown in Fig 2.4.

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Fig 2.4 3-bit ripple binary counter


1. Make sure that the power supply and the function generator are turned off. 2. Continued from the previous experiment, fix another 7473 ICs onto the breadboard. Mind

the IC placement; later, you will need to fix one more IC onto the same breadboard.3. Connect pin 4 and pin 11 of this second IC to +5V and GND, respectively.4. Complete the circuit connections as shown in Fig 2.4. 5. Set the function generator's frequency to 2 Hz. 6. Verify your connections again. 7. Now you are ready for the experiment. Turn on the DC power supply. 8. Push the reset button to reset all the flip-flops. It will turn off all the LEDs. 9. Turn on the function generator.

Observations: I. Complete Table R2.2.

II. Using the oscilloscope, record the waveforms at Q0, Q1 and Q2 relative to the clock.

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IC-BIC-A

2 Hz

LSB MSB

Q1Q2Q0

+5 V

Reset

(SYNC OUT)

4.7K9

6

10

57

7473

QCLR

SET Q

K

J12

2

3

1

147473

QCLR

SET Q

K

J

1.2K1.2K

12

2

3

1

147473

QCLR

SET Q

K

J

1.2K


2B.2: Design of Synchronous Binary Counter using JK Flip-flops (1 hour)

A synchronous binary counter's states change synchronously with the clock. It is faster than ripple binary counters. All flip-flops in a synchronous binary counter share a common clock. A 3-bit synchronous binary counter circuit is shown in Fig 2.5.

Fig 2.5 3-bit synchronous binary counter


1. Make sure that the power supply and the function generator are turned off. 2. Continued from the previous experiment, fix one 7408 IC onto the breadboard and

connect its pin 14 to +5V and pin 7 to GND.3. Complete the circuit connections as shown in Fig 2.5.4. Verify your connections again. 5. Now you are ready for the experiment. Turn on the DC power supply unit. 6. Push the reset button to reset all the flip-flops. It will turn off all the LEDs. 7. Turn on the function generator.

Observations: I. Complete Table R2.3.

II. Using the oscilloscope, record the waveforms at Q0, Q1, Pin 3(7408) and Q2 relative to the clock.

III. Describe the function of the AND gate.IV. If a clock frequency fclk is applied to an n-bit binary counter, what is the frequency

of the final stage flip-flop output (Qn-1)? Show your derivation. The waveforms can help you in this derivation.

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2 Hz

12

2

3

114

7473

QCLR

SET Q

K

J

ICB

MSB

Q2

1.2K

ICA 32

1 7408

LSB

Q1Q0

1.2K1.2K

+5 V

Reset

(SYNC OUT)

4.7K

9

6

10

57

7473

QCLR

SET Q

K

J12

2

3

114

7473

QCLR

SET Q

K

J


APPENDIX

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Testing AND gate: Each AND gate is tested according to the truth table.

Input Output0 0 00 1 01 0 01 1 1

Input connected to ground is logic 0.Input not connected to ground is logic 1.Use 1.2K+LED or multimeter (V mode) to

indicate output state.

Pin layout for 7408 quad 2-input AND gates

Pin Layout for 7473 Dual J-K Flip-Flop

Testing J-K flip-flop: Use Fig 2.2 and operate the flip-flop in toggle mode.1. Connect input J, input K and CLR to +5V.2. Test the flip-flop using clock and 1.2K + LED.

The LED will be ON and OFF alternately.3. Disconnect CLR from +5V and connect it to

GND. The LED will be OFF regardless the clock trigger.

EEE1036: Digital Logic Design, Lab Exp. DL2 result and mark sheets Student ID ……………………… Name ………………………………….. Major ………………………….

EXPERIMENTAL RESULTS AND DISCUSSIONS

Exp. 2A: JK flip-flop

I. Table R2.1: Observation results of J-K flip-flop

Operational sequence S1 S2 LED (ON/OFF)

Mode of operation

0 (Push the reset button) CLS (0) CLS (0) OFF

1 (Release the reset button) CLS (0) CLS (0)

2 OPEN (1) CLS (0)

3 CLS (0) CLS (0)

4 CLS (0) OPEN (1)

5 CLS (0) CLS (0)

6 OPEN (1) OPEN (1)

II. Fig R2.1: Measured waveforms of clock and J-K flip-flop output Q

Clock

J-K flip-flop output Q

III. When is the flip-flop output Q changes state?

IV. When the reset button is held in closed position, what is the output Q of the J-K flip-flop?

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f = _______Hz

f = _______Hz


Exp. 2B.1: Ripple binary counter

I. Table R2.2: Observation results of the ripple binary counter(Use binary 0 to represent LED OFF and binary 1 to represent LED ON)

Sequence No./Clock Pulse No.

MSBQ2 Q1

LSBQ0 Decimal

0 (Push the reset button) 0 0 0 0

1 (Release the reset button)

2

3

4

5

6

7

8

9

10

II. Draw the waveforms at Q0, Q1 and Q2 relative to the clock.

Pulse No. 0 1 2 3 4 5 6 7 8 9 10

Clock

Q0

Q1

Q2

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Exp. 2B.2: Synchronous Binary Counter

I. Table R2.3: Observation results of the synchronous binary counter

Sequence No./Clock Pulse No.

MSBQ2 Q1

LSBQ0 Decimal

0 (Push the reset button) 0 0 0 0

1 (Release the reset button)

2

3

4

5

6

7

8

9

10

II. Draw the waveforms at Q0, Q1, Pin 3(7408) and Q2 relative to the clock.

Pulse No. 0 1 2 3 4 5 6 7 8 9 10

Clock

Q0

Q1

Pin 3(7408)

Q2

III. Describe the function of the AND gate.

IV. If a clock frequency fclk is applied to an n-bit binary counter, what is the frequency of the final stage flip-flop output (Qn-1)? Show your derivation.

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EEN1032: DIGITAL LOGIC DESIGN - Faculty of …foe.mmu.edu.my/v3/lab/lab sheet/TRIM3/BETA/EEE1036-DL1... · Web viewEEE1036: DIGITAL LOGIC DESIGN EXPERIMENT 2: Flip-flops and Their