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Materials Science in Semiconductor Processing

Materials Science in Semiconductor Processing 14 (2011) 13–17

1369-80

doi:10.1

n Corr

E-m

journal homepage: www.elsevier.com/locate/mssp

Effects of post-oxidation annealing temperature on ZrO2 thin filmdeposited on 4H-SiC substrate

Tedi Kurniawan a, Yew Hoong Wong a, Kuan Yew Cheong a,n, Jeong Hyun Moon b, Wook Bahng c,Khairunisak Abdul Razak a, Zainovia Lockman a, Hyeong Joon Kim b, Nam-Kyun Kim c

a Energy Efficient & Sustainable Semiconductor Research Group, School of Materials & Mineral Resources Engineering, Engineering Campus,

Universiti Sains Malaysia, 14300 Nibong Tebal, Penang, Malaysiab Department of Materials Science and Engineering, College of Engineering and Inter-university Semiconductor Research Center, Seoul National University,

Seoul 151-744, Republic of Korea.c Center for Energy Efficient Semiconductors, Korea Electrotechnology Research Institute, P.O. Box 20, Changwon, Gyungnam 641-120, Republic of Korea

a r t i c l e i n f o

Available online 15 January 2011

Keywords:

Wide-bandgap semiconductor

High dielectric constant oxide

Post-oxidation annealing

01/$ - see front matter & 2010 Elsevier Ltd. A

016/j.mssp.2010.12.011

esponding author. Tel.: +604 599 5259; fax:

ail address: cheong@eng.usm.my (K. Yew Che

a b s t r a c t

ZrO2 thin film has been formed on n-type 4H-SiC substrate using a combination of metal

sputtering (�25 nm thick) and thermal oxidation (15 min at 500 1C) processes. Effects of

post-oxidation annealing temperature (600–900 1C) on the physical and electrical

properties of the thin film have been investigated. High resolution transmission electron

microscopy attached with energy dispersive X-ray has been used to examine cross-

sectional morphology and to study element chemical distribution of the investigated

region. Selected area diffraction analysis has been employed to examine crystallinity of

the samples. Metal-oxide-semiconductor capacitors have been fabricated to examine

leakage current through the oxide using current–voltage measurement. Oxide-semi-

conductor interface-trap density has been extracted using capacitance–voltage measure-

ment. The annealing process reduced leakage current density as low as one order of

magnitude. However, breakdown voltage of the oxide has been reduced. Dielectric

constant extracted from this work ranges from 22 to 80, depending on the annealing

temperature.

& 2010 Elsevier Ltd. All rights reserved.

1. Introduction

Silicon carbide (SiC) metal-oxide-semiconductor (MOS)based devices are developed for high-temperature, high-power, and/or high-radiation applications [1]. The formationof high quality gate oxide is one of the most important factorsthat determine the success of this device [2]. Silicon dioxide(SiO2), as a native oxide of SiC, grown by thermal nitrida-tion process has revealed excellent properties to serve thispurpose [3]. Due to relatively low dielectric constant of thenitrided oxide (3.9), it is unable to withstand a high electricfield, which is imposed vertically on the gate. The maximum

ll rights reserved.

+604 594 1011.

ong).

blocking voltage of such structure is limited by the gate oxidebreakdown instead of the breakdown field of SiC. This isbecause electric field in the oxide is larger than that in SiC by afactor of 2.5, which is equal to the ratio of their dielectricconstants [4,5]. This poses a serious reliability problem for thegate oxide. Therefore, alternative gate oxide with a higherdielectric constant (high-k dielectric) becomes an alternativeway to solve this problem. Zirconium dioxide (ZrO2) seems tobe one of the attractive candidates due to its excellent bulkproperties such as high-k value (k=20–25) and wide energybandgap (4.7–5.8 eV) [6,7]. This material has shown goodcharacteristics when it is applied as gate oxide on Si-basedsubstrate [7–16]. However, information on this materialdeposited on SiC substrate is very limited. Karlsson et al.[17] deposited ZrO2 by chemical vapor deposition (CVD) onSiC (0 0 0 1). Heterogeneous layer was formed after being

20

Inte

nsity

(a.u

)

800°C

700°C

600°C

900°C

t-ZrO2(011)

m-ZrO2(-111)SH 4H-SiC

(004)

As-Ox 500°C

2θ (deg)25 30 35 40

Fig. 1. XRD pattern of annealed as-oxidized samples at different tempera-

tures: (a) 600 1C, (b) 700 1C, (c) 800 1C, and (d) 900 1C.

T. Kurniawan et al. / Materials Science in Semiconductor Processing 14 (2011) 13–1714

annealed at 1000 1C because of the decomposition of ZrO2;thus it leads to the formation of t-ZrO2 remnants, metallic Zrsilicide, and Si aggregates. No electrical result was reportedfrom that work. Therefore, further understanding in exploringthe correlation between physical and electrical properties ofZrO2 on SiC-based substrate is essential and it is reported inthis work. ZrO2 has been formed by a combination of directsputtered Zr on SiC substrate and continued by thermaloxidation process. Correlation between physical and elec-trical properties of the oxide is investigated and reported.

2. Experimental

N-type 4H-SiC substrates were cleaned by RCA cleaningmethod followed by dipping in HF in order to remove thenative silicon dioxide on the surface. Zirconium thin filmswere deposited by DC magnetron sputtering for 60 s sput-tering time. During the sputtering, base pressure, workingpressure, and DC power were regulated at 4.4�10�5 Torr,3–6�10�3 Torr, and 250 W, respectively. Samples werethen inserted into a tube furnace at 500 1C for 15 min withan oxygen gas flow rate of 150 ml/min, followed by post-oxidation annealing in Ar gas environment for 30 min attemperature range of 600–900 1C.

Structural properties of the oxide were analyzed by ahigh resolution X-ray diffraction (HR-XRD) system (PANa-lytical X’Pert PRO MRD PW3040). High resolution transmis-sion electron microscope (HRTEM) (Tecnai G2 F30) wasused to characterize the cross-sectional areas of the sam-ples. Prior to this, Pt was deposited on the sample surface toprotect the surface from ion bombardment damage causedby focusing ion beam during lamella preparation. Selectivearea diffraction (SAED) was then performed to study thecrystallinity of the layers. Diffraction pattern from thismeasurement was calculated by fast Fourier transform (fft)method and presented in the diffraction images. Thechemical composition of the samples was determined byX-ray energy dispersive (EDX) analysis using an EDAXdetector.

For electrical characterizations, sample was first sub-jected to photolithography process to form capacitor withan array of area of 9�10-4 cm2. Capacitance–voltage (C–V)measurement was conducted by an Agilent 4284A Preci-sion LCR Meter from 0 to 20 V in dual step mode. Mean-while, current–voltage (I–V) measurement was performedby an Agilent Precision Semiconductor Parameter Analyzer(SPA) by applying voltage from 0 to 40 V in sweep modewith frequency of 50 Hz.

3. Results and discussion

XRD patterns of as-oxidized sample and annealed samplesin a scanned range of 2y=20–401 are presented in Fig. 1. Peakat 251 belongs to sample holder (SH). Samples annealed at600 and 700 1C show the same XRD patterns as those of theas-oxidized sample, in which the peak of monoclinic-ZrO2

(m-ZrO2) phase in (�1 1 1) plane is observed at 28.251 (ICDD:00-013-0307). As the annealing temperature increases to800 1C, m-ZrO2 phase is transformed into tetragonal-ZrO2

(t-ZrO2) (0 1 1) as the peak changes to 30.21 (ICDD: 00-050-1089). Furthermore, sample annealed at 900 1C possesses

both m-ZrO2 and t-ZrO2 phases. The existence of m-ZrO2 maybe originated from amorphous phase of ZrO2 that has notbeen fully crystallized at temperature below 900 1C. Thisresult indicates that annealing temperature would inducephase transformation of ZrO2. The same result has beenreported by He et al. [18], in which different orientations ofcrystallites and increment of intensity of the particular peakhave been observed during annealing in O2 atmosphere attemperature ranging from 600 to 900 1C.

Cross-sectional area of as-oxidized sample of HRTEMdark field image and its respective line-scan of EDX arepresented in Fig. 2. Result of the EDX analysis shows thatsample can be divided into four different layers, which areSiC, interfacial layer (IL), ZrO2, and Pt. The chemical compo-sitions in the IL may consist of SiOx and/or ZrxSiyOz. In orderto provide more structural information on the layers,HRTEM bright field images of the as-oxidized sample andsample annealed at 900 1C are presented in Fig. 3. It can beseen in Fig. 3(a), as-oxidized sample consists of ZrO2 with athickness of approximately 35 nm and an interfacial layer inbetween ZrO2 and SiC with a thickness of approximately2.5 nm. Furthermore, SAED was performed to study thecrystallinity of the layers. Diffraction pattern from thismeasurement has been calculated by fast Fourier transform(fft) method and the result is presented in diffractionimages. The existence of many spots pattern in the fft imageindicates that ZrO2 layer is in the partially polycrystallineform. The fft images of interfacial layer and SiC substrateshow both amorphous (cloudy spots) and single crystalpatterns (patterned spots), respectively. Fig. 3(b) shows thatthickness of interfacial layer is increased to approximately10 nm for sample annealed at 900 1C. The high annealingtemperature is presumed to enhance the diffusion of Siatoms toward the Si/interfacial layer interface and form SiOx

and/or ZrxSiyOz [19]. SAED analysis of the sample also givesthe same crystallinity characteristics as what has beenshown in Fig. 3(a).

Typical high-frequency C–V characteristics are pre-sented in Fig. 4. Samples annealed at 600–900 1C haveincreased the level of capacitance oxide (Cox) if compared

ZrO2

Pt

IL

SiC

Pt

ZrO2

IL

SiC

Fig. 3. HRTEM images of (a) as-oxidized sample and (b) after annealed

at 900 1C. Inset of the images shows the SAED pattern. IL represents

interfacial layer.

Point

0

Inte

nsity

(a.

u.)

1

10

100

1000

Pt L

C K

Si K

O K

Zr K

SiC IL Pt

SiC ZrO2 Pt

20 40 60 80 100

ZrO2

IL

Fig. 2. (a) HRTEM dark field image and (b) EDX analysis of cross section

area for as-oxidized sample.

T. Kurniawan et al. / Materials Science in Semiconductor Processing 14 (2011) 13–17 15

with the Cox level obtained from as-oxidized sample. Basedon the formula given below [20]:

Cox ¼keoA

dð1Þ

The increment of capacitance would come from higher kvalue, larger capacitor area (A), or thinner oxide layer (d).Since the capacitor area in this work is constant and thereduction in oxide thickness during annealing in Ar ambientis not possible, the increment of Cox may be due to incrementof k value. The C–V curves have a huge parallel shift topositive bias (9.7–10.7 V). To clarify the result, calculatedeffective oxide charge (Qeff) of each sample is shown in Fig. 5.It is found that the shift was caused by a huge amount ofnegative charge (in the order of 13) trapped in the oxide.Calculated slow trap density (STD) values of all annealedsamples are presented in Fig. 6. It shows that STD of thesamples is only in the order of 11 owing to the smallhysteresis (1–18 nV) between forward and reverse of theC–V curves. Dit for the as-oxidized and annealed samples atdifferent temperatures (600–900 1C) is presented in Fig. 7.Dit decreases as the energy differences from conductionband edge (Ec) increase. In general, the Dit values of annealedsamples are higher than those of as-oxidized sample.

Dielectric constants (k) of as-oxidized and annealedsamples are presented in Fig. 8. Total thickness of the oxidefor all annealed samples is assumed to be the same with as-oxidized sample, which is 37.5 nm (as has been measured

from TEM image). It is shown that k values for annealedsamples are higher if compared to the value of as-oxidizedone. On the other hand, the k values of annealed samplesare more than two times higher if compared with bulk ZrO2

(k=25). This k value has the same characteristic with ZrO2

on Si substrate (by plasma-assisted catholic arc deposition)reported by Li et al. [21], with dielectric constants between7.5 and 55. It is well known that the dielectric layer stronglydepends on oxide–substrate interface characteristics, nat-ure of the substrate and electrode materials, and oxidedeposition method [21].

Bias (V)0

Cap

acita

nce

(pF)

0200400600800

100012001400160018002000

ForwardReverse

2 4 6 8 10 12 14

800°C

700°C

600°C

900°C

As-Ox 500°C

Fig. 4. Comparison of high-frequency C–V characteristic of as-oxidized

sample and samples annealed at different temperatures (600–900 1C).

Annealing Temperature (°C)As-Ox 500

Effe

ctiv

e ox

ide

Cha

rge

Qef

f (x

1013

cm

-2)

-12.0

-10.0

-8.0

-6.0

-4.0

-2.0

600 700 800 900

Fig. 5. Effective oxide charge (Qeff) as a function of annealing temperature

(600–900 1C) and compared with as-oxidized sample.

Annealing Temperature (°C)As-Ox 500

Slow

trap

den

sity

STD

(x 1

011 c

m-2

)

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

600 700 800 900

Fig. 6. Slow trap density (STD) as a function of annealing temperature

(600–900 1C) and compared with as-oxidized sample.

Ec-E (eV)0.10

Inte

rfac

e tr

ap d

ensi

ty D

it (e

V-1 c

m-2

)

1014

1015

As-Ox 500°C600°C700°C800°C900°C

0.15 0.20 0.25 0.30 0.35

Fig. 7. Interface trap density (Dit) of as-oxidized sample compared with

samples annealed at different temperatures (600–900 1C).

As-Ox 500

Die

lect

ric c

onst

ant (

κ)

10.0

20.0

30.0

40.0

50.0

60.0

70.0

80.0

90.0

Annealing Temperature (°C)600 700 800 900

Fig. 8. Dielectric constant (k) of as-oxidized sample compared with

samples annealed at different temperatures (600–900 1C).

Voltage (V)0

Leak

age

curr

ent d

ensi

tyJ,

(A/c

m2 )

10-1010-910-810-710-610-510-410-310-210-1100101102

As-Ox 500°C600°C700°C800°C900°C

2 4 6 8 10 12 14 16

Fig. 9. J–V characteristic of as-oxidized sample compared with samples

annealed at different temperatures (600–900 1C).

T. Kurniawan et al. / Materials Science in Semiconductor Processing 14 (2011) 13–1716

Curve of leakage current density–voltage (J–V) of as-oxidized and annealed samples is presented in Fig. 9. Ascompared to as-oxidized sample, annealing process has

enabled the reduction in leakage current density of theoxide. At 1 V, J for as-oxidized sample is 2.9�10�7 A/cm2,while for annealed samples, J is in the range of 1.12�10�8–7.8�10�8 A/cm2. The existence of higher negative charge

T. Kurniawan et al. / Materials Science in Semiconductor Processing 14 (2011) 13–17 17

in the annealed samples is presumed to be able to generatea higher barrier for electrical current to pass through theoxide [22]. Furthermore, the leakage current of the samplesdecreases as the annealing temperature increases. It ispossible that Qeff and/or Dit can induce this characteristic.Higher –Qeff may provide a higher barrier for currentleakage as explained above. On the other hand, the lowerJ and higher breakdown voltage (VB) of 9000 1C-annealedsample is due to its lower Dit value if compared to the otherannealed samples. In agreement with the previous workconducted by Karlsson et al. [17], thermal stability of ZrO2

on SiC below annealing temperatures of 1000 1C has beensupported by electrical results in this work.

4. Conclusion

ZrO2 thin films were deposited on n-type 4H-SiC by acombination of metal sputtering deposition and thermaloxidation processes. XRD analysis has shown that post-annealing at higher temperatures induced phase transfor-mation on ZrO2 structure. HRTEM images showed that ILsof SiOx and/or ZrxSiyOz were formed from the oxidationprocess, and the thickness was increased after post-annealing treatment. From electrical characterization, itis depicted that post-annealing has increased oxide capa-citance, increased dielectric constant of the oxide, andreduced the leakage current density. On the contrary, post-annealing has reduced the breakdown voltage of the oxide.

Acknowledgments

This work was supported by the eScienceFund (Grant no.6013370) and the Academy Sciences for the DevelopingWorld (TWAS) through TWAS-COMSTECH Research Grant(09-105 RG/ENG/AS_C). One of the authors (YHW) would liketo acknowledge USM fellowship, USM-RU-PRGS (8032051).

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