Effects of Switched-Bias Annealing on Charge Trapping in HfO 2 high- Gate Dielectrics

June 13, 2006 2006 MURI Annual Review X. J. Zhou, et al 1

Effects of Switched-Bias Annealing on Charge Trapping in HfO2 high- Gate Dielectrics

X. J. Zhou,a D. M. Fleetwood,a L. Tsetseris,b R. D. Schrimpf,a S. T. Pantelidesb

a Department of Electrical Engineering and Computer Science, Vanderbilt Universityb Department of Physics and Astronomy, Vanderbilt University

Supported in part by Air Force Office of Scientific Researchthrough the MURI program and the US Navy


Outline

Motivation

Experimental resultsSwitched bias annealing after X-ray radiationSwitched bias annealing after Constant Voltage Stress

(CVS)

Model of device response based onMetastable electron traps near interface (Vot)

Primarily after radiation exposureProton transport & reaction (Vit)

After irradiation or CVSAdditional defect growth during longer anneal cycles


General Motivation

High- dielectrics are promising candidates for future commercial and space electronics.

At last year’s IEEE NSREC, we reported more degradation (very large threshold voltage shifts) when irradiation and bias temperature stressing (BTS) were combined than when the two separate effects were assessed independently and added.

Charge trapping properties of high- dielectrics are not well understood – more insight is needed in advance of their potential use in manufacturing.


Specific Motivation (from last year’s NSREC)

Worst case forCircuit response:pMOS devices irradiated “off” and annealed “on

Zhou, Fleetwood, Felix, Gusev, and D’Emic, TNS, 52 (6),2231, 2005

• Doses: 1 Mrad(SiO2); 0, ±2 MV/cm• BTS: 10 min; ±2 MV/cm; 75ºC


Experimental details

Devices

• Al/SiOxNy+HfO2/p-Si MOS caps

• EOT = 2.1 nm

Irradiation or constant voltage stress (CVS)

• Rad: 10-keV X-rays; ~ 500 rad(SiO2)/s to 1 Mrad(SiO2); Eox= 2MV/cm

• CVS: Eox = – 3.6 MV/cm; t = 1200s; T=25ºC

Switched-Bias annealing• 25ºC to 150ºC

• Eox = ± 2 MV/cm alternating

• Typical anneal time: 10 min

Si

Oxynitride (1.0 nm)

HfO2 (6.8 nm)

Al

∆Vot and ∆Vit (flatband to midgap) estimated by midgap method of Winokur et al., IEEE TNS 31, 1453 (1984)


Reversibility observed in ∆Vot after irradiation,during switched-bias anneals at 50ºC

Vot increases during NBTS and decreases during PBTS

Metastably trapped electrons near interface contribute to reversibility of Vot

Rad: 1 Mrad (SiO2); 2 MV/cmAnneals: ±2 MV/cm, 50C


Si

Al

HfO2 (6.8 nm)

SiOxNy(1.0 nm)

-V +V

+

++

+

_ _

+ +_ _++ ++_ _ _ _

Dominant Mechanism: ∆Vot

Electrons move out of oxideduring NBTS

Electrons pulled back intooxide during PBTS


Vot reversibility increases with annealing temperature

• Pure electron tunneling should not depend strongly on temperature

•Other mechanisms must be contributing (e.g., H+ motion), as we now show

Rad: 1 Mrad (SiO2); 2 MV/cmAnneals: ±2 MV/cm


Similar reversibility also observed for Vit

• Vit increases during NBTS, and decreases during PBTS

• Process not due to normal two-stage Vit buildup due to H+ release in oxide

• More consistent with Vit buildup seen in NBTI experiments



Candidate Mechanism (Oversimplified)[structural reconfiguration likely also occurs; not just H+ motion]

Si

Al

HfO2 (6.8 nm)

SiOxNy(1.0 nm)

-V +V

H+

H+

Si SiSiSi

Protons depassivate Si-H bond: Vit ↑, Vot ↑

Protons passivate Si-H bond: Vit ↓, Vot ↓


Vit increases with increasing anneal temperature

• More than simple reversibility in charge motion after rad

•Additional defect growth must occur in these devices during the anneal – why?



After rad, |ΔVot| > |ΔVit|

Both electron exchange and H+ motion occur

Enhanced reversibility in Vot consistent with large e-h (dipole) generation during rad

Rad: 1 Mrad (SiO2); 2 MV/cmAnneals: ±2 MV/cm @ 50 C


Post-CVS annealing at 50C |ΔVot| < |ΔVit|

Similar trend as post-rad, but now Vit dominates

No electron-hole pair creation due to low voltage; lack of radiation

Proton interactions relatively more important than for post-rad case

CVS: (– 3.6 MV/cm; 1200s; 25ºC)Anneals: ±2 MV/cm


More annealing cycles lead to enhanced defect growth

Degradation increases with time (not just reversibility)

Defect growth increases with annealing time and temperature



Defect growth with time: post-CVS(similar trends post-rad)

• Low electric fields, but high enough to increase gate current

• Gate current increases with temperature

• Additional CVS stress occurs during annealing cycles at high-T

•Enhanced H+ motion and interactions lead to increasing ∆Vit, ∆Vot



Conclusions and Implications

• High-κdevices can trap large numbers of compensating electrons and holes during irradiation.

• Leads to significant reversibility in ∆Vot during switched-bias annealing.

• Effects large enough to cause pMOS transistors to fail in circuit applications.

• Constant-voltage stress experiments show the importance of hydrogen motion and reactions on device response.

• Reversible with bias.

• But generally increasing with time and temperature.

• Unless effects are addressed via process improvements, qualification of high-κdevices for space application will require additional screening and testing margins, as compared to SiO2

Documents

Effects of Switched-Bias Annealing on Charge Trapping in HfO 2 high- Gate Dielectrics