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Spring 2010 1
ELCT 604: Electronic Circuitschapter 5:
Differential Amplifiers, Current Mirrors
and Active Loads
(Continued)
Associate Prof. Dr. Soliman Mahmoud
Faculty of Information Engineering and Technology
Electrical and Electronic Department
Assistant Prof. Dr. Ahmed H. Madian
Faculty of Information Engineering and Technology
Electrical and Electronic Department
Associate Prof. Dr. Soliman Mahmoud & Dr. Ahmed Madian
Electronics and Electrical Engineering Department
ELCT 604, Electronic Circuits
Spring 2007 2
4. Simple Current Source (or Mirror)
Q3 Q4
VCC
Rref
IREF
+
- -
+
VBE3VBE4
IEE
E
IB3 IB4IC3
IC4
►The simplest form of a current mirror
consists of two transistors. The shown
Figure shows a bipolar version of this
mirror. Transistor Q3 is diode connected,
forcing its collector-base voltage to zero. In
this mode, the collector-base junction is off
and Q3 operates in the active region.
► Assume that Q4 also operates in the
forward-active region. Then IEE= IC4 is
controlled by VBE4, which is equal to VBE3
by KVL. (VBE4 = VBE3)
)ln(4
44
Co
CTBE
I
IVV )ln(
3
33
Co
CTBE
I
IVV =
► If the transistors are identical, ICO3 = ICO4 and from the above equation shows that the current
flowing in the collector of Q3 is mirrored to the collector of Q4 ( IC4=IC3).
Associate Prof. Dr. Soliman Mahmoud & Dr. Ahmed Madian
Electronics and Electrical Engineering Department
ELCT 604, Electronic Circuits
Spring 2007 3
4. Simple Current Source (or Mirror)
Q3 Q4
VCC
Rref
IREF
+
- -
+
VBE3VBE4
IEE
E
►By applying KCL at node (1)
IEE/βIEE IEE/β
(1)EE
EEREF
III
2
)2
1(
REFEE
II
Where
ref
CC
ref
BECCREF
R
V
R
VVI
)7.0()( 3
ifREFEE II
Associate Prof. Dr. Soliman Mahmoud & Dr. Ahmed Madian
Electronics and Electrical Engineering Department
ELCT 604, Electronic Circuits
Spring 2007 4
Complete Differential Amplifier with
actual Current SourceVCC
RC RC
1iv 2iv
ICMDC VV 1 ICMDC VV 2
Q1 Q2
1ov 2ovRref
Q4Q3
IEE
IREF
Associate Prof. Dr. Soliman Mahmoud & Dr. Ahmed Madian
Electronics and Electrical Engineering Department
ELCT 604, Electronic Circuits
Spring 2007 5
5. Active LoadsThe differential mode gain Adm is given by :
)*(1
CC
T
CmBJTdm RIV
RgA
To achieve large voltage gain, the above equations shows that the
product must made large which in turn requires a large power-supply voltage.
Furthermore, large values of resistance are required. As a result the required die
area for the resistors can be large.
To overcome this problem and provide large gain without large power supply
voltages or resistances, the ro of a transistor can be used as a load element.
Since the load element in such a circuit is a transistor instead of a resistor,
the load element is said to be active load.
BJTCC RI )*(
Associate Prof. Dr. Soliman Mahmoud & Dr. Ahmed Madian
Electronics and Electrical Engineering Department
ELCT 604, Electronic Circuits
Spring 2007 6
Q1
VCC
vi
vout
Q2Q3
Rref
Rin
Rout
Q1
VCC
vi
vout
Vbias
(DC Voltage)Q2
Rin
Rout
CE with Resistive Load CE with Active Load biased
by a DC voltage
CE with Active Load biased
by a current source
Example: Active load Active loadBiasing of Active load
≡ ro2
Q1
VCC
RL
vi
vout
Rin
Rout
1rRin 1// oLout rRR
1
1)//(
r
rR
v
v oLn
in
out
& 1rRin 12 // ooout rrR
1
12 )//(
r
rr
v
v oon
in
out
& 1rRin 12 // ooout rrR
1
12 )//(
r
rr
v
v oon
in
out
&
Associate Prof. Dr. Soliman Mahmoud & Dr. Ahmed Madian
Electronics and Electrical Engineering Department
ELCT 604, Electronic Circuits
Spring 2007 7
Complete Differential Amplifier with Actual
Current Source and Active LoadsVCC
1iv 2iv
ICMV
ICMV
Q1 Q2
1ov 2ovRref1
Q4Q3
IEE
IREF1
Q5Q6Q7
IREF2
Rref2
Circuit Description:
1. Q1 and Q2 :
Differential pair transistors
2. Q3, Q4 and Rref1:
Current source of the
differential pair transistors
3. Q5, Q6, Q7 and Rref2 :
Active loads and the
biasing of the active loads
Associate Prof. Dr. Soliman Mahmoud & Dr. Ahmed Madian
Electronics and Electrical Engineering Department
ELCT 604, Electronic Circuits
Spring 2007 8
Differential input- Single ended output Amplifier with
Actual Current Source and Active Loads
VCC
inv
ICMV
Q1 Q2
ovRref1
Q4Q3
IEE
IREF1
Q5 Q6
+
-
Circuit Description:
1. Q1 and Q2 :
Differential pair transistors
2. Q3, Q4 and Rref1:
Current source of the
differential pair transistors
3. Q5 and Q6:
Active loads and the
biasing of the active loads
Associate Prof. Dr. Soliman Mahmoud & Dr. Ahmed Madian
Electronics and Electrical Engineering Department
ELCT 604, Electronic Circuits
Spring 2007 9
Example:
For the shown differential input–
single output amplifier, find:
1. The input resistance
2. The output resistance
3. The ac output current
4. The transconductance Gain
5. The voltage Gain
Assumptions:
1. Q1, Q2 are matched
2. Q3, Q4 are matched
3. Q5, Q6 are matched
4. βn and βp are large
Therefore,
2
1
51 62
ref
CCCC
IIIII
refCC III 43
)( 21
21
CC
Anoo
II
Vrr
)( 43
43
CC
Anoo
II
Vrr
)( 65
65
CC
Ap
ooII
Vrr
})(
{ 2121
T
CC
n
V
IIrr
, , and
VCC
inv
ICMV
Q1 Q2
ovRref1
Q4Q3
IEE
IREF1
Q5 Q6
+
-
Rout
Rin
iout
Associate Prof. Dr. Soliman Mahmoud & Dr. Ahmed Madian
Electronics and Electrical Engineering Department
ELCT 604, Electronic Circuits
Spring 2007 10
invQ1 Q2
outvRref1
Q4Q3
Q5 Q6
+
-
iout
ro4
Rin
Rout
)1
//()(1( 241
n
onin
rrrR
2121 22 rrrrRin
)})1(
//)(1(//{ 142226
n
oomooout
rrrgrrR
26 2// ooout rrR
1. The input resistance
2. The output resistance
Associate Prof. Dr. Soliman Mahmoud & Dr. Ahmed Madian
Electronics and Electrical Engineering Department
ELCT 604, Electronic Circuits
Spring 2007 11
invQ1 Q2
outvRref1
Q4Q3
Q5 Q6
+
-
iout
ib1 βnib1
≈βnib1≈βnib1
≈βnib1
ro4
≈ 0
≈βnib1
≈βnib1
Rin
Rout
3. The ac output current
12 bnout ii
111 2* binbin irRiv
inminn
out vgvr
i 1
1
3. Transconductance gain
1mM
in
out gGv
i
4. Voltage gain
outM
in
outout
in
out RGv
Ri
v
v
Associate Prof. Dr. Soliman Mahmoud & Dr. Ahmed Madian
Electronics and Electrical Engineering Department
ELCT 604, Electronic Circuits
Spring 2007 12
Objective:
The objective from this chapter is:
1. Define and characterize MOS differential amplifier.
2. Show the large signal and small signal performance of
MOS differential amplifier.
Outlines(2nd lecture):
1. Large Signal Currents and Voltages Transfer Function
of MOS differential amplifier.
2. Small Signal performance of MOS differential amplifier.
3. Simple MOS Current Source (Or Mirror).
5. MOS Active loads
Differential Amplifiers, Current Mirrors
and Active Loads
Associate Prof. Dr. Soliman Mahmoud & Dr. Ahmed Madian
Electronics and Electrical Engineering Department
ELCT 604, Electronic Circuits
Spring 2007 13
1. Large Signal Currents and
Voltages Transfer function of MOS
Differential amplifier
Objectives:
(1)Calculation DC currents ID1 and ID2 as
a function of the biasing current source
ISS and the input differential voltage
Vid=Vi1-Vi2.
(2)Calculation output differential voltage
Vod= Vo1- Vo2 as a function of biasing
current source ISS, drain resistors RD
and input differential voltage Vid=Vi1-
Vi2.
►Consider the following NMOS
differential amplifier (sometimes called an
source-coupled pair)
ISS RSS
ID1 ID2
S
Associate Prof. Dr. Soliman Mahmoud & Dr. Ahmed Madian
Electronics and Electrical Engineering Department
ELCT 604, Electronic Circuits
Spring 2007 14
►Assumptions:
1. Assume M1 and M2 are identical and
operating in the saturation region.
Therefore:
2
11 )(2
TGSD VVK
I
KKK 21 TTT VVV 21&
K
IVV DTGS
11
2
&
2
22 )(2
TGSD VVK
I
K
IVV DTGS
22
2
ISS RSS
ID1 ID2
S
Associate Prof. Dr. Soliman Mahmoud & Dr. Ahmed Madian
Electronics and Electrical Engineering Department
ELCT 604, Electronic Circuits
Spring 2007 15
The Basic equation of the SCC is :
2211 GSiGSiS VVVVV
Therefore
)(2
212121 DDGSGSidii IIK
VVVVV
Definition:
The currents of M1 and M2 can be written as:
21 DDout III
22
112
)(2
AK
VVK
I TGSD 22
222
)(2
BK
VVK
I TGSD
The output current of the NMOS Differential pair :
&
ISS RSS
ID1 ID2
S
Associate Prof. Dr. Soliman Mahmoud & Dr. Ahmed Madian
Electronics and Electrical Engineering Department
ELCT 604, Electronic Circuits
Spring 2007 16
ISS RSS
ID1 ID2
S
Therefore:
))((2
)(2
22 BABAK
BAK
I out
And
SSDD IBAK
II )(2
22
21
idGSGS VVVBA 21
Where
)(2)()( 2222 BABABA
idSS VK
IBA 22 4)(
Note
Therefore:
)/4
1(4)(2
KI
V
K
IBA
SS
idSS )/4
1(2
KI
VVKII
SS
id
idSSout
Associate Prof. Dr. Soliman Mahmoud & Dr. Ahmed Madian
Electronics and Electrical Engineering Department
ELCT 604, Electronic Circuits
Spring 2007 17
)/4
1(2
1
2
2
1KI
VVKI
II
SS
id
idSSSS
D
)/4
1(2
1
2
2
2KI
VVKI
II
SS
id
idSSSS
D
Therefore:
)/4
1(2
21KI
VVKIIII
SS
id
idSSDDout
SSDD III 21
and
ISS RSS
ID1 ID2
S
Associate Prof. Dr. Soliman Mahmoud & Dr. Ahmed Madian
Electronics and Electrical Engineering Department
ELCT 604, Electronic Circuits
Spring 2007 18
idSSSS
D VKII
I2
1
22
Notes:
The nonlinear term of output current can be neglected and the output
current is given by:
idSSout VKII and
idSSSS
D VKII
I2
1
21
2. If K
IV SSid
2
K
IV SSid
21. At 0& 21 DSSD III
K
IV SSid
2 SSDD III 21 &0
(M1 is ON & M2 Is Off)
(M1 is Off & M2 Is ON)
)/4
1(2
1
2
2
1KI
VVKI
II
SS
id
idSSSS
D )/4
1(2
1
2
2
2KI
VVKI
II
SS
id
idSSSS
D &
Associate Prof. Dr. Soliman Mahmoud & Dr. Ahmed Madian
Electronics and Electrical Engineering Department
ELCT 604, Electronic Circuits
Spring 2007 19
Source-coupled pair Drain currents as a function of differential input voltage.
)/4
1(2
1
2
2
1KI
VVKI
II
SS
id
idSSSS
D )/4
1(2
1
2
2
2KI
VVKI
II
SS
id
idSSSS
D &
ID1, ID2
ID1ID2
VK
ISS 1.02
VK
ISS 25.02
VK
ISS 5.02
VK
ISS 1.02
VK
ISS 25.02
VK
ISS 5.02
ISS
0.5 ISS
Associate Prof. Dr. Soliman Mahmoud & Dr. Ahmed Madian
Electronics and Electrical Engineering Department
ELCT 604, Electronic Circuits
Spring 2007 20
Notes : 3. We can now compute the output voltages as:
DDDDo RIVV 11
DDDDo RIVV 22 DoutDDDod RIRIIV )( 21
id
SS
id
SSDod VKI
VKIRV ])
/41([
2
If K
IV SSid
2 idSSDod VKIRV
Vod
0
ISS RD
- ISS RD
VK
ISS 1.02
VK
ISS 25.02
VK
ISS 5.02
KIRSlope SSD
Associate Prof. Dr. Soliman Mahmoud & Dr. Ahmed Madian
Electronics and Electrical Engineering Department
ELCT 604, Electronic Circuits
Spring 2007 21
Optimum DC operating Point
►From the previous Figure, the optimum DC operating for linear operation
between the output and the input differential voltage is at Vid =0.
► At Vid =0, we have
221
SSDD
III
SSorDmm KIKIgg 2121 2
SSorDor
dsdsII
rr
21
2121
21 ,
Associate Prof. Dr. Soliman Mahmoud & Dr. Ahmed Madian
Electronics and Electrical Engineering Department
ELCT 604, Electronic Circuits
Spring 2007 22
2. Small-Signal Analysis of MOS-
Differential Amplifiers
Objectives :
(1)Calculation differential
mode gain (Adm)
(2)Calculation common
mode gain (Acm)
(3)Calculation common
mode rejection ratio
(CMRR)
Using Half Circuit Concept
(HCC)
VDD
VSS
ISS RSS
RD RD
1iv 2iv
ICMDC VV 1 ICMDC VV 2
M1 Q2
1ov 2ov
Associate Prof. Dr. Soliman Mahmoud & Dr. Ahmed Madian
Electronics and Electrical Engineering Department
ELCT 604, Electronic Circuits
Spring 2007 23
RSS
RD RD
icid
i vv
v 2
1
M1 M2
icid
i vv
v 2
2
ocod
o vv
v 2
1 ocod
o vv
v 2
2
RD RD
2
idv
M1 M2
2
idv
2
odv
2
odv
RD RD
icv
M1 M2
ocv ocv
icv2 RSS 2 RSS
Differential
mode
circuit
Common
mode
circuit
VDD
VSS
ISS RSS
RD RD
1iv 2iv
ICMDC VV 1 ICMDC VV 2
M1 Q2
1ov 2ov
Associate Prof. Dr. Soliman Mahmoud & Dr. Ahmed Madian
Electronics and Electrical Engineering Department
ELCT 604, Electronic Circuits
Spring 2007 24
Differential Mode Gain Adm, Common Mode Gain Acm
and Common Mode Rejection Ratio CMRR
RD
2
idv
M1
2
odvrds is neglected
Dm
id
oddm Rg
v
vA
SSm
Dm
ic
occm
Rg
Rg
v
vA
21
RD
icv
M1
ocv
2 RSS
SSm
cm
dm RgA
ACMRR 21
►Note that increasing the output resistance of
the biasing current source improves the
common-mode-rejection ratio
Associate Prof. Dr. Soliman Mahmoud & Dr. Ahmed Madian
Electronics and Electrical Engineering Department
ELCT 604, Electronic Circuits
Spring 2007 25
3. Simple Current Source (or Mirror)
M3 M4
VDD
Rref
IREF
+
- -
+
VGS3VGS4
ISS
S
ID3ID4
►The simplest form of a current mirror
consists of two transistors. The shown
Figure shows a NMOS version of this
mirror. Transistor M3 is diode connected,
forcing its Drain-Gate voltage to zero. In
this mode, M3 operates in the sat. region.
► Assume that M4 also operates in the
saturation region. Then ISS= ID4 is
controlled by VGS4, which is equal to VGS3
by KVL. (VGS4 = VGS3)
4
44
2
K
IVV DSTGS
3
33
2
K
IVV DSTGS =
► If the transistors are identical, K3 = K4 and from the above equation shows that the current
flowing in the Drain of M3 is mirrored to the Drain of M4 ( ID4=ID3=Iref).
Associate Prof. Dr. Soliman Mahmoud & Dr. Ahmed Madian
Electronics and Electrical Engineering Department
ELCT 604, Electronic Circuits
Spring 2007 26
Complete Differential Amplifier with
actual Current SourceVDD
RD RD
1iv 2iv
ICMDC VV 1 ICMDC VV 2
M1 M2
1ov 2ovRref
M4M3
ISS
IREF
Associate Prof. Dr. Soliman Mahmoud & Dr. Ahmed Madian
Electronics and Electrical Engineering Department
ELCT 604, Electronic Circuits
Spring 2007 27
3. Active LoadsThe differential mode gain Adm is given by :
)*(2DDDmMOSdmRIKRgA
To achieve large voltage gain, the above equations shows that the
product must made large which in turn requires a large power-supply voltage.
Furthermore, large values of resistance are required. As a result the required die
area for the resistors can be large.
To overcome this problem and provide large gain without large power supply
voltages or resistances, the rds of a transistor can be used as a load element.
Since the load element in such a circuit is a transistor instead of a resistor,
the load element is said to be active load.
MOSDDRI )*(
Associate Prof. Dr. Soliman Mahmoud & Dr. Ahmed Madian
Electronics and Electrical Engineering Department
ELCT 604, Electronic Circuits
Spring 2007 28
M1
VDD
vi
vout
M2M3
Rref
Rin
Rout
M1
VDD
vi
vout
Vbias
(DC Voltage)M2
Rin
Rout
CS with Resistive Load CS with Active Load biased
by a DC voltage
CS with Active Load biased
by a current source
Example: Active load Active loadBiasing of Active load
≡ rds2
M1
VDD
RL
vi
vout
Rin
Rout
inR 1// dsLout rRR
)//( 11 dsLm
in
out rRgv
v
& inR 12 // dsdsout rrR
)//( 121 dsdsm
in
out rrgv
v
& inR 12 // dsdsout rrR
)//( 121 dsdsm
in
out rrgv
v
&
Associate Prof. Dr. Soliman Mahmoud & Dr. Ahmed Madian
Electronics and Electrical Engineering Department
ELCT 604, Electronic Circuits
Spring 2007 29
Complete Differential Amplifier with Actual
Current Source and Active LoadsVDD
1iv 2iv
ICMV
ICMV
M1 M2
1ov 2ovRref1
M4M3
IEE
IREF1
M5M6M7
IREF2
Rref2
Circuit Description:
1. M1 and M2 :
Differential pair transistors
2. M3, M4 and Rref1:
Current source of the
differential pair transistors
3. M5, M6, M7 and Rref2 :
Active loads and the
biasing of the active loads
Associate Prof. Dr. Soliman Mahmoud & Dr. Ahmed Madian
Electronics and Electrical Engineering Department
ELCT 604, Electronic Circuits
Spring 2007 30
Differential input- Single ended output Amplifier with
Actual Current Source and Active Loads
Circuit Description:
1. M1 and M2 :
Differential pair transistors
2. M3, M4 and Rref1:
Current source of the
differential pair transistors
3. M5 and M6:
Active loads and the
biasing of the active loads
VDD
inv
ICMV
M1 M2
ovRref1
M4M3
ISS
IREF1
M5 M6
+
-
Rout
Rin
iout
Associate Prof. Dr. Soliman Mahmoud & Dr. Ahmed Madian
Electronics and Electrical Engineering Department
ELCT 604, Electronic Circuits
Spring 2007 31
Example:
For the shown differential input–
single output amplifier, find:
1. The input resistance
2. The output resistance
3. The ac output current
4. The transconductance Gain
5. The voltage Gain
Assumptions:
1. M1, M2 are matched
2. M3, M4 are matched
3. M5, M6 are matched
Therefore,
2
1
51 62
ref
DDDD
IIIII
143 refDD III
)(
1
2121
21
DDor
dsdsII
rr
)(
1
4343
43
DDor
dsdsII
rr
)(
1
6565
65
DDor
dsdsII
rr
, and
VDD
inv
ICMV
M1 M2
ovRref1
M4M3
ISS
IREF1
M5 M6
+
-
Rout
Rin
iout
Associate Prof. Dr. Soliman Mahmoud & Dr. Ahmed Madian
Electronics and Electrical Engineering Department
ELCT 604, Electronic Circuits
Spring 2007 32
inR
)}1
//)(1(//{1
42226
m
dsdsmdsdsoutg
rrgrrR 26 2// dsdsout rrR
1. The input resistance
2. The output resistance
VDD
inv
ICMV
M1 M2
ovRref1
M4M3
IREF1
M5 M6
+
-
Rout
Rin
iout
rds4
Associate Prof. Dr. Soliman Mahmoud & Dr. Ahmed Madian
Electronics and Electrical Engineering Department
ELCT 604, Electronic Circuits
Spring 2007 33
3. The ac output current
112 gsmout vgi
2211 gsmgsm vgvg
21 gsgs vv
3. Transconductance gain
1mM
in
out gGv
i
4. Voltage gain
outM
in
outout
in
out RGv
Ri
v
v
VDD
inv
M1 M2
ovRref1
M4M3
IREF1
M5 M6
+
-
+ v
gs1 - -
v gs2
+
gm1 vgs1
gm1 vgs1 gm1 vgs1
gm1 vgs1
Rout
Rin
iout
rds4
≈ 0
1211 2 gsgsgsin vvvv
inmout vgi 1