ELE22MIC Microprocessors Aug 2004 68HC11 Instruction Set Reference Page 1

ELE22MIC Microprocessors Aug 2004 68HC11 Instruction Set Reference Page 2

ELE22MIC Microprocessors Aug 2004 68HC11 Instruction Set Reference Page 3

ELE22MIC Microprocessors Aug 2004 68HC11 Instruction Set Reference Page 4

ELE22MIC Microprocessors Aug 2004 68HC11 Instruction Set Reference Page 5

ELE22MIC Microprocessors Aug 2004 68HC11 Instruction Set Reference Page 6

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68HC11 Instruction Set by Instruction Category

ARITHMETIC ADDITION

ABA A = A + BABX IX = IX + BABY IY = IY + BADCA A = A + M + CarryFlagADCB B = B + M + CarryFlagADDA A = A + MADDB B = B + MADDD D = D + M

SUBTRACTIONSBA A = A - BSBCA A = A - M - CarryFlagSBCB B = B - M - CarryFlagSUBA A = A - MSUBB B = B - MSUBD D = D - M

TWOS COMPLEMENT (NEGATE)NEG M = -MNEGA A = -ABEGB B = -B

DECREMENTDEC M = M - 1DECA A = A - 1DECB B = B - 1DES SP = SP - 1DEX IX = IX - 1

INCREMENTINC M = M + 1INCA A = A + 1INCB B = B + 1INS SP = SP + 1INX IX = IX + 1INY IY = IY + 1

MULTIPLYMUL D = A * B

DIVIDEIDIV IX = D / IX, D = D % IXFDIV IX = D / IX, D = D % IX

(FDIV treats args as fractions)

ARITHMETIC SHIFT LEFT: (Multiply by 2)

ASL Arithmetic Shift Left (M)ASLA Arithmetic Shift Left (A)ASLB Arithmetic Shift Left (B)ASLD Arithmetic Shift Left (D)

RIGHT: (Divide By 2)ASR Arithmetic Shift Right (M)ASRA Arithmetic Shift Right (A)ASRB Arithmetic Shift Right (B)

LOGICAL SHIFT

LEFT:LSL Logical Shift Left (M)LSLA Logical Shift Left (A)LSLB Logical Shift Left (B)LSLD Logical Shift Left (D)

SHIFT RIGHT: LSR Logical Shift Right (M)LSRA Logical Shift Right (A)LSRB Logical Shift Right (B)LSRD Logical Shift Right (D)

ROTATE LEFT: (used to extend multiply)

ROL ROtate Left (M)ROLA ROtate Left (A)ROLB ROtate Left (B)

RIGHT: (used to extend divide)ROR ROtate Right (M)RORA ROtate Right (A)RORB ROtate Right (B)

BINARY CODED DECIMAL (BCD) DAA Decimal Adjust after Addition

Branch & JumpBRA Branch AlwaysBRN Branch Never

JMP Jump to AddressJSR Jump to Subroutine

NOP No OPeration ; i.e do nothing but fetchnext instruction

CLEAR (bit(s) = 0) & SET (bit(s) = 1)CLR M = 0CLRA A = 0CLRB B = 0BCLR Clear Bits (M)BSET Set Bits (M)

COMPARE & TEST

CONDITION CODE MANIPULATIONCLC CarryFlag = 0 Clear Carry FlagCLV OVerflowFlag = 0 Clear Overflow FlagSEC CarryFlag = 1 Set Carry FlagSEV OVerflowFlag = 1Set Overflow FlagTAP CCR = A Transfer A to

Condition CodesRegister (CCR)

TPA A = CCR Transfer CCR to A

CONDITIONAL BranchesBEQ Branch if EQualBNE Branch if Not EqualBCC Branch if CarryFlag is Clear

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BCS Branch if CarryFlag is SetBRCLR Branch if bits clearBRSET Branch if bits set

Conditional Branches using SIGNED NUMERICINTERPRETATION

BMI Branch if MInusBPL Branch if PLusBVS Branch if oVerflow SetBVC Branch if oVerflow ClearBLT Branch if Less ThanBGE Branch if Greater-Than or Equal-toBLE Branch if Less-Than or Equal-to

Branches for UN-SIGNED NUMERICINTERPRETATION

BHI Branch if HIgher thanBHS Branch if Higher or SameBLS Branch if Lower or SameBLO Branch if Lower

DATA MOVEMENT Push - Push register value onto stack

PSHA M[SP--] = A PSHB M[SP--] = BPSHX M[SP--] = IX.LOW ;

M[SP--] = IX.HIGHPSHY M[SP--] = IY.LOW ;

M[SP--] = IY.HIGH

Pull - Pull (POP) value from stack to Register PULA A = M[++Sp] PULB B = M[++SP]PULX X.HIGH = M[++SP] ; X.LOW =

M[++SP]PULY Y.HIGH = M[++SP] ; Y.LOW =

M[++SP]

Load RegisterLDAA A = MLDAB B = MLDD D = MLDS SP = MLDX X = MLDY Y = M

Store Register

STAA A -> MSTAB B -> MSTD D -> M:M+1

([M] = A, [M+1] = B)STX IX -> M:M+1STY IY -> M:M+1

Transfer RegistersTAB A = BTBA B = ATSX IX = SP + 1TSY IY = SP + 1TXS SP = IX - 1TXY SP = IY - 1

Exchange Registers

XGDX D <=> IXXGDY D <=> IY

INTERRUPT HANDLING:CLI ; Clear interrupt MaskSEI ; Set interrupt MaskSWI ; Software InterruptRTI ; Return from InterruptWAI ; Wait for interrupt

LOGICALLOGICAL AND

ANDA A = A & MANDB B = B & M

LOGICAL EXCLUSIVE OREORA A = A ^ MEORB B = B ^ M

LOGICAL ORORAA A = A | MORAB B = B | M

ONES COMPLEMENT (NOT)COM M = M#COMA A = A#COMB B = B#

MISCELLANEOUSSTOP Stop clocksTEST Special test mode

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