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192 CHANNEL PLASMA DISPLAY PANEL DATA DRIVER

(PRELIMINARY SPEC)

JULY. 2003.

Ver. 2.0

Prepared by: Young Joon Cho

[email protected]

S6P1002

Contents in this document are subject to change without notice. No part of this document may be reproduced or

transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written

permission of Samsung Electronics CO. Ltd.



S6P1002 PRELIMINARY SPEC 192 CH. PDP DATA DRIVER

2

S6P1002 Specification Revision History

Version Content Date

0.0 Original Jan.2003

1.0 Addition of RSDS function, Feb.2003

1.1 Pin Location Revision (page 6) Jun.2003

2.0 Addition of ERC function and pin location revision Jul.2003



192 CH. PDP DATA DRIVER S6P1002 PRELIMINARY SPEC

3

CONTENTS

INTRODUCTION.......................................................................................................4 FEATURES ...............................................................................................................4 BLOCK DIAGRAM ...................................................................................................5 PIN ASSIGNMENT ...................................................................................................6 PIN DESCRIPTION ..................................................................................................7 ABSOLUTE MAXIMUM RATINGS.........................................................................9 RECOMMENDED OPERATION RATINGS...........................................................9 DC CHARACTERISTICS...................................................................................... 10 AC TIMING REQUIREMENTS............................................................................. 11 AC TIMING CHARACTERISTICS ....................................................................... 11 AC TIMING DIAGRAM (TTL MODE).................................................................. 12 RSDS TIMING CHARACTERISTICS .................................................................. 13 AC TIMING DIAGRAM (RSDS MODE)............................................................... 14 OPERATION DESCRIPTION............................................................................... 15

DATA BUS CONFIGURATION..........................................................................................................15 INTERNAL FUNCTION DESCRIPTION............................................................................................17 RSDS DATA SAMPLING DIAGRAM1..............................................................................................18 RSDS DATA SAMPLING DIAGRAM2..............................................................................................19 TEST CONFIGURATION....................................................................................................................20




4

INTRODUCTION

S6P1002 is a data driver for Plasma Display Panel (PDP). This device is designed in CDMOS high voltage

process technology. Using a 6 or 12bit wide data bus, it can control 192 high voltage-high current outputs.

It can also apply two mode signal interface, TTL mode operation and RSDS mode operation, alternately by using

IMOD input signal. S6P1002 is supplied with a separated 75V power output supply and a 5V logic supply. All

control inputs are CMOS and 3.3V logic levels compatible.

FEATURES

• 192 High Voltage Output Channels.

• Absolute Maximum Supply Voltage = 95V.

• Bi - directional Shift Register.

• 3.3V / 5V Flexible Logic Input.

• -40 / 30 mA Source / Sink Output MOS.

• 50 / 50 mA Source / Sink Output Diode.

• 6 or 12 Bit Data Bus (40 MHz).

• CDMOS Process.

• TCP (Tape Carrier Package).

• Low EMI data interface by RSDS mode operation.

• Energy Recovery Circuit (Charge Sharing)




5

BLOCK DIAGRAM

B < 1 : 6 >

O U

T 1

O U T 2

O U T 1 9 1 O U T 1 9 2

C L K

L V C P

L V C N

1 9 2

B i t D a t a L a t c h

1 6 B i t S h i f t R e g i s t e r

I n p

u t C o n t r o l U n i t

A < 1 : 6 >

M O D E

P O C

B L K

V P P

V S S P

S T B

V S S 1

V C C






S / R

0 6

S / R

0 5

S / R

0 4

S / R

0 3

S / R

0 2

S / R

0 1

S / R

9 6

S / R

9 5

S / R

9 4

S / R

9 3

S / R

9 2

S / R

9 1

1 6 B i t S h i f t

R e g i s t e r

1 6 B i t S h i f t

R e g i s t e r

1 6 B i t S h i f t

R e g i s t e r

1 6 B i t S h i f t

R e g i s t e r

1 6 B i t S h i f t

R e g i s t e r

1 6 B i t S h i f t

R e g i s t e r

S / R

0 6

S / R

0 5

S / R

0 4

S / R

0 3

S / R

0 2

S / R

0 1

S / R

9 6

S / R

9 5

S / R

9 4

S / R

9 3

S / R

9 2

S / R

9 1

O u t p u t C o n t r o l C i r c u i t

1 9 2 O u t p u t B u f f e r a n d L e v e l S h i f t e r

F / R

I M O D

E C

C S E

Figure 1. Block Diagram




6

PIN ASSIGNMENT

Y1

Y2Y3

Y4

Y192

Y191

Y190

Y189

S 6 P 1 0 0 2 A 0 1

( T OP VI E W )

LVCN

LVCP

VSSP

VSS1

F_R

CLK

POC

VCC

STB

BLK

B1

B3

B2

B4

B5

B6

VCC

VSS1

VSSP

EC

VSSP

VPP

VPP

A5

A6

CSE

VCC

MODE

IMOD

VSS1

VSSP

A4

A3

A2

A1

VCC

VSS1

EC

VPP

Figure 2. Pin Assignment




7

PIN DESCRIPTION

Table 1. Each Pin Description

Symbol Pin NameI /

O

Description

OUT

(1 to 192)PDP Drive Output O

Power Output

The output signals change in synchronization with the falling

edge of latch clock input, STB.

The amplitude of the driver output is VPP - VSSP.

F/R _

Shift Direction Control Input IWhen F/R

_

= L, An → OUT1 →……→ OUT192, Forward Shift

When F/R _

= H, An→ OUT192 →……→ OUT1, Reverse Shift

CLK Shift Clock Input I

Clock of data shift register

The shift register operates in synchronization with the rising

edge of this input

LVCP/LVCN RSDS clock pair I RSDS clock pair

IMOD Mode Selection Input IWhen IMOD = L, TTL mode is enable

When IMOD = H, RSDS mode is enable.

MODE Mode Selection Input I

This input selects the TTL mode, IMOD = L, within 6Bit and

12Bit

When MODE = L, 6Bit serial cascade TTL mode is enable.

When MODE = H, 12Bit parallel non-cascade TTL mode is

enable.

This input also selects the RSDS mode, IMOD = H.

When MODE = L, only RSDS clock is operating and not data

sampling.

When MODE = H, valid data are sampled from 1st falling edge

STB Strobe Input I

This input transfers the data of shift register to the output latch.

When STB = L and output data is contrary to previous output,

all driving outputs are short and execute the charge sharing.

BLK Output Blank Control Input I

This input controls the state of the driver outputs.

This pin is prior to the data of shift register and POC signal

When BLK = L, the driver output is fixed to VSSP.

When BLK = H, the driver output is VPP or VSSP

corresponding to the data and the state of POC.

POC Power Output Control Input I

This input controls the state of the driver outputs.

If the state of BLK is High,

When POC = L, the driver output is fixed to VPP

When POC = H, the driver output is VPP or VSSP

corresponding to the data.

ECEnergy Recovery

ConnectionI/O

In case of Charge sharing operation, all outputs are short via

EC pin where storage capacitor shall be connected.

CSE Charge sharing enable I

This input activates the charge sharing operation.

Normally, this pin is short to the vcc1 of TCP connection.

When CSE = H, in proportion to the STB low pulse duration,

charge sharing is executed.




8

When CSE = L, charge sharing operation is disable.

VSSP High Voltage Output Ground I Ground of power outputs.

VSS Logic Ground I Logic ground.

VCC Logic Power Supply I 5V logic supply.

VPP Drive Power Supply I High voltage supply of power outputs.

INOUT

(A1-A6,

B1-B6)

Data Input / Output I

At TTL 6 Bit data operation

When F/R _

is L, Data input is A1 to A6 and Output is B1 to B6.

When F/R _

is H, Data input is B1 to B6 and Output is A1 to A6.

When 12Bit data operation is adopted, A1-A6 and B1-B6 are

all input.

At RSDS mode, differential input(A1-A2, A3-A4, A5-A6, B1-

B2, B3-B4, B5-B6) is applied and 12 Bit data is sampled by

double edge RSDS clock.




9

ABSOLUTE MAXIMUM RATINGS

Table 2. Absolute Maximum Ratings

Parameter Symbol Ratings Unit

Logic power supply Vcc - 0.3 to 7.0 V

Driver power supply Vpp - 0.3 to 95 V

Input voltage Vin - 0.3 to VCC + 0.3 V

Driver output current (Note1) Ipout -50 / 35 mA

Output power voltage range Vout - 0.3 to 95 V

Maximum junction temperature Tjmax 125 °C

Storage temperature Tstg - 50 to 150 °C

NOTES:

1. Through one power output for al l power outputs (see Figure 4. Test configuration page14) with junction temperature lower

than or equal to Tjmax

RECOMMENDED OPERATION RATINGS

Table 3. Recommended Operation Ratings

(Vcc = 5V, Vpp = 75V, Vssp = 0V, Vss = 0V, Tamb = 25°C, FCLK = 40MHz, unless otherwise specified)

Parameter Symbol Min. Typ. Max. Unit Pin

Logic supply voltage Vcc 4.5 5 5.5 V

Power output supply voltage Vpp 30 - 75 V

Logic supply static current (Note 2) Iccs - 50 100 uA

Logic supply dynamic current

(FCLK = 20MHz) (Note 3) Iccd - 20 25 mA

Power output supply current

(steady outputs)Ipps - 5 10 uA

Power

(Vpp,Vcc)

NOTES:

2. Logic input levels compatible with 5V CMOS logic.3. All data inputs are commuted at 10MHz.




10

DC CHARACTERISTICS

Table 4. DC Characteristics

(Vcc = 5V, Vpp = 75V, Vssp = 0V, Vss = 0V, Tamb = 25°C, FCLK = 40MHz, unless otherwise specified)

Parameter Symbol Min. Typ. Max. Unit Pin

Power output high level (voltage drop versus Vpp)

@ Ipouth = -25mA and Vpp = 75VVpouth - 11 13

Power output low level

@ Ipoutl = 25 mAVpoutl - 7 13

Output diode voltage drop

@ Idouth = 50mA (Note 4) Vdouth - 1.5 3

Output diode voltage drop

@ Idoutl = -50mA (Note 4) Vdoutl -3 -1.1 -

V

Output

(OUT1

to

OUT192)

Input high level Vih 2.5 - - V

Input low level Vil - - 1.0 V

High level input current (Vih ≥ 2.0V) Iih - - 5 uA

Low level input current (Vil = 0V) Iil - - 5 uA

Input capacitance (Note 5) Cin - - 15 pF

Input

(CLK,

MODE,

IMOD

STB,

POC,

BLK,

F/R _

,

A1 to A6

B1 to B6)

NOTES:

4. See Figure8. Test configuration page 20

5. This parameter is not tested on the part.




11

AC TIMING REQUIREMENTS

Table 5. AC Timing Requirement

(Tamb = - 20 to 85 °C, VCC = 4.5 to 5.5 v, input signal max leading edge & trailing edge(tr,tf) =5ns)

Parameter Symbol Min. Typ. Max. Unit Remark

Data clock period tCLK 25 - -

Duration of CLK pulse at high level tWHCLK 10 - -

Duration of CLK pulse at low level tWLCLK 10 - -

Setup time of data input before low to high clock transition tSDAT 5 - -

Hold time of data input after low to high clock transition tHDAT 5 - -

Hold-time of STB after low to high clock transition tHSTB 5 - -

STB low level pulse duration tSTB 10 - -STB set-up time before CLK rise tSSTB 5 - -

ns ---

AC TIMING CHARACTERISTICS

Table 6. AC Timing Characteristics in TTL Mode

(Vcc = 5V, Vpp = 80V, Vssp = 0V, Vsssub = 0V, Vsslog = 0V, Tamb =25 °C, FCLK = 40MHz)

Parameter Symbol Min. Typ. Max. Unit Remark

Delay of power output change after CLK transition

- high to low

- low to high

tPHL1

tPLH1

-

-

-

-

100

100

Delay of power output change after STB transition (Note 6)

- high to low

- low to high

tPHL2

tPLH2

-

-

-

-

95

95

Delay of power output change after BLK, POC transition

- high to low

- low to high

tPHL3

tPLH3

-

-

-

-

90

90

Delay of logic output A1-A6, B1-B6 data after CLK transition

- high to low

- low to high

tPHL4

tPLH4

-

-

-

-

100

100

Power output rising time (Note 7) tROUT 50 - 200

Power output falling time (Note 7) tFOUT 50 - 200

ns

Vilmax =

0.2Vcc

Vihmin =

0.8Vcc

NOTES:

6. Because of the Charge Sharing operation, STB low level duration time is subtracted from delay (tPHL/PLH2).

7. One among 192 outputs, loading capacitor CL=50pF, other outputs at low level and STB low duration is shorter than

20nS




12

AC TIMING DIAGRAM (TTL MODE)

tCLK

tWHCLK tWLCLK

tSDAT tHDAT

tHSTBtSTB

tSSTB

tPHL2

tPLH2

tPHL1

tPLH1

tPHL3 tPLH3

50% 50% 50%

50% 50%

50% 50%

50% 50%

10%10%

CLK

AINPUT / BINPUT

STB

OUTn

BLK

(POC="L")

OUTn

tFOUT tROUT

90%

10% 10%

90%

LOGIC OUT

(A1- A6,

B1- B6)

tPHL4 tPHL4

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

CHARGE

SHARING

CHARGE

SHARING

10% 10%

Figure 3. AC Timing Diagram in TTL operation




13

RSDS TIMING CHARACTERISTICS

VIHRSDSVILRSDS VCMRSDS

VRSDS N

VRSDS P

GND

VIHRSDS

VILRSDS

0 VVRSDS P - VRSDS N

Figure 4. RSDS Basic Signal Diagram

Table 7. Specification of RSDS signal

Parameter Symbol Condition Min Typ Max Unit

RSDS high input voltage VIHRSDS VCMRSDS = +1.3V (Note 8) 100 200 -

RSDS low input voltage VILRSDS VCMRSDS = +1.3V (Note 8) - -200 -100

mV

RSDS common mode input

voltage rangeVCMRSDS

VIHRSDS = +100mV (Note 9)

VILRSDS = -100mV (Note 9) 0.9 - 1.3 V

RSDS input leakage current IDL An / Bn, An+1 / Bn+1,

LVCP,LVCN-10 - 10 uA

NOTES:

8. VCMRSDS = (VLVCP + VLVCN) / 2 or VCMRSDS = (V_An + V_ An+1) / 2

9. The positive sign means that An / Bn (or LVCP) is higher than RSDS ground An+1 / Bn+1 (or LVCN).

The negative sign means that An / Bn (or LVCP) is lower than RSDS ground An+1 / Bn+1 (or LVCN).




14

AC TIMING DIAGRAM (RSDS MODE)

tSMODE

50%

AINPUT

"1"

"0"

LVCP

MODE

tHMODE

tSDAT tHDAT

50%

"1"

"0"

"1"

"0"

Figure 5. AC Timing Diagram in RSDS mode

Table 8. AC Timing Characteristics in RSDS Mode

(Vcc = 5V, Vpp = 75V, Vssp = 0V, Vss = 0V, Tamb = 25°C, FCLK = 65MHz, unless otherwise specified) Parameter Symbol Min. Typ. Max. Unit Remark

Setup time of MODE transition tSMODE 0.5CK - -

Hold time of MODE transition tHMODE 0.5CK - -

Setup time of AINPUT transition tSDAT 5 - -

Hold time of AINPUT transition tHDAT 5 - -

ns -




15

OPERATION DESCRIPTION

DATA BUS CONFIGURATION

This table describes the position of the first data sampled by the first rising edge of the CLK signal.

For the first configuration described in the below table, (MODE =”H” and F/R _

= “L”), data on A1 bus sampled by the

1st clock pulse is applied on Output1. After 16 clock pulses this data will be shifted to Output192.

The shifting relationship between A1 - A6 and B1 - B6 data is as follows:

Table 9. The relationship between A1 to A6, B1 to B6 data corresponding to the MODE and F/R _

Data ShiftMODE F/R

_

INPUT

CLK 01 02 03 --- 14 15 16

Remark

A1

A2

A3

A4

A5

A6

Out

Out

Out

Out

Out

Out

01

02

03

04

05

06

07

08

09

10

11

12

13

14

15

16

17

18

---

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96H L

B1

B2

B3

B4

B5

B6

Out

Out

Out

Out

Out

Out

97

98

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

---

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

For

A1

A2

A3

A4

A5

A6

Out

Out

Out

Out

Out

Out

91

92

93

94

95

96

85

86

87

88

89

90

79

80

81

82

83

84

---

13

14

15

16

17

18

07

08

09

10

11

12

01

02

03

04

05

06H H

B1

B2

B3

B4

B5

B6

Out

Out

Out

Out

Out

Out

187

188

189

190

191

192

181

182

183

184

185

186

175

176

177

178

179

180

---

109

110

111

112

113

114

103

104

105

106

107

108

97

98

99

100

101

102

Rev




16

Data ShiftMODE F/R

_

INCLK 01 02 03 --- 30 31 32

L L

A1

A2

A3

A4

A5

A6

Out

Out

Out

Out

Out

Out

01

02

03

04

05

06

07

08

09

10

11

12

13

14

15

16

17

18

---

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

For

L H

B1

B2

B3

B4

B5B6

Out

Out

Out

Out

OutOut

187

188

189

190

191192

181

182

183

184

185186

175

176

177

178

179180

---

13

14

15

16

1718

07

08

09

10

1112

01

02

03

04

0506

Rev




17

INTERNAL FUNCTION DESCRIPTION

S6P1002 includes all the logic and power circuits necessary to drive column electrodes of a Plasma Display Panel

(P.D.P). Binary values of each pixel of a selected line are loaded into the shift register by a 12bit wide (A1 - A6, B1 –B6) data bus or a 6bit wide (A1 – A6 or B1 – B6) data bus depending on the configuration of the MODE input pin.

Data are shifted at each rising edge of the CLK clock.

The forward / reverse (F/R _

) input is used to select the direction of the shift register. The MODE input is used to

configure the shift register either in 12 X 16 bits or in 6 X 32 bits.

In case of 6bit mode (MODE = “L”), A1 to A6 pins are used. The 6 shift registers are loaded with 32 clock pulses. B1

to B6 pins are used as output pin for cascade connection. The maximum frequency of the shift clock is 40MHz. This

leads to an equivalent 480MHz serial shift register for a 12 X 16 bits shift register configuration.

When the STB signal is Low, data are transferred from the shift register to the latch and power output stages.

At that time, if the new output is contrary to previous output, Charge sharing operation is executed until rising edge. All the output data are kept memorized and held in the latch stage when the latch input STB is pulled high.

In RSDS mode operation, 3 input pairs (A1-A2, A3-A4, A5-A6) are used and differential signals are converted to TTL

signal in RSDS receiver. Converted 3 bit data are sampled to 6 bit data by double edge clock.

Vsssub and Vsslog must be connected as close as possible to the logical reference ground of the application.

S6P1002 is supplied with a 5 V power supply. All the logic inputs can be driven either by 5V CMOS logic, or by 3.3V

CMOS logic.

Table 10. Shift register truth table

Input pin status Shift register function

MODE F/R _

CLK Output

X L Rising edge Forward shift

X L H or L Steady

X H Rising edge Reverse shift

X H H or L Steady

H X X 12 bits shift register

L X X 6 bits shift register

Table 11. Power output truth table

Qn STB BLK POC Driver Output Comments

X X L X All L Output at low level

X X H L All H Output at high level

X H H H Qn Data latched

L L H H L Data copied

H L H H H Data copied




18

RSDS DATA SAMPLING DIAGRAM (MODE RISING TIME)

A[1]

1

A[2]

1

A[3]

1

A[4]

1

A[5]1

A[6]1

CLKP-CLKN

MODE

A[1:2]

B[1:2]

SFT_REG 1

tSDAT

tHDAT

IMOD=H

SFT_REG 2

SFT_REG 3

A[1]

1

A[1]

2

A[1]

3

A[2]1

A[2]2

A[2]3

A[3]

1

A[3]

2

A[3]

3

A[4]1

A[4]2

A[4]3

A[5]]

1

A[5]

2

A[5]

3

A[6]1

A[6]2

A[6]3

A[3:4]

B[3:4]

A[5:6]

B[5:6]

A[1]2

A[2]2

A[3]

2

A[4]

2

A[5]2

A[6]2

A[1]3

A[2]3

A[3]

3

A[4]

3

A[5]3

A[6]3

A[1]4

A[2]4

A[3]

4

A[4]

4

A[5]4

A[6]4

SFT_REG 4

SFT_REG 5

SFT_REG 6

1 2 3 4

tSMODE

Figure 6. Timing Diagram of RSDS Data Sampling when MODE is rising




19

RSDS DATA SAMPLING DIAGRAM (MODE FALLING TIME)

CLKP-CLKN

MODE

A[1:2]

B[1:2]

SFT_REG 1

tHMODE

IMOD=H

SFT_REG 2

SFT_REG 3

A[3:4]

B[3:4]

A[5:6]

B[5:6]

SFT_REG 4

SFT_REG 5

SFT_REG 6

14

14 15 16 1713

A[1]

A[3]

A[5]

A[2]

A[4]

A[6]

14

14 14

14 14

15

A[1]

A[3]

A[5]

A[2]

A[4]

A[6]

15

15 15

15 15

16

A[1]

A[3]

A[5]

A[2]

A[4]

A[6]

16

16 16

16 16

14

A[1]

A[3]

A[2]

A[4]

14

14 14

A[1] A[1] A[1]

A[2] A[2] A[2]

A[3] A[3] A[3]

A[4] A[4] A[4]

A[5]] A[5] A[5]

A[6] A[6] A[6]

A[5] A[6]

14 14

A[1] A[1]

A[2] A[2]

A[3] A[3]

A[4] A[4]

A[5]] A[5]

A[6] A[6]

1615141312

1615141312

1615141312

1615141312

1615141312

1615141312

Figure 7. Timing Diagram of RSDS Data Sampling when MODE is falling




20

TEST CONFIGURATION

Vpp=Vssp

Vssp

VdouthI douth

Vdoutl I doutl

Vssp

Vpp=Vssp

Output sinking current as positive value, sourcing current as negative value

Figure 8. Test circuit configuration for the Power Output Diode

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