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ELECTRONICS DIVISION TECHNICAL NOTE 195
IPG Continuum Data Collection System Tim Weadon
8/29/03
The "IPG" Continuum System was designed and built in 1998 by Rick Fisher, Rich Lacasse, Dwayne Schiebel and Tim Weadon. Rick specified the system requirements. Rich designed and built the Filter Amplifier system. Dwayne designed and built the Clock and Switching system and Tim designed and built and specified the computer associated hardware and software. Figure 1 is an over-all block diagram of the system.
The Filter Amplifier has one SMA input and one BNC output. There are three low-pass filters one may choose. The single pole three throw switch (SP3T) allows the user to select either a 50Hz, 500Hz or 5000Hz low-pass filter.
The Clock and Switching system inputs 4 differential signals and routes them, through the ribbon cable, to the computer A/D card. Only one signal was originally requested so the system, presently, only supports one input on the first channel. This system has thumb-wheel switches to set the hardware parameters "sample rate", "switch rate" and "cycles/integration".
The enable/stop switch arms and disarms the system from any spurious signals which could trigger a false start. The thumb-wheel switches should be set when this switch is in the stop position. Once the thumb-wheel switches are set, and the computer system is on and stable, this switch may be set to the enable position. When you wish to begin a new scan the enable/stop switch should be set to stop, the thumb-wheel switches should be set, then the enable/stop switch should be set to enable. The Switch Control LED and the Recording Data LED will be flashing when the clock and switching system is running.
The Clock and Switching system provide an interrupt to the computer A/D for when to sample the data. The computer provides the "go" signal to the Clock and Switching system for when it is to start generating the clock and switching signals.
The Computer and associated hardware provide the user interface for collecting, documenting and analyzing the data. The user enters a filename and description of the data. The number of samples to blank after each switch cycle, the sample rate, switch cycle and cycles/integration. The program generates two files. The first is filename.rfi and the second is filename.rf2. Filename.rfi contains the configuration data such as sample rate, switch cycle, samples/integration, etc. Filename.rfZ contains the raw "streamed" data.
When setting up for a scan the user first sets the thumb-wheel switches and enables the Clock and Switching System. Provisions for reading the thumb-wheel switches were not made or requested so the thumb-wheel positions should be repeated on the computer GUI panel. The total number of A/D conversions (samples) is determined from this data and is used by the program for when to quit sampling, so it is important to set the switches correctly or you will not know how many samples to wait for. Otherwise this data does not affect the collection
of the data but is used by the plotting and analysis software so it is stored for later reference. The Scan Complete "LED" on the GUI screen will turn green when all the data is collected. (If this LED turns green before the Clock and Switching system LEDs stop switching or if it stays black after the Clock and Switching system stops then you know your thumb-wheel switches do not match your GUI settings.)
The GUI panel allows you to collect, load and plot / analyze data which has just been collected or data which was collected sometime in the past. When you specify the filename then press the "Read&Plot" or "Fold&Plot" or "FFT" switches the computer reads the associated filename and performs the appropriate analysis on the data. A picture of the GUI panel is shown below in figure 2.
"Read&Plot" allows the user to plot out all the data collected. The X-axis is sample number and the Y-axis is the amplitude in volts. "Fold&Plot" averages each "cycle" of data and plots one cycle of the average of all the data. "FFT' performs an FFT on the data. The X-axis is Hz and the Y-Axis is power. The boxes labeled "Sig/Ref', "Sig-RetfRef', "SIG" and "REF' are the accumulative counts of SIG and REF and the associated equation on that data. It is only filled in when you do the scan, not during post processing.
Figure 2
Instructions to run the IPG RFI computer software. (Appendix A)
1. Turn on the computer and associated equipment. 2. Log on to the computer. 3. Double click on the IPG RFI Test Software Icon. 4. Click on the "File" button in the "fileRFT box. 5. Enter the filename you wish to store your data to or read data from. 6. Fill in the descriptions entry. 7. Set the thumb-wheel switches on the metal box beside the computer to the desired
settings and the "Enable/Stop" switch to Enable". 8. Set the Radio Buttons on the IPG RFI Panel to what you set the thumb-wheel
switches to. 9. Press "SCAN" when you are ready to collect data. (Data is presently only
collected on input channel 0.) 10. The Scan Complete light will be black during the scan and it will turn to green
when the scan is complete. 11. The "Time Graph" will be plotted when the Scan is complete. 12. The data is now in the file you selected in step 5 above. 13. Press "Read&Plot" to read data from the file and plot it in the 'Time Graph
Window". 14. Press "Folt&Plot" to flod each cycle from the selected file into one cycle and plot
the resulting "average" cycle. 15. Press "FFT" to run and plot the FFT on the data in the file selected.
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Continuin Systen Filter Amplifier (Lacasse)
REVISIONS
Continuin Systen Clock and Switching Hardware (Schiebel)
Continuin Systen Conputer & Hardware (Weadon)
APPROVED
Signal Input <SMA)
Signal Output <BNC)
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IPG Continuum Systen Dwgt T. Weadon
Datei 8/29/03
SIZE FSCM NO.
SCALE N/A
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SHEET 1/1
PP3 S0.OK
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lOOOpF
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11
FIGURE 9A. PP3 Inverting Pole-Pair Subcircuit.
1 > HP Out c >BPOut OLPOut
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FIGURE 9B. Inverting Pole-Pair Subcircuit Using R3 to Eliminate External Q-Setting Resistor RQ.
R }nse: Lowpass Tyjf«3 : Butterworth
UAF42 Filter Component Values
Topology: Inverting f-3dB Order n Resistors
: 50.00Hz : 6 : exact
Subckt fo Q fz RFI, 2 C ext Rp Cp Rzl Rz2
RQ RG R2A Rz3 Ckt-gain
Sub PP3 Ckt 1
Sub PP3 Ckt 2
Sub PP3 Ckt 3
50.00Hz 517.6m
50.00Hz 707.1m
50.00Hz 1.932
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3.183M 44.59k 50.00k 1.000
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Filter Block Diagram
Subckt 1 Subckt 2 Subckt 3
Lp Lp Lp In Out In Out In Out
Build this filter by connecting filter subcircuits in order as shown in the 'Filter Block Diagram' above. See Application Bulletin AB-035 for detailed schematics of subcircuits. When no value is shown for a component in the 'Filter Component Values' table, omit the component.
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UAF42
FIGURE 9A. PP3 Inverting Pole-Pair Subcircuit.
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FIGURE 9B. Inverting Pole-Pair Subcircuit Using R3 to Eliminate External Q-Setting Resistor RQ.
UAF42 Filter Component Values
R }nse: Lowpass Ty**^ : Butterworth
Topo1ogy: Invert ing f-3dB Order n Resistors
500.0Hz 6 exact
Subckt fo Q fz RFI, 2 RQ RG C ext Rp Cp Rzl Rz2 Rz3 Ckt-gain
R2A
Sub Ckt 1
Sub Ckt 2
Sub Ckt 3
PP3
PP3
PP3
500.0Hz 517.6m
500.0Hz 707.1m
500.0Hz 1.932
318.3k 90.43k 50.00k 1.000
318.3k 44.59k 50.00k 1.000
318.3k 10.43k 50.00k
Subckt 1
Filter Block Diagram
Subckt 2 Subckt 3
In PP3
Lp Out In
PP3
Lp Out In
PP3
Lp Out O VOUT
Build this filter by connecting filter subcircuits in order as shown in the 'Filter Block Diagram' above. See Application Bulletin AB-035 for detailed schematics of subcircuits. When no value is shown for a component in the 'Filter Component Values' table, omit the component.
Passband gain Max Input
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FIGURE 9A. PP3 Inverting Pole-Pair Subcircuit.
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FIGURE 9B. Inverting Pole-Pair Subcircuit Using R3 to Eliminate External Q-Setting Resistor Ro-
R' xmse: Lowpass •: : Butterworth
UAF42 Filter Component Values
Topology: Inverting f-3dB Order n Resistors
5.000kHz 6 exact
Subckt fo Q fz RFI, 2 RQ RG R2A C ext Rp Cp Rzl Rz2 Rz3 Ckt-gain
Sub PP3 Ckt 1
Sub PP3 Ckt 2
Sub PP3 Ckt 3
5.000kHz 517.6m
5.000kHz 707.1m
5.000kHz 1.932
31.83k 90.43k 50.00k 1.000
31.83k 44.59k 50.00k 1.000
31.83k 10.43k 50.00k
Subckt 1
Filter Block Diagram
Subckt 2 Subckt 3
In VT" O PP3
Lp Out In
PP3
Lp Out In
PP3
Lp Out O VOUT
Build this filter by connecting filter subcircuits in order as shown in the 'Filter Block Diagram' above. See Application Bulletin AB-035 for detailed schematics of subcircuits. When no value is shown for a component in the 'Filter Component Values' table, omit the component.
Passband gain Max Input
1.00 V/V (0 dB) 10.00 V (Vs=+-15V)
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Pin assignments for I/O connectors Jl and J2 of the STA-1800U screw terminal accessory are shown in Figure B-2.
(User Common Mode) U_CM MD - 01 CH00LOorCH08HI-03 CH01LOorCH09HI-05 CH02LOorCH10HI-07 CHOSLOorCHII HI -09 CH04LOorCH12HI-11 CH05LOorCH13HI-13 CH06LOorCH14HI-15 CH07LOorCH15HI-17
0DAC2 (Note 2)-19 ODAC3(Note2)-21
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DGND-27 29 31 33 35
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DAS-1701AO, and DAS-1702AO boards only 2 DAS-1701ST-DA and DAS-1702ST-OA boards only
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Figure B-2. STA-1800U I/O Connectors Jl and J2
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