Electronics Laboratory II EECS 3440 Lab Manualrking/3440lab/LabManual3440.pdfElectronics Laboratory II EECS 3440 Lab Manual January 2002 ... Experiment 3 SPICE Simulation of a JFET

Electronics Laboratory II

EECS 3440

Lab Manual

January 2002rev. 2editor

Roger King, prof. EECS

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Foreword

This lab is a continuation of the lab experience included with the course Electronics I.As such, it would be repetitious to include the sections describing the equipment, documentingprocedures, or reviewing SPICE. For the same reason, a comprehensive set of data sheets is notincluded in this lab manual. (The PN2222A data sheet is included because of its frequent use.)It is assumed that the student has retained a copy of the lab manual from the Electronics I(EECS 3400) course.

The main new topics covered by this lab are frequency response and feedback in analogelectronic systems. These are fundamental for any practical electronics, and in addition, each ofthese has a counterpart in the digital signal processing world. An understanding of the behaviorof the analog system is the best preparation for an understanding of the correspondingdigital-domain behavior. As with Electronics I, this lab will also emphasize the use of SPICEalong with hands-on experimentation to gain an intuitive understanding of the electronicsinvolved. The student is encouraged in each experiment to simulate the lab using SPICE, tohand work a simplified analysis, and to compare these with the observed experimental behavior.

This lab is continually being redeveloped. Please give the instructor your feedbackconcerning the lab experiments and procedures so that the future manuals can be as error-free aspossible.

Prof. Roger King, EECSJuly 1998

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Table of Contents

51Data Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47Experiment 13 Analog/Digital Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43Experiment 12 Wien Bridge Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39Experiment 11 Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35Experiment 10 Negative Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Experiment 9 Complementary-SymmetryPush-Pull Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

27Experiment 8 Differential Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Experiment 7 BJT High-FrequencyPerformance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

19Experiment 6 Bypass and Coupling CapacitorEffects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15Experiment 5 Small-Signal CC and CBAmplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11Experiment 4 JFET Common-SourceAmplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9Experiment 3 SPICE Simulation of a JFETCommon-Source Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5Experiment 2 ‘741 Op-Amp Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Experiment 1 SPICE Modeling the ‘741Op-Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

v

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Experiment 1 SPICE Modeling the ‘741 Op-Amp

Introduction

The purpose of this experiment is to gain experience with ac and transient SPICEsimulation procedures, and to learn about the slew rate and bandwidth behaviors of a typicalgeneral-purpose op-amp. A simple model of the internal structure of the ‘741 op-amp will beused.

Equipment Needed

v SPICE model for a ‘741general-purpose op-amp

v PC running a current version ofPSpice

Procedure

Use PSpice to run an analysis of the circuit of Fig. 1. A model for the ‘741 op-amp isgiven in Fig. 2. (The model in Fig. 2 is also available from the instructor on disk.) The actualcircuit requires two 15-V power supplies for the op-amp; the model in Fig. 2 works withouthaving to explicity show these power supplies. Most general purpose op-amps have two internalstages of gain: the first one is modeled in Fig. 2 as the voltage-controlled current sourceGstage1, and the second one is modeled as the voltage-controlled voltage source Estage2.

1. Make the input source Vin a pulse voltage source (VPULSE) in series with a transientsine source (VSIN). Set the ac component of VPULSE to 1 V, and its pulse componentto transition from -1 V to +1 V as a square wave with a period of 400 μs (200 μs at -1 V,and 200 μs at +1 V). Set up VSIN for an offset voltage of 0, an amplitude of 50 mV, anda frequency of 40 kHz. The input voltage to the inverting amplifier will then be a 1-V acsignal during the ac analysis (a steady-state phasor analysis), and it will be a 50-mV40-kHz sine wave added to a 1-V 2.5-kHz square wave during the transient simulation.

2. Run an ac sweep from 0.1 Hz to 10 MHz, and a transient simulation for 500 μs.

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Fig. 1 Inverting amplifier using a ‘741 op-amp.

3. Use PROBE to view the results of the ac sweep. The input ac voltage Vin will have aconstant magnitude of 1 V (0 dB); display the dB magnitude of the output voltage Vout.Determine the high-frequency cutoff of the inverting amplifier by finding the frequencyat which the output is reduced to 3 dB less than its low-frequency value.

4. Determine why the gain of the inverting amplifier is not constant up to a very highfrequency. Use PROBE to plot the gain of the op-amp itself by adding the plotDB(Vout/-Vid) to the previous plot. Note that -Vid is the input voltage to the op-amp,not the input voltage to the circuit. Print this composite plot of the inverting circuit gaintogether with the op-amp gain for a frequency range of 0.1 Hz to 10 MHz.

5. Use PROBE to view the results of the transient run. Plot the output voltage Vouttogether with -10 times the input voltage Vin. Ideally, these two traces should coincide.However, there will be some notable discrepancies. Print this composite plot.

6. The output voltage will show evidence of slew rate limiting at the times that the squarewave transitions. During this time, the Vout rises or falls with a well-defined slope, andthe small sinusoidal component of signal disappears. To find out why, add an additionalY-axis to the plot and add a trace of the output current leaving the first stage, I(Gstage1).The vertical scale of this new Y-axis should be -15 μA to +15 μA, and there should beevidence that the current output of stage 1 is clipping. Print this composite plot.

Report

There is no formal report for this lab. Simply record your findings and comments andsubmit them in a homework format. In the following, be careful to distinguish the op-amp byitself from the complete amplifier circuit of Fig. 1. Please answer the following questions:

1. What is the voltage gain (in dB) of the circuit of Fig. 1? VoutVin

2. The high-frequency cutoff fH is defined as the frequency at which the gain is down to3 dB less than its low-frequency value. What is the value of fH for this amplifier?

3. What is the voltage gain of the op-amp itself (in dB) at very low frequencies?VoutVid

Describe the variation of the op-amp gain with respect to frequency. What is the value offH for the op-amp by itself?

4. Describe the behavior of this inverting amplifier when it is producing a 10-Vsquare-wave output voltage, especially with regard to the regions where Vout is intransition. Why does the sine waveform disappear from the output waveform during thetransition times?

SPICE Modeling the ‘741 Op-Amp

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Table 1Device Parameters for the Inverting Amplifier SPICE Model

Dbreak D(IS=1E-14CJO=0.1pFRS=0.1)

TABLE=(-50mV,-13V)(+50mV,+13V)

TABLE=(-75mV,-15uA)(+75mV,+15uA)

DC=0AC=0VOFF=0VAMPL=50mVFREQ=40kHz

DC=0AC=1VV1=-1VV2=+1VTD=200usTR=0TF=0PW=200usPER=400us

D1 & D2Generic diodes

(use Dbreak model)

Estage2Voltage amplifier

(VCVS) withsaturation

Gstage1Transconductanceamplifier (VCCS)

with saturation

VSINInput source for

transient sine wave

VPULSEInput source for ac

steady state +transient square

wave


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Fig. 2 Inverting amplifier with ‘741 op-amp model.


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Experiment 2 ‘741 Op-Amp Circuits

Introduction

The purpose of this experiment is to gain experience with the '741 op-amp in severaltypical applications, and to discover some of the basic limitations of all op-amps. The observedbehavior of the inverting amplifier will be compared with the simulated behavior fromExperiment 1.

Pre-Lab

It is expected that Experiment 1, "SPICE Modeling the '741 Op-Amp," has already beenperformed.

Equipment Needed

v Power supplies, functiongenerator, oscilloscope

v LM741/MC741/SN741 op-amp(prefix indicates manufacturer)

Procedure

1. Connect the circuit of Fig. 1. Use a 100-mV peak 1-kHz sine wave input voltage tomeasure the system voltage gain . (The expected result is -10.) To reduce theAv = vo

vihigh-frequency noise on the scope channel handling the 100-mV signal, turn on itsbandwidth limit, found on the channel input menu.

2. Measure the high-frequency cutoff (fH) of Fig. 1 using a 100-mV sine wave input andmonitoring the output voltage. Starting at 1 kHz, increase the frequency of until thev ioutput has decreased to 70.7% of its 1-kHz value. Record this -3 dB frequency as fH .v o(The expected value of fH is about 90 kHz.)

3. Collect two output voltage waveforms from Fig. 1 and display them simultaneously usingthe memory capability of the DSO. Focus on the rising edge of the square waveresponse. Display and record:

a) The response to a 50-mV peak 1-kHz square wave. Measure the slope of the risingedge of the response using a horizontal scale of 0.5 μs/div, and a vertical scale of0.2 V/div.

b) The response to a 500-mV peak 1-kHz square wave. Measure the slope of the risingedge of the response using a horizontal scale of 5 μs/div, and a vertical scale of 2 V/div.

4. Measure the slew rate (SR) capability of the '741 op-amp from the recorded response of(b) above. (The expected value of SR is about 0.5 V/μs.) Try increasing the amplitude

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of the input square wave. Can the output voltage attain a rate-of-change any greater thanyour measured slew rate?

5. Connect Fig. 2. Measure the voltage gain of Fig. 2 using a low amplitude 1-kHz sinewave. (The expected result is +11.)

6. Connect Fig. 3 and display the input and output voltage waveforms together, using a0.5-V peak 1-kHz square wave for . Does the output appear to satisfy the followingv itransfer function?

vo = −1RiCf

¶0tvi(t) dt + vo(0)

7. Record this square wave input with its triangle wave response. Record the input/responsepair for a 1-kHz sine wave.

Report

1. Compare the 1-kHz voltage gains measured for Figs. 1 and 2 with those predicted byideal op-amp equations.

2. Compare the high-frequency cutoff measured for Fig. 1 with that predicted by the SPICEsimulation in Experiment 1. Use the SPICE model for the '741 op-amp to explain whythe circuit gain decreases at frequencies above fH .

3. Compare the slew rate measured for Fig. 1 with that predicted by the SPICE simulationin Experiment 1. Does increasing the input voltage amplitude beyond 1 V increase theslew rate observed at the output? Why?

4. Do the integrator responses observed in steps 6 and 7 agree with the equation given foran ideal op-amp? Compare the shapes and amplitudes of the predicted and observedresponses to square wave and sine wave inputs.

‘741 Op-Amp Circuits

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Fig. 2 Non-inverting amplifier.

Fig. 3 Integrator.

Fig. 1 Inverting amplifier, 8-pin dual-in-line plastic package (top view).


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Experiment 3 SPICE Simulation of a JFET Common-Source Amplifier

Introduction

The purpose of this experiment is to gain practical experience with the mechanics of theSPICE simulations for bias point and ac analysis. The circuit used is a JFET common-sourceamplifier.

Pre-Lab

There is no pre-lab for this experiment.

Equipment Needed

v Current version of PSpice

Procedure

Turn on the PC and open the current version of PSpice. Enter the circuit of Fig. 1 usingthe library model for the 2N5457 JFET. The signal source Vin should be an ac source, set to anamplitude of 1 V, and with its dc component set to 0 V.

1. Set up the simulation for a detailed bias point solution, a dc sweep, and an ac sweep. Thebias point solution will consist of a detailed listing of the operating-point solution in theoutput file, along with calculated incremental model parameters for the JFET. Set the dcsweep to step the dc value of source Vin from -5 V to +5 V in 0.1-V steps. Set the acsweep to step the frequency of the ac content of Vin from 1 Hz to 100 kHz in 101 steps

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Fig. 1 JFET common-source amplifier.

per decade.

2. After running the simulation, examine the output file to find the bias point solution. TheJFET drain-source voltage (VDS) must be more than 2 V, and the drain current (ID) mustbe more than 0.1 mA. If the bias point does not represent a reasonable operating pointfor an amplifier, there is no point in proceeding further - something has gone wrong inthe entry of the schematic, or the design of the circuit. Note: Later versions of SPICEallow you to enable direct display of the bias point solution on the schematic diagram.Record ID and VDS .

3. Use probe to display the dc sweep results. Plot the output voltage Vo vs. the inputvoltage Vin. Use the “add trace” menu to add a plot of the derivative of Vo [the syntax is“D(V(Vo))”]. Record these traces.

4. Use probe to display the ac sweep results. Plot the dB equivalent of the output voltageVo vs. frequency. (Vin should be 0 dB at all frequencies.) Record this trace.

Report

No formal report is required for this experiment. Simply summarize the results you haveobtained in a homework format. Briefly answer the following questions:

1. Discuss the location of the optimum Q-point for this amplifier using the plot of Vo vs.Vin obtained from the dc sweep. Use the plot of the derivative of Vo to estimate the gainat this Q-point. At what values of Vo (upper and lower) will the amplifier saturate?

2. Discuss the voltage gain of the amplifier as measured at various frequencies. Why doesthe voltage gain vary with frequency?

3. For what range of frequencies does the voltage gain read from the ac sweep agree withthe incremental voltage gain read from the dc sweep? Why?

Notes on SPICE

SPICE computes the bias point analysis by setting all ac and transient components of allsources to zero, and considering only the dc components of these sources. The dc sweep iscomputed by stepping the dc component of the source specified in the dc sweep setup statement.During dc analyses, capacitors are open circuits; and inductors are short circuits.

When SPICE does an ac sweep, it first uses the dc source values to compute the dc biaspoint solution. It then computes incremental models for all devices in the circuit based upon thebias point. After this, SPICE applies an ac steady-state analysis to the incremental equivalentcircuit over the frequency range given in the setup. The ac amplitude of the source Vin can beset to any convenient value without causing amplifier saturation because the incremental modelis always a linear model.

SPICE Simulation of a JFET Common-Source Amplifier

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Experiment 4 JFET Common-Source Amplifier

Introduction

The purpose of this experiment is to investigate the performance of a JFETcommon-source amplifier.

Equipment Needed

v For alternate VP and IDSS , youmay substitute 2N5458/59

v 2N5457 n-channel JFETv Normal laboratory equipment

Pre-Lab

Estimated typical values of the JFET parameters are: VP = -2.5 V and IDSS = 3 mA.Obtain a 2N5457 data sheet and find out what the allowable ranges of these parameters are.Read the text file of the 2N5457 SPICE model currently used in this department and determinewhat values the model assumes for these parameters.

Procedure

1. Obtain the FET drain characteristics using the curve tracer. Measure the pinchoff voltageVP and the zero-bias drain current IDSS. Make sure these lie within the ranges promisedon the 2N5457 data sheet. Record the measured values of these two parameters, but youdo not need to record the drain characteristics.

2. Connect the circuit of Fig. 1 without C1 and measure its quiescent operating point (IDQ

and VGSQ).

3. Set the function generator for a 5-kHz sine wave with zero dc offset. Increase the FGvoltage level until the output voltage is on the verge of clipping-type distortion.Vo

Record the output waveform, showing evidence of the voltage levels at which clippingwill occur.

4. Reduce the signal level to assure an undistorted output. Measure and record the voltagegain at 5 kHz. Place C1 into the circuit and record its effect on the voltageAv = Vo

Vigain.

5. With C1 in the circuit, measure and record the amplitude and phase of the output voltage(relative to the input voltage) at the following frequencies: 5 kHz, 500 Hz, 50 Hz.

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Report

1. Use the measured values of VP and IDSS to predict the Q-point (IDQ and VGSQ). Comparethese values with the experimentally-measured values. Compare these values with theprediction of a SPICE bias point solution using the 2N5457 model.

2. Use the measured values of VP and IDSS to estimate the transconductance (gm). Calculatethe midband voltage gain (the 5-kHz gain) with and without C1, and compare with theexperimentally-measured values. Also, compare the measured 5-kHz gain with the resultof a SPICE ac analysis.

3. Estimate the maximum possible output voltage before the onset of severe distortion.Consider clipping due to the drain current going to zero, and distortion due to the JFETentering its ohmic region of operation. Compare these estimates with your observed data.

4. Comment on the observed frequency response data. What happens to the signal as itsfrequency is lowered below midband? Why? Compare these experimental results withthe results of a SPICE ac frequency sweep.

Background

Refer to your electronics text for background on modeling the JFET. For the purpose ofthis experiment, it is OK to ignore channel-length modulation in modeling the JFET. Be awarethat various electronics books may present the following equations using different symbols.

iD = IDSS 1 − vGS

VP

2

andgm = ØiD

ØvGS Q point

= 2IDSS−VP

1 − VGSVP

= 2VP

IDSS $ ID

where

IDSS = zero-gate-voltage drain current, and VP = pinchoff voltage.

The equations above are valid only in the constant-current (saturation, or pinch-off) region.

JFET Common-Source Amplifier

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Fig. 1 JFET common-source amplifier.

Fig. 2 2N5457 case and pin-outs.


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Experiment 5 Small-Signal CC and CB Amplifiers

Introduction

The purpose of this experiment is the measurement of the small-signal voltage gain, inputresistance, and output resistance of a common-collector (emitter follower) and a common-baseamplifier. These two circuits are then compared to each other.

Equipment Needed

v PN2222A npn transistorv Normal laboratory equipment

Procedure

Connect the circuit of Fig. 1 and measure its quiescent operating point (ICQ and VCEQ).Connect a 5-kHz sine wave signal source to the input terminals, and a 100-Ω load resistor to theoutput. Measure the following small-signal amplifier parameters using a signal level low enoughto avoid clipping, yet high enough to be measurable.

1. Measure the voltage gain . Av =VoVi

2. Measure the input resistance . Ri∏

3. Measure the output resistance . Ro∏

Connect the circuit of Fig. 2 and measure its quiescent operating point (ICQ and VCEQ).Connect a 5-kHz sine wave signal source to the input terminals, and a 10-kΩ load resistor to theoutput. Measure the same small-signal amplifier parameters as previously. Remember to keepthe signal level small enough to avoid any visible distortion of the sinusoidal waveforms.

1. Measure the voltage gain . Av =VoVi

2. Measure the input resistance . Ri∏

3. Measure the output resistance . Ro∏

Use the curve tracer to measure the incremental current gain (βac = hfe) of your transistorin the neighborhood of IC = 1 mA, VCE = 10 V.

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Report

1. Using reasonable approximations, predict the Q-point of Figs. 1 and 2, assuming thatβdc = 150. Compare this with the experimentally measured Q-point.

2. Using the values of βac (hfe) and Q-point which were measured experimentally, predict thefollowing: , , , , and for Figs. 1 and 2. Av Ri Ri

∏Ro Ro

∏

3. Compare these calculated values with the experimentally-determined values. Comparethe relative values of , , and for Figs. 1 and 2. Based on simplified formulas,Av Ri Ro

give the most important factor(s) which determine , , and for Figs. 1 and 2. Av Ri Ro

Small-Signal CC and CB Amplifiers

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Fig. 2. Common-base amplifier.

Fig. 1 Common-collector (emitter follower) amplifier.

Fig. 3 PN2222A package and pin-out.

Appendix: The Experimental Determination of Voltage Gains and Incremental Resistances

1. Voltage gain is measured with a specified load resistor in place by monitoring and Vi Vo

with a two-channel scope. The smallest measurable level is used; the measurement isonly valid if no appreciable distortion occurs in either or . Vi Vo

2. Input resistance can be measured by monitoring while driving the amplifier from aRi∏

Vo

source having a known source resistance (RS). Then, using a variable resistor in serieswith the source, the source resistance is increased until drops to one-half its previousVo

value. We have:

3. (first measurement), and (1)Vo1 = Av VsRi∏

Ri∏ +Rs

(second measurement) (2)Vo2 = Av VsRi∏

Ri∏ +Rs +Rpot

4. Therefore:

(3)Vo1Vo2

= 12 =

Ri∏ +Rs

Ri∏ +Rs +Rpot

(4)Ri∏ = Rpot − Rs

5. The input resistance is calculated from the measured value of the variable resistor Ri∏

( ) and the value of the source resistance ( ). For the FG in the electronics lab, Rpot Rs

. This measurement is only valid for small (undistorted) signals. is easilyRs = 50 Ri

calculated from . Ri∏

6. Output resistance is measured by monitoring while driving the amplifier with a Ro∏

Vosignal source having the specified source resistance ; is first measured, and then aRs Vo

variable resistor is paralleled with the output terminals and adjusted so that is one-halfVo

its previous value. The resistance of the potentiometer is then equal to the outputresistance . This measurement is only valid for small signals. is easily calculatedRo

∏Ro

from . Ro∏


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Experiment 6 Bypass and Coupling Capacitor Effects

Introduction

The purpose of this experiment is the measurement of the low-frequency response of anac-coupled amplifier.

Equipment Needed

v Switchable 0-dB/40-dB 50-Ωattenuator


Pre-Lab

Calculate the expected locations of the poles and zeros contributed by each capacitor inFig. 1 (they each act independently). Calculate the midband gain, and sketch a Bode plot of theexpected magnitude of the voltage gain from 1 Hz to 10 kHz.

Procedure

Gain will be measured over a wide range of values in this experiment: The amplitude ofthe input signal may need to be changed in order to maintain a measurable output level, but at alltimes keep the levels low enough to avoid appreciable distortion, yet high enough to bemeasurable. You will need to use a switchable 0-dB/40-dB 50-Ω attenuator at the FG output todo this. Turn on the bandwidth limiters in both channels of the scope to reduce anyhigh-frequency noise present in low-level signals.

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Fig. 1 Common-emitter amplifier with blocking and bypass capacitors.

1. Connect the circuit of Fig. 1 and measure its operating point (IC and VCE). Note that thefunction generator (FG) must be connected to provide a dc path for the base current.Make sure that the operating point is reasonable for operation as an amplifier.

2. Set the FG to produce a 7-mV rms 10-kHz sine wave at Vi and measure the midbandgain at 10 kHz. (Expected value is about +40 dB.) Make sure that both scope channelsare dc-coupled throughout this procedure. An ac-coupled scope channel is itself ahigh-pass filter.

3. Measure the gain magnitude (in dB) over the frequency range of 10 Hz to 10 kHz. Markthe data points on your predicted frequency response plot. If there is a deviation of morethan 6 dB, you should investigate the reason for the discrepancy. Use the 2-channelscope to measure the peak-to-peak values of Vi and Vo for the purpose of measuring gain.

Details Lower the frequency by steps in a 10-4-2-1 sequence (e.g., 1 kHz - 400 Hz -200 Hz - 100 Hz), taking gain magnitude measurements at each step. You may need toincrease the input signal level at lower frequencies to maintain a measurable outputsignal. Take data from 10 kHz down to 100 Hz. Continue going down in frequencytowards 10 Hz as far as meaningful data can be obtained. Use "averaging1" (found in thescope Display menu) to reduce the amount of noise on small signals.

4. Divide the midband gain measured in part 1 by 1.414 (this is equivalent to subtracting3 dB from its decibel value). Use the FG to experimentally measure the frequency atwhich the amplifier's gain is 3 dB below its midband value. This is called the"low-frequency cutoff."

Report

1. Bode plot the pre-lab calculated frequency response on 4-cycle semi-log paper. Use dBnotation, and use a frequency range of 1 Hz to 10 kHz.

2. Mark the experimental data points on this graph. Do they agree well with the predictedvalues?

3. Identify the midband gain from the experimental data, and from the calculated response.How do they compare?

4. Identify the low-frequency cutoff (fL) from the experimental data, and from the calculatedresponse. How do they compare?

Bypass and Coupling Capacitor Effects

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1 "Averaging" is the process of storing repeated acquisitions of the waveform, each one based on the triggerevent, and point-by-point averaging these stored waveforms to produce the display. Averaging only works if thereis a stable trigger event.

Bode Plots

The actual gain vs. frequency plot of an ac-coupled amplifier is a smooth curve.However, Bode pointed out that if semi-log paper is used, a series of straight-line asymptoticapproximations to the gain curve will be close enough for many engineering purposes. The gainmagnitude in dB is placed on the linear scale; the frequency is placed on the log scale. Fig. 2below shows sample Bode plots of the contribution of the emitter bypass C1 acting alone (upperfigure), and the collector blocking capacitor C2 acting alone (lower figure).


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Fig. 2 Bode plot of frequency response of C1 alone (upper figure); and C2 alone (lower figure)


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Experiment 7 BJT High-Frequency Performance

Introduction

The purpose of this experiment is the investigation of the high-frequency performance ofa BJT common-emitter amplifier. The transistor junction capacitances Cπ and Cμ will beestimated from typical data sheet information.

Equipment Needed


Pre-Lab

Study the appendix to this lab which shows how to estimate the transistor junctioncapacitances on the basis of the limited information typically given on a data sheet.

Procedure

The circuit of Fig. 1 may not maintain a stable dc operating point; therefore, you shouldverify at several stages during the experiment that the operating point is still 5 mA/5 V (IC/VCE).The collector current is controlled by adjusting VBB , and the collector-emitter voltage is then setby adjusting VCC . Be sure to remove the dc voltmeter or milliameter from the circuit whenmaking the actual gain measurements. Gain will be measured from midband (5 kHz) to beyondthe high-frequency cutoff fH (1 MHz).

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Fig. 1 Common-emitter amplifier.

1. Connect Fig. 1 using a 1 K load resistor (RL). Set the dc operating point and remove all

dc meters from the circuit. Measure the midband gain factor at 5 kHz using a smallVoVi

signal. Measure the transistor base-emitter resistance at 5 kHz by measuring the acsignal at each end of R1.

2. Take gain measurements from 5 kHz to 1 MHz. The objective is to accurately determinethe high-frequency cutoff (fH). Take enough data points to be sure of the value of themidband gain, and the frequency at which the gain is reduced to 70.7% of its midbandvalue. (Expected midband gain and hf cutoff are about -100 and 400 kHz.)

3. Change the load resistor (RL) to 560 Ω. Readjust the dc operating point to maintain5 mA/5 V. Measure the midband gain and the high-frequency cutoff again. (Theexpected values are now 56% and 179% of the previous measurements, respectively.)

Report

1. Obtain a copy of the transistor data sheet for type 2N2222A or PN2222A, and put it in anappendix to your report. Use the data sheet to estimate values for Cπ and Cμ .

2. Calculate the midband gain and high-frequency cutoff for each of the two values of loadresistance used. Compare these results with the experimental data.

3. Use SPICE to simulate the frequency response of the experimental circuit. Compare themidband gain and high-frequency cutoff predicted by SPICE with your calculated andobserved data. After running your simulation successfully, open the *.OUT file and readthe values for Cπ and Cμ that were produced by SPICE. Compare these with yourestimated values.

BJT High-Frequency Performance

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Appendix A - Estimating Cπ and Cμ From a Data Sheet

The capacitance associated with a pn junction has two components: the transitioncapacitance, which is a nonlinear function of the junction voltage; and the diffusion capacitance,which is directly proportional to the junction forward current.

In the active mode, the collector-base junction is reverse-biased, and therefore it has onlytransition capacitance, whose value is determined by the dc collector-base voltage. Thiscapacitance is denoted Cbc , Cμ , Cob or "output capacitance" on most data sheets. A completedata sheet will typically contain a graph of Cμ vs. collector-base reverse voltage. An abbreviateddata sheet will at least give a single value for Cμ . Note that the transition capacitance increaseswith decreasing reverse-bias, reaching its maximum value at zero bias.

In the active mode, the emitter-base capacitance is composed of both transition anddiffusion components. The transition component is generally small and independent of operatingpoint (VBE is almost constant at 0.7 V); the diffusion component is generally large and directlyproportional to emitter current. The foregoing is true when the transistor is used at normalcurrent densities: In a large transistor used at low current, Cπ will not be zero; it will approach alower limit equal to its transition capacitance. The transition component of Cπ can be estimatedfrom the data sheet as the zero-voltage limiting value of the reverse-biased emitter-basecapacitance. The diffusion component of Cπ is directly proportional to IE , and is never directlygiven on the data sheet.

The short-circuit unity-current-gain frequency (denoted fT and frequently called thecurrent gain-bandwidth product, or GBW) is normally found on the data sheet. It can be shownthat this is related to the junction capacitances by:

2 fT = gmC + C

If the proposed operating point current (IE ) is within one decade of the operating point used inmaking the data sheet measurement, it may be assumed that fT does not change and thecomputation of Cπ is straightforward. If the proposed IE is small, model Cπ by the following:

C = X0 + X1 $ IE

X0 is the zero-bias limiting value of the transition capacitance, and X1 is readily calculated fromthe given GBW data together with the operating point used to measure it. This equation is thenused to estimate Cπ at the proposed operating point.

As an example, capacitances are estimated from the data sheet for a NationalSemiconductor PN2222A. A graph labeled "Emitter Transition and Output Capacitance vs.Reverse Bias Voltages" directly states that Cμ is typically 4.5 pF at VCB = 4.3 V. From the samegraph, X0 = 21 pF. Under the small-signal characteristics, it is stated that fT is at least 300 MHzat IC = 20 mA. From this data, X1 = 20 pF/mA. Therefore, Cπ is expected to be 121 pF at 5 mA.


25

An alternative calculation, which simply assumes that fT is the same at 5 mA as at 20 mA,produces Cπ = 102 pF. Either is justifiable given the precision of the available data.

Appendix B - SPICE Simulation of the CE Amplifier

The CE amplifier of Fig. 1 can be easily entered into SPICE and simulated using a2N2222A transistor model. The problem that will immediately arise is that the dc operatingpoint in the simulation will not be the same as that in the lab. The gain and bandwidth results arestrongly operating-point dependent, and therefore will not match the lab results at all. The newerversions of PSpice allow the direct display of the calculated operating point on the schematic: Enable this option and verify that the correct operating point has been achieved before looking atthe frequency response data in probe.

With the direct display of the bias point solution, it is not difficult to iteratively adjustVBB to obtain IC = 5 mA, and then adjust VCC to obtain VCE = 5 V. This process is speeded if allother analyses except for bias point are disabled during this iterative procedure.


26

Experiment 8 Differential Amplifiers

Introduction

The purpose of this experiment is to investigate several key features of the balanceddifferential pair and the wide band (asymmetrical) differential pair.

Equipment Needed

v Scope probe having known inputcapacitance

v two PN2222A npn transistorsv Normal laboratory equipment

Pre-Lab

Assuming that the transistors will have a dc current gain (β or hFE) equal to 100, predictthe Q-points of Figs. 1 and 2. Estimate the differential gain (Ad) and the common-mode gain(Acm) for Fig. 1. In each case, the output is taken at Q2's collector.

Procedure

1. Connect the circuit of Fig. 1 and verify that a reasonable Q-point is obtained. Rememberthat the amplifier is not properly biased unless a dc current path is provided from eachtransistor base to the ground. Substitute transistors until the collector currents of Q1 andQ2 match to within 10 μA of each other. Use the curve tracer to measure the ac currentgain (βO or hfe) in the vicinity of the Q-point for each transistor.

2. Use the signal connections shown in solid lines in Fig. 1 to measure the differential-modegain ( ) of the symmetric differential pair. Note that the output is takenAd = Vo

Vssingle-endedly (from one collector only). This is a midband, small-signal measurement;use 400 Hz and a signal level low enough that there is no appreciable distortion in theoutput sine wave. Use an attenuator as needed to reduce the output of the functiongenerator (FG). (The expected value is about 85.)

3. Measure the high-frequency cutoff fH of the symmetrical differential amplifier of Fig. 1.Note that the input capacitance of the scope probe1 is a part of the high-frequency modelof the circuit. (The expected value is about 27 kHz.)

4. Use the signal connections shown in broken lines in Fig. 1 to measure the common-modegain ( ) of the symmetric differential pair. Use 400 Hz and a low signal levelAcm = Vo

Vcmso that there is no appreciable distortion in the input or output waveforms. (The expectedvalue is about -0.3.)

27

1 For the HP 10071A probe, the input capacitance is 16 pF.

5. Connect the asymmetric differential pair of Fig. 2 and verify that a reasonable Q-point isobtained. (VCB for Q2 should be between 10 and 18 V.)

6. Measure the gain ( ) and the high-frequency cutoff of the asymmetricAd = VoVs

differential pair of Fig. 2. Note that the input capacitance of the scope probe is also animportant part of the high-frequency model of this circuit. (The expected values areabout 85 and 80 kHz, respectively.)

Report

1. From the transistor data sheet, estimate the values of collector-base and emitter-basecapacitance at the Q-point. Hint: at the current level used here, Cπ will be dominated byits transition component.

2. Calculate the theoretical values of Ad , Acm and fH for Figs. 1 and 2, and compare with theexperimental results. (For Fig. 1, use Miller's Theorem and model the symmetricaldifferential amplifier as equivalent to a common-emitter stage.)

3. Use SPICE (with a 2N2222A model) to simulate this circuit, and compare these resultswith the experimental and calculated results.

4. Compare the gains and cutoff frequencies of Figs. 1 and 2. Compute a gain-bandwidthproduct for each.

Differential Amplifiers

28


29

Fig. 1 Symmetrical differential pair. The load capacitance is the scope probe capacitance.

Fig. 2 Asymmetrical differential pair. The load capacitance is the scope probe capacitance.

Fig. 3 PN2222Apackage and pin-out.


30

Experiment 9 Complementary-Symmetry Push-Pull Amplifier

Introduction

The purpose of this experiment is to observe the operation of a class-Bcomplementary-symmetry amplifier and the use of negative feedback to improve its behavior.

Equipment Needed

v Load resistor (about 12 Ω, 5 W)v Complementary-symmetryoutput stage circuit board

v Normal laboratory equipment

Procedure

Connect the circuit of Fig. 1 using a complementary-symmetry output stage circuit board.Fig. 3 gives a top view (component side) of this circuit board to identify the correct connectionpoints. Note that both Figs. 1 and 2 show only a simplified equivalent of the circuit boardschematic: The details of the circuit board are shown in Fig. 3. In making connections, bringall ground leads separately back to the "COM" binding post on the circuit board (including thefunction generator and scope ground leads). This is known as a "star" grounding arrangement.

1. Use the function generator (FG) to apply a 10-V peak 100-Hz triangle wave as shown inFig. 1. Connect the two scope channels as indicated. Display and record the input(Chan. 1) and output (Chan. 2) waveforms. Note carefully the defect in the outputwaveform around its zero crossings. This is known as "crossover" distortion.

2. Display and record an X-Y plot of output vs. input on the scope. (Look on the horizontal"Main/Delayed" menu.) Be sure that both channels are set for zero offset and 2 V/divbefore switching to the X-Y mode. This is the transfer function of the basiccomplementary-symmetry output stage.

3. Obtain a type '741 op-amp and connect Fig. 2, placing the op-amp on a proto-board. It isbest to run separate jumper wires from each op-amp terminal to the correspondingterminals on the output stage circuit board. Make all power supply connections (+15 V,-15 V and COM) to the circuit board, not to the proto-board. Set the FG for 10 V peak at100 Hz as before.

4. Display and record the input from the FG (Chan. 1) and the output (Chan. 2) waveforms.Note the suppression of the crossover distortion by the negative feedback.

5. Display and record an X-Y plot of output vs. input as before. Use identical verticalsettings of 2 V/div and zero offset on both channels.

31

6. Investigate how the negative feedback functions to suppress the crossover distortion.Move the scope channel 1 to the two transistor bases (B1 and B2) on the circuit board.Switch the scope back to voltage vs. time. Display and record the input and output of thecomplementary-symmetry stage itself. Note the inverse crossover distortion at the inputto the complementary-symmetry stage.

7. Maintain these two waveforms on the scope while increasing the FG frequency to10 kHz. Note the decreasing ability of the feedback to cancel the crossover distortion athigh frequency. Record these waveforms.

Report

1. Explain the cause of the crossover distortion observed in steps 1 and 2. (Most electronicstexts have a good discussion of this problem in a chapter on "power amplifiers" or"output stages.")

2. Analyze the circuit in Fig. 2 based upon the assumption of an ideal op-amp. (Assumethat the voltages on pins 2 and 3 of the '741 must be exactly equal because of its infinitegain.) How does this suppress the distortion? Use the waveforms gathered in steps 4 and5 to support your discussion.

3. Why is the distortion reduction in step 7 (at 10 kHz) not so good as it was at 100 Hz?Explain this in terms of a specific imperfection in all practical op-amps, as opposed to anideal op-amp.

Complementary-Symmetry Push-Pull Amplifier

32


33

Fig. 1 Simplified diagram of the complementary-symmetry output stage.

Fig. 2 Complementary-symmetry amplifier with negative feedback.

Fig. 3 Pictorial top view and detailed schematic of the complementary-symmetry output stage.


34

Fig. 4 '741 pinout, top view.

Experiment 10 Negative Feedback

Introduction

The purpose of this experiment is to investigate the effects of shunt-shunt negativefeedback on the gain, input resistance and output resistance of a transresistance amplifier.

Equipment Needed


Procedure

Connect the circuit of Fig. 1. Verify that the Q-point is approximately 1 mA. All acmeasurements will be at midband (5 kHz) and small signal (no appreciable distortion).

1. Measure the closed-loop voltage gain . Av = VoVs

2. Measure the input resistance indicated on Fig. 1, . This may be done by measuringRif∏

the ac voltages VS and VSJ using the scope. Verify that these two voltages are in-phase.

Compute the current in RS, and then find . (The expected value is aboutRif∏ = VSJ

IRS60 Ω.)

3. Measure the output resistance indicated on Fig. 1, . Fig. 2 shows how to do this: Rof∏

Remove the function generator (FG), but keep its source resistance RS in place asindicated. Connect the FG at the output terminal with a 100-K series resistor (R5). Setthe FG for a 10-V peak 5-kHz sine wave output and measure voltages V1 and V2.

Compute the current in R5, and then find . (The expected value is aboutRof∏ = V1

IR5370 Ω.)

4. Connect the circuit of Fig. 3. This is the amplifier with the feedback removed, but theloading effects of the feedback resistor Rf retained. Verify that the Q-point is the same aspreviously, approximately 1 mA.

5. Measure the voltage gain , input resistance , and output resistance usingAv = VoVs Ri

∏ Ro∏

the same techniques as previously. (The expected values are -150, 3.2 KΩ and, 5 KΩrespectively.)

35

Report

1. Use feedback theory to calculate the gain , input resistance , and outputAv = VoVs

Rif∏

resistance for Fig. 1. Be sure to note that the gain factor is not the one directlyRof∏

Av

stabilized by the feedback or given by the equation . A1+A

2. Use SPICE simulation to predict the gain and input/output resistances of Fig. 1.

3. Compare the results predicted by SPICE and by calculation to your experimental data.

Background - Measuring Input/Output Resistances in a Feedback System

There are two general cautions to observe in analyzing a feedback system: The quantitywhich you are computing may not be the same as the one actually stabilized by the feedback; andeverything (all gains and resistances) pertaining to the feedback amplifier is affected by the loopgain. The first caution applies to this lab in that the voltage gain of Fig. 1 is not directlystabilized by the feedback. Fig. 1 is a transresistance amplifier: Its current-to-voltageconversion factor is stabilized by the feedback. The best way to calculate the voltage gain ofFig. 1 is to compute the transresistance first, and then convert it into the voltage gain.

The second caution affects the resistance measuring procedure used in this lab. The"ohmmeter" applied to the circuit must not alter the loop gain of the amplifier. (This cautionmust also be remembered in devising a SPICE-based procedure for determining the input andoutput resistances as well.) When measuring the input resistance , the source resistance RSRif

∏

provides a convenient way of measuring the input current; however, changing the value of RS

from that given will alter the measured value of because it would alter the loop gain. TheRif∏

function generator (FG) is connected in series with a 1-KΩ resistor which is considered thesource resistance. It is reasonably accurate to neglect the internal 50 Ω resistance of the FG.

Similarly, the measuring apparatus in Fig. 2 (the FG with R5) alters the loop gain, andthus produces an erroneous value of . In this case, R5 is chosen to be much greater than theRof

∏

open loop value of the output resistance so that it will only change the open loop gain by a smallamount and produce a reasonably accurate measurement.

Negative Feedback

36

Negative Feedback

37

Fig. 1 Amplifier with shunt-shunt feedback.

Fig. 2 Measuring the output resistance.

Fig. 3 Amplifier with feedback removed, but loading effects retained.

Negative Feedback

38

Experiment 11 Voltage Regulators

Introduction

The purpose of this experiment is to investigate the performance characteristics of twosimple voltage regulators.

Equipment Needed

v Resistor decade box

v 1N754 6.8-V Zener diode(alternates: 1N4736 or 1N5235)

v MJE 371 pnp power transistor v Normal laboratory equipment

Pre-Lab

Complete the design of the Zener diode shunt regulator in Fig. 1 (determine the largest5% standard value which can be used for R1). It must operate satisfactorily over a load currentrange of 0 to 10 mA using a supply voltage of 12 V. The output voltage is expected to have anominal value of 6.8 V.

Procedure

The 12-V supply in the following procedure is a laboratory supply capable of 200 mA ofoutput current. Be sure to set its current limiter for at least this amount.

1. Set up the circuit of Fig. 1 using the standard value that you calculated for R1 in thepre-lab. Use a resistor decade box as the "load resistor" RLOAD. Insert a milliammeter asshown to monitor the load current. Measure the load voltage at light-load (ILOAD = 1 mA),and at full-load (ILOAD = 10 mA).

2. Measure the output voltage/current pairs with various values of load resistance. Useoutput currents ranging from zero to well beyond the point where the regulator "drops outof regulation." Collect enough data to sketch a map of the regulator performance on theVLOAD vs. ILOAD plane (put VLOAD on the vertical axis, and ILOAD on the horizontal). Theexpected result is that the regulator will maintain the output voltage almost-constant withregard to load current up to the "dropout current:" the output voltage will then fallrapidly with further increase in load current.

3. Set up the circuit of Fig. 2 and adjust it for an output voltage of 5.0 V at no-load.Measure the output voltage and current with load resistors of 500 Ω and 50 Ω.

4. Operate the voltage regulator for several minutes with a 50-Ω load and feel Q2. (Is itgetting warm?)

39

Report

1. Include and discuss your design calculations for the Zener diode voltage regulator ofFig. 1.

2. Describe the range of output current over which Fig. 1 operates satisfactorily. Why doesit "drop out of regulation?"

3. Find the experimentally-measured dynamic output resistance of each regulator in thefollowing manner:

ROUT = VLOADILOAD

=VLOAD,1 − VLOAD,2ILOAD,1 − ILOAD,2

4. Use PSpice to estimate the output resistance of Figs. 1 and 2. Use ac simulation andmeasure the resistance at midband (about 1 kHz). Include a 680-Ω load resistor in Fig. 1,and a 50−Ω load resistor in Fig. 2. Model Z1 using a 1N750-series Zener diode, but editthe breakdown voltage parameter to: (BV=6.8V). Model Q2 with a transistor having itsSPICE parameters set to: (IS=1E-14 BF=100 VAF=50V). Compare the SPICE resultswith the experimentally-measured output resistances.

5. Use PSpice to determine the range of output current over which Fig. 2 operatessatisfactorily. Put a dc current source in place of the load resistor, and use a dc sweep toplot the load voltage vs. the load current. (Truncate any data beyond the point at whichthe load voltage is reduced to zero.) What is the maximum useful load current accordingto this simulation? Calculate the power dissipation in Q2, and its junction temperaturefor this amount of load current.

Background - Zener Shunt Regulator

The Zener diode shunt regulator is treated in detail by most electronics texts. For thepurposes of the pre lab design, it is sufficient to treat the diode as an ideal 6.8-V Zener. Thedesign problem is to pick R1 such that some amount of reverse current will flow in the Zenerdiode under all normal load conditions. Here, worst case is at maximum load current. Acalculation at maximum load current produces the maximum feasible value for R1, which thenmust be rounded downward to the nearest available standard value. The student version ofPSpice includes a 1N750-series Zener diode model - if it is not the one you need, modify thelibrary model to include "BV = 6.8." (This sets the reverse breakdown voltage of the diode.)

Background - Series-Pass Voltage Regulator

The voltage regulator in Fig. 2 is an application of series-shunt negative feedback.Resistors R5 and R4, together with Z1, form an adjustable "input voltage" to a voltage amplifierprogrammed for a gain of +1. The load is the external circuitry to which the voltage regulator is

Voltage Regulators

40

Voltage Regulators

41

Fig. 1 Zener diode shunt regulator. Calculate the maximum standard value which can be used for R1.

Fig. 2 Adjustable voltage regulator.

Fig. 3 Transistor package outlines.

MJE 371

feeding power. (Nowadays, almost all electronic circuitry is fed from a voltage-regulated powersupply.) Note that the +12-V supply is the energy source which runs the whole system; it is notusually a regulated source. One of the key specifications of a voltage regulator is its dynamicoutput resistance, which indicates its ability to maintain a constant output voltage even as theload current varies. This can be predicted theoretically by the same methods used to calculatethe output resistance of any shunt-sensing feedback amplifier.

Transistor Q2 is called a "series-pass transistor." This is because the main load current iscarried by Q2; the collector-emitter voltage drop on Q2 is equal to the difference between thesupply voltage (+12 V) and the load voltage. In general, Q2 dissipates a lot of heat, and thusgets hot. The junction temperature of Q2 may be estimated by using a simplified heat-flowmodel which makes the temperature drop between two locations directly proportional to theamount of heat flowing from one to the other. (Note the analogy to Ohm's law.) For theMJE 371, which is in a TO 225 package, mounted in free air, the "thermal resistance" betweenthe junction and the ambient air is approximately 83 C/W. The maximum safe junctiontemperature for the long-term survival of this semiconductor is rated by the manufacturer at150 C. The heat dissipated in the junction is calculated by (watts).PDISS = VCE $ ICTherefore, assuming a laboratory ambient temperature of 25 C, the junction temperature isestimated by: . The junction temperature of Q2 defines theTJ = PDISS $ (83 C/W) + 25 Cmaximum load current that this regulator can safely deliver.

Voltage Regulators

42

Experiment 12 Wien Bridge Oscillator

Introduction

The Wien bridge oscillator will be used to demonstrate the effects of positive feedback,and the Barkhausen criterion for oscillation. Negative feedback is also used to stabilize thetransfer characteristics of the amplifier used by this oscillator.

Equipment Needed

PN2907A pnp transistor(alternate: 2N4403)

PN2222A npn transistor(alternate: 2N4401)

Normal laboratory equipment

Pre Lab

Read the appropriate section(s) of your electronics text dealing with the "Barkhausencriterion" or "quasi-linear sinusoidal" oscillators.

Procedure

1. Construct the amplifier of Fig. 1. Measure its voltage gain at 1 kHz. VerifyVoutVin

that the amplifier is non-inverting, and that trim pot R4 adjusts its voltage gain fromsomething less than +3 to something more than +3. Use the 100-K series resistortogether with the function generator (FG) to measure the amplifier input resistanceRin . (The expected value is about 180 KΩ.)

2. Add the frequency-selective feedback network to the amplifier as shown in Fig. 2.Use the capacitor value given for C on Fig. 2, unless otherwise instructed. Initially,wire the circuit as indicated by the "TEST" position of the switch. Set the FG for asine wave at the frequency and monitor Vout and the FG signal using thefo = 1

2 RCtwo-channel scope. Monitor the phase shift. (Hint: A phase measurement isavailable on the DSO "Measure Time" menu.) Vary the FG frequency about untilfoyou find the frequency at which the phase is zero.

3. Remove the FG, and wire Fig. 2 as indicated by the "OSCILLATE" position of theswitch. Adjust trim pot R4 until the circuit breaks into oscillation. Adjust R4 toproduce the minimum amplifier gain which maintains oscillation. Study the effectsof a slight decrease or increase of the amplifier gain about the borderline valuewhich just barely sustains oscillation. Measure the frequency of oscillation.

4. Do not change the setting on R4. Remove the frequency-selective feedback network,and measure the amplifier gain as done previously in Fig. 1.

VoutVin

43

Report

1. Review the Barkhausen criterion for oscillation.

2. Derive the transfer function of Fig. 3, the frequency-selective feedbackVo(s)Vi(s)

network. Calculate the magnitude and the phase of this function at the frequency . fo = 1

2 RC

3. Calculate the amplifier gain required for oscillation at . Compare this with yourfolaboratory observations.

4. Run a series of several PSpice simulations of the complete oscillator circuit. Use a transient simulation, and parametrically step the total resistance RE = R3+R4 from1.2 KΩ to 1.6 KΩ in 100-Ω steps. Set the simulation run time at 50 ms with amaximum step size of 0.1 ms. Do not omit the initial transient solution. Observe thestart-up process for the oscillator, and comment on it in your report.

Wien Bridge Oscillator

44


45

Fig.1 Voltage amplifier with series-shunt feedback.

Fig. 2 Completed oscillator circuit using amplifier from above.

Fig. 3 Frequency-selective feedback network.


46

Experiment 13 Analog/Digital Conversion

Introduction

Most digital signal processing systems are interfaced to the analog world throughanalog-to-digital converters (A/D) and digital-to-analog converters (D/A). The purpose of thisexperiment is to observe how the conversion process modifies the signal. A circuit board havingseparate sample-and-hold (S/H), A/D and D/A sections is provided for this experiment. It allowseasy access to the signals at each stage of these conversion processes.

Equipment Needed

Analog/digital conversioncircuit board

Function generatorDigital Scope with eventaveraging capability

Pre Lab

Read the appropriate section(s) of your electronics text dealing with A/D and D/Aconversion, as well as S/H circuits.

Procedure

1. Connect the analog/digital conversion circuit board as shown in Fig. 1. Be sure toobserve correct polarity in connecting the +/- 15-V power supplies. The functiongenerator and oscilloscope ground leads should be connected to "analog ground."The power supply common lead is connected to "digital ground." Set the FG for a dcoutput1 voltage of 0 V. Connect the scope channel 1 to the analog input (to the A/Dconverter), and channel 2 to the analog output (from the D/A converter).

2. Vary the dc voltage at the analog input slowly from 0 V to 5 V. The eight LEDsindicate the digital value of the converted analog input voltage. The 8-bit byteshould vary from 00h to FFh . Determine what happens when the analog inputvoltage goes below zero, or above 5 V. Using an increment of 1 mV in the analogvoltage, carefully determine the voltage change (to the nearest 1 mV) required toproduce a 1-bit change in the digital output. This is the "quantization step size."

3. Use a dc voltmeter connected between "analog ground" and "VREF" to measure theinternal reference voltage of the A/D and D/A converters. The result should be 5 V,plus or minus 5%. Divide VREF by (28 -1) and compare with the quantization stepsize measured in step 2. These two results should be equal.

47

1 To obtain dc output from the HP 33120A, press and hold the buttons for two waveforms, suchas sine and triangle, simultaneously for several seconds.

4. Set the FG for a 100-mVpp 50-Hz triangle wave with a 100-mV dc offset2. Connectchannel 1 of the scope to show this analog input waveform, and connect channel 2 toshow the output voltage of the S/H stage, labeled "S/H OUT." Trigger from channel1. You will need to use event averaging to obtain a low-noise display at 50 mV/div.Record this display which documents the relationship between the low-frequencyinput signal and a sampled version of it.

5. Keep the same setup as the previous step, except move channel 2 to the "analogoutput." This output shows the result of digitizing the sampled signal, and thenconverting it back to analog form. Record this display which documents therelationship between the low-frequency input signal and a sampled and quantizedversion of it. Use this display to measure the quantization step size.

6. Measure the frequency of the sampling-and-conversion clock signal labeled"CONV. CLK." This is the sampling frequency.

7. Set the FG for a 5-Vpp 500-Hz sine wave with a 2.5-V dc offset. View the inputsignal on channel 1, and the sampled signal (S/H OUT) on channel 2. Be sure totrigger the scope from channel 1. View the results both with and without eventaveraging (8 averages is fine). The normally-acquired waveforms should clearlyshow the effects of the sampling process on the signal. Record two sets offwaveforms, one event-averaged and the other without event averaging.

8. With the event averaging turned off, slowly change the frequency of the sine waveby +/- 10 Hz using 1-Hz increments. Your scope display should be showing signalcomponents at 500 Hz, and signal components at the sampling frequency (≅ 7 kHz).These two frequencies could be commensurate (having an integer-ratio relationship),or incommensurate. As you change the signal frequency slightly, observe whathappens when the two frequencies involved become commensurate. Record yourwritten comments.

9. Set the scope time base for 1 ms/div, and change the triggering source to channel 2with HF reject on. Channel 2 is still connected to the analog output. Increase thefrequency of the sine wave input from 0.5 kHz to 22 kHz, going in 0.1 kHz steps.Observe what happens as you pass through the frequencies fS, 2 fS, and 3 fS. Recordyour written comments.

Report

1. Discuss the meaning of "quantization step size." Give its numerical value for thisA/D converter as measured in steps 2 and 3. Label your waveforms recorded in step

Analog/Digital Conversion

48

2 Remember that the actual output voltage amplitude will not agree with the programmed valueunless the output termination is set to "High Z."

5 to show where the quantization step size can be measured from these results.

2.3.


49

Fig. 1 Top view of analog/digital conversion experiment circuit board. Observe polarity whenconnecting the +/- 15-V power supplies.


50

Data Sheets

The following data sheets are included with this lab manual:

Operational Amplifier: GBW=1 MHz, SR=0.5 V/μs, Voff<7.5 mVLM741

pnp BJT: power, 40 V, 4 A, 4 W, TO-225AA case, complement to MJE521

MJE371

npn BJT: small signal, 40 V, 1 A, 625 mW, TO-92 case, complement to PN2907A

PN2222A

Brief Description(see data sheet)

PartNumber

Additional data sheets are found in the Electronics Lab I lab manual.

51

52

NPN General Purpose AmplifierThis device is for use as a medium power amplifier andswitch requiring collector currents up to 500 mA. Sourcedfrom Process 19.

Absolute Maximum Ratings* TA = 25°C unless otherwise noted

*These ratings are limiting values above which the serviceability of any semiconductor device may be impaired.

NOTES:1) These ratings are based on a maximum junction temperature of 150 degrees C.2) These are steady state limits. The factory should be consulted on applications involving pulsed or low duty cycle operations.

Symbol Parameter Value UnitsVCEO Collector-Emitter Voltage 40 V

VCBO Collector-Base Voltage 75 V

VEBO Emitter-Base Voltage 6.0 V

IC Collector Current - Continuous 1.0 A

TJ, Tstg Operating and Storage Junction Temperature Range -55 to +150 °C

1998 Fairchild Semiconductor Corporation

Thermal Characteristics TA = 25°C unless otherwise noted

Symbol Characteristic Max UnitsPN2222A *MMBT2222A **PZT2222A

PD Total Device DissipationDerate above 25°C

6255.0

3502.8

1,0008.0

mWmW/°C

RθJC Thermal Resistance, Junction to Case 83.3 °C/W

RθJA Thermal Resistance, Junction to Ambient 200 357 125 °C/W

*Device mounted on FR-4 PCB 1.6" X 1.6" X 0.06."

**Device mounted on FR-4 PCB 36 mm X 18 mm X 1.5 mm; mounting pad for the collector lead min. 6 cm2.

PN2222A

CB E

TO-92

MMBT2222A

C

B

E

SOT-23Mark: 1P

PZT2222A

BC

C

SOT-223

E

PN

2222A / M

MB

T2222A

/ PZ

T2222A

Electrical Characteristics TA = 25°C unless otherwise noted

Symbol Parameter Test Conditions Min Max Units

OFF CHARACTERISTICS

ON CHARACTERISTICS

SMALL SIGNAL CHARACTERISTICSfT Current Gain - Bandwidth Product IC= 20 mA, VCE= 20 V, f= 100 MHz 300 MHz

Cobo Output Capacitance VCB = 10 V, IE = 0, f = 100 kHz 8.0 pF

Cibo Input Capacitance VEB = 0.5 V, IC = 0, f = 100 kHz 25 pF

rb’CC Collector Base Time Constant IC= 20 mA, VCB= 20 V, f= 31.8 MHz 150 pS

NF Noise Figure IC = 100 µA, VCE = 10 V, RS = 1.0 kΩ, f = 1.0 kHz

4.0 dB

Re(hie) Real Part of Common-EmitterHigh Frequency Input Impedance

IC = 20 mA, VCE = 20 V,f = 300 MHz

60 Ω

SWITCHING CHARACTERISTICS

*Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%

Spice Model

V(BR)CEO Collector-Emitter Breakdown Voltage* IC = 10 mA, IB = 0 40 V

V(BR)CBO Collector-Base Breakdown Voltage IC = 10 µA, IE = 0 75 V

V(BR)EBO Emitter-Base Breakdown Voltage IE = 10 µA, IC = 0 6.0 V

ICEX Collector Cutoff Current VCE = 60 V, VEB(OFF) = 3.0 V 10 nA

ICBO Collector Cutoff Current VCB = 60 V, IE = 0VCB = 60 V, IE = 0, TA = 150°C

0.0110

µAµA

IEBO Emitter Cutoff Current VEB = 3.0 V, IC = 0 10 nA

IBL Base Cutoff Current VCE = 60 V, VEB(OFF) = 3.0 V 20 nA

hFE DC Current Gain IC = 0.1 mA, VCE = 10 VIC = 1.0 mA, VCE = 10 VIC = 10 mA, VCE = 10 VIC = 10 mA, VCE = 10 V, TA = -55°CIC = 150 mA, VCE = 10 V*IC = 150 mA, VCE = 1.0 V*IC = 500 mA, VCE = 10 V*

35507535

1005040

300

VCE(sat) Collector-Emitter SaturationVoltage*

IC = 150 mA, IB = 15 mA IC = 500 mA, IB = 50 mA

0.31.0

VV

VBE(sat) Base-Emitter Saturation Voltage* IC = 150 mA, IB = 15 mAIC = 500 mA, IB = 50 mA

0.6 1.22.0

VV

td Delay Time VCC = 30 V, VBE(OFF) = 0.5 V, 10 ns

tr Rise Time IC = 150 mA, IB1 = 15 mA 25 ns

ts Storage Time VCC = 30 V, IC = 150 mA, 225 ns

tf Fall Time IB1 = IB2 = 15 mA 60 ns

NPN (Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=255.9 Ne=1.307 Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0Ikr=0 Rc=1 Cjc=7.306p Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p Itf=.6Vtf=1.7 Xtf=3 Rb=10)

NPN General Purpose Amplifier(continued)

PN

2222A / M

MB

T2222A

/ PZ

T2222A

Typical Characteristics

Typical Pulsed Current Gainvs Collector Current

0.1 0.3 1 3 10 30 100 3000

100

200

300

400

500

I - COLLECTOR CURRENT (mA)

h

- T

YP

ICA

L P

ULS

ED

CU

RR

EN

T G

AIN

C

FE

125 °C

25 °C

- 40 °C

V = 5VCE

Collector-Emitter SaturationVoltage vs Collector Current

1 10 100 500

0.1

0.2

0.3

0.4

I - COLLECTOR CURRENT (mA)V

- CO

LLE

CT

OR

-EM

ITT

ER

VO

LTA

GE

(V

)C

ES

AT

25 °C

C

β = 10

125 °C

- 40 °C

Base-Emitter SaturationVoltage vs Collector Current

1 10 100 500

0.4

0.6

0.8

1


V

- B

AS

E-E

MIT

TE

R V

OLT

AG

E (

V)

BE

SAT

C

β = 10

25 °C

125 °C

- 40 °C

Base-Emitter ON Voltage vsCollector Current

0.1 1 10 250.2

0.4

0.6

0.8

1

I - COLLECTOR CURRENT (mA)V

- B

AS

E-E

MIT

TE

R O

N V

OLT

AG

E (

V)

BE

(ON

)

C

V = 5VCE

25 °C

125 °C

- 40 °C

Collector-Cutoff Currentvs Ambient Temperature

25 50 75 100 125 150

0.1

1

10

100

500

T - AMBIENT TEMPERATURE ( C)

I

- C

OL

LE

CT

OR

CU

RR

EN

T (

nA

)

A

V = 40VCB

CB

O

°

Emitter Transition and OutputCapacitance vs Reverse Bias Voltage

0.1 1 10 100

4

8

12

16

20

REVERSE BIAS VOLTAGE (V)

CA

PAC

ITA

NC

E (

pF)

f = 1 MHz

C ob

C te


PN

2222A / M

MB

T2222A

/ PZ

T2222A

Typical Characteristics (continued)

Power Dissipation vsAmbient Temperature

0 25 50 75 100 125 1500

0.25

0.5

0.75

1

TEMPERATURE ( C)

P

- P

OW

ER

DIS

SIP

AT

ION

(W

)D

o

SOT-223TO-92

SOT-23

Turn On and Turn Off Timesvs Collector Current

10 100 10000

80

160

240

320

400


TIM

E (

nS

)

I = I =

t on

t off

B1

C

B2I c

10

V = 25 Vcc

Switching Timesvs Collector Current

10 100 10000

80

160

240

320

400


TIM

E (

nS

)

I = I =

t r

t s

B1

C

B2I c

10

V = 25 Vcc

t f

t d

PN

2222A / M

MB

T2222A

/ PZ

T2222A


Typical Common Emitter Characteristics (f = 1.0kHz)

Common Emitter Characteristics

0 10 20 30 40 50 600

2

4

6

8


CH

AR

. RE

LATI

VE

TO

VA

LU

ES

AT

I =

10m

A

V = 10 VCE

C

C T = 25 CA o

hoe

h re

h fe

h ie


0 20 40 60 80 1000

0.4

0.8

1.2

1.6

2

2.4

T - AMBIENT TEMPERATURE ( C)

CH

AR

. RE

LA

TIV

E T

O V

AL

UE

S A

T T

= 2

5 C

V = 10 VCE

A

A I = 10 mAC

hoe

hre

hfe

hie

o

o


0 5 10 15 20 25 30 350.75

0.8

0.85

0.9

0.95

1

1.05

1.1

1.15

1.2

1.25

1.3

V - COLLECTOR VOLTAGE (V)

CH

AR

. RE

LA

TIV

E T

O V

AL

UE

S A

T V

=

10V

CE

CE

T = 25 CA o

hoe

hre

h fe

h ie

I = 10 mAC


PN

2222A / M

MB

T2222A

/ PZ

T2222A

Test Circuits

30 V

1.0 KΩΩΩΩΩ16 V

0

≤≤≤≤≤ 200ns

≤≤≤≤≤ 200ns

500 ΩΩΩΩΩ

200 ΩΩΩΩΩ

50 ΩΩΩΩΩ

37 ΩΩΩΩΩ

- 1.5 V

1.0 KΩΩΩΩΩ

6.0 V

0

30 V

FIGURE 2: Saturated Turn-Off Switching Time

FIGURE 1: Saturated Turn-On Switching Time

1k

PN

2222A / M

MB

T2222A

/ PZ

T2222A


NOTE: BVEBO = 5.0 V

TO-92 Tape and Reel Data

March 2001, Rev. B1©2001 Fairchild Semiconductor Corporation

TO-92 PackagingConfiguration: Figure 1.0

AMMO PACK OPTIONSee Fig 3.0 for 2 Ammo

Pack Options

2000 units perEO70 box for

std option

FSCINT Label

530mm x 130mm x

83mmIntermediate box

10,000 units maximumper

intermediate boxfor std option

FSCINT Label

114mm x 102mm x 51mmImmediate Box

Anti-static Bubble Sheets

(TO-92) BULK PACKING INFORMATION

EOLCODE DESCRIPTION LEADCLIP

DIMENSION QUANTITY

J18Z TO-18 OPTION STD NO LEAD CLIP 2.0 K / BOX

J05Z TO-5 OPTION STD NO LEAD CLIP 1.5 K / BOX

NO EOLCODE

TO-92 STANDARDSTRAIGHT FOR: PKG 92, NO LEADCLIP 2.0 K / BOX

BULK OPTIONSee Bulk PackingInformation table

375mm x 267mm x 375mmIntermediate Box

FSCINTLabel

CustomizedLabel

333mm x 231mm x 183mmIntermediate Box

FSCINTLabel

CustomizedLabel

TO-92 TNR/AMMO PACKING INFROMATION

Packing Style Quantity EOL code

Reel A 2,000 D26Z

E 2,000 D27Z

Ammo M 2,000 D74Z

P 2,000 D75Z

Unit weight = 0.22 gmReel weight with components = 1.04 kgAmmo weight with components = 1.02 kgMax quantity per intermediate box = 10,000 units

F63TNRLabel

5 Ammo boxes per Intermediate Box

CustomizedLabel

327mm x 158mm x 135mmImmediate Box

LOT: CBVK741B019

NSID: PN2222N

D/C1: D9842 SPEC REV: B2

SPEC:

QTY: 10000

QA REV:

FAIRCHILD SEMICONDUCTOR CORPORATION HTB:B

(FSCINT)

F63TNRLabel

CustomizedLabel

5 Reels perIntermediate Box

TAPE and REEL OPTIONSee Fig 2.0 for various

Reeling Styles

LOT: CBVK741B019

FSID: PN222N

D/C1: D9842 QTY1: SPEC REV:

SPEC:

QTY: 2000

D/C2: QTY2: CPN:N/F: F (F63TNR)3

F63TNR Label sample

FSCINT Label sample

C

5 EO70 boxes per intermediate Box

ustomizedLabel

94 (NON PROELECTRON

SERIES), 96

L34Z TO-92 STANDARDSTRAIGHT FOR: PKG 94 NO LEADCLIP 2.0 K / BOX

(PROELECTRON SERIES

BCXXX, BFXXX, BSRXXX),97, 98

TO-92 Tape and Reel Data, continued

September 1999, Rev. B

TO-92 Reeling StyleConfiguration: Figure 2.0

Style “A”, D26Z, D70Z (s/h)

Machine Option “A” (H)

Style “E”, D27Z, D71Z (s/h)

Machine Option “E” (J)

FIRST WIRE OFF IS EMITTERADHESIVE TAPE IS ON THE TOP SIDEFLAT OF TRANSISTOR IS ON BOTTOM

ORDER STYLED75Z (P)

FIRST WIRE OFF IS COLLECTORADHESIVE TAPE IS ON THE TOP SIDEFLAT OF TRANSISTOR IS ON TOP

ORDER STYLED74Z (M)

TO-92 Radial Ammo PackagingConfiguration: Figure 3.0

FIRST WIRE OFF IS EMITTER (ON PKG. 92)ADHESIVE TAPE IS ON BOTTOM SIDEFLAT OF TRANSISTOR IS ON BOTTOM

FIRST WIRE OFF IS COLLECTOR (ON PKG. 92)ADHESIVE TAPE IS ON BOTTOM SIDEFLAT OF TRANSISTOR IS ON TOP

ITEM DESCRIPTION

Base of Package to Lead Bend

Component Height

Lead Clinch Height

Component Base Height

Component Alignment ( side/side )

Component Alignment ( front/back )

Component Pitch

Feed Hole Pitch

Hole Center to First Lead

Hole Center to Component Center

Lead Spread

Lead Thickness

Cut Lead Length

Taped Lead Length

Taped Lead Thickness

Carrier Tape Thickness

Carrier Tape Width

Hold - down Tape Width

Hold - down Tape position

Feed Hole Position

Sprocket Hole Diameter

Lead Spring Out

SYMBOL

b

Ha

HO

H1

Pd

Hd

P

PO

P1

P2

F1/F2

d

L

L1

t

t1

W

WO

W1

W2

DO

S

DIMENSION

0.098 (max)

0.928 (+/- 0.025)

0.630 (+/- 0.020)

0.748 (+/- 0.020)

0.040 (max)

0.031 (max)

0.500 (+/- 0.020)

0.500 (+/- 0.008)

0.150 (+0.009, -0.010)

0.247 (+/- 0.007)

0.104 (+/- 0 .010)

0.018 (+0.002, -0.003)

0.429 (max)

0.209 (+0.051, -0.052)

0.032 (+/- 0.006)

0.021 (+/- 0.006)

0.708 (+0.020, -0.019)

0.236 (+/- 0.012)

0.035 (max)

0.360 (+/- 0.025)

0.157 (+0.008, -0.007)

0.004 (max)

Note : All dimensions are in inches.

ITEM DESCRIPTION SYSMBOL MINIMUM MAXIMUM

Reel Diameter D1 13.975 14.025

Arbor Hole Diameter (Standard) D2 1.160 1.200

(Small Hole) D2 0.650 0.700

Core Diameter D3 3.100 3.300

Hub Recess Inner Diameter D4 2.700 3.100

Hub Recess Depth W1 0.370 0.570

Flange to Flange Inner Width W2 1.630 1.690

Hub to Hub Center Width W3 2.090

Note: All dimensions are inches

TO-92 Tape and Reel TapingDimension Configuration: Figure 4.0

Ha

H1 HO

PO

P2

P1 F1

DO

P Pd

b

d

L1

LS

WOW2

W

t

t1

Hd

W1

TO-92 ReelConfiguration: Figure 5.0

User Direction of Feed

SEN SITIVE D EVICES

ELECTROSTATIC

D1

D3

Customized Label

W2

W1

W3

F63TNR Label

D4

D2

TO-92 Tape and Reel Data, continued

July 1999, Rev. A

TO-92 (FS PKG Code 92, 94, 96)

TO-92 Package Dimensions

January 2000, Rev. B

1:1Scale 1:1 on letter size paper

Dimensions shown below are in:inches [millimeters]

Part Weight per unit (gram): 0.1977

©2000 Fairchild Semiconductor International

SOT-23 PackagingConfiguration: Figure 1.0

ComponentsLeader Tape500mm minimum or

125 empty pockets

Trailer Tape300mm minimum or

75 empty pockets

SOT-23 Tape Leader and TrailerConfiguration: Figure 2.0

Cover Tape

Carrier Tape

Note/Comments

Packaging Option

SOT-23 Packaging Information

Standard(no flow code) D87Z

Packaging type

Reel Size

TNR

7" Dia

TNR

13"

Qty per Reel/Tube/Bag 3,000 10,000

Box Dimension (mm) 187x107x183 343x343x64

Max qty per Box 24,000 30,000

Weight per unit (gm) 0.0082 0.0082

Weight per Reel (kg) 0.1175 0.4006

Human readableLabel

Human Readable Label

Human Readable Label sample

343mm x 342mm x 64mmIntermediate box for L87Z Option

187mm x 107mm x 183mmIntermediate Box for Standard Option

SOT-23 Unit Orientation

3P 3P 3P 3P

Human ReadableLabel

Customized Label

EmbossedCarrier Tape

Antistatic Cover Tape

Packaging Description:

SOT-23made from a dissipative (carbon fil led) polycarbonateresin. The cover tape is a multilayer film (Heat ActivatedAdhesive in nature) primarily composed of polyester film,adhesive layer, sealant, and anti-static sprayed agent.These reeled parts in standard option are shipped with3,000 units per 7" or 177cm diameter reel. The reels aredark blue in color and is made of polystyrene plastic (anti-static coated). Other option comes in 10,000 units per 13"or 330cm diameter reel. This and some other options aredescribed in the Packaging Information table.

These full reels are individually labeled and placed insidea standard intermediate made of recyclable corrugatedbrown paper with a Fairchil d logo printing. One pizza boxcontains eight reels maximum. And these intermediateboxes are placed inside a labeled shipping box whichcomes in different sizes depending on the number of partsshipped.

parts are shipped in tape. The carrier tape is

SOT-23 Tape and Reel Data

September 1999, Rev. C©2000 Fairchild Semiconductor International

Dimensions are in millimeter

Pkg type A0 B0 W D0 D1 E1 E2 F P1 P0 K0 T Wc Tc

SOT-23(8mm)

3.15+/-0.10

2.77+/-0.10

8.0+/-0.3

1.55+/-0.05

1.125+/-0.125

1.75+/-0.10

6.25min

3.50+/-0.05

4.0+/-0.1

4.0+/-0.1

1.30+/-0.10

0.228+/-0.013

5.2+/-0.3

0.06+/-0.02

Dimensions are in inches and millimeters

Tape SizeReel

Option Dim A Dim B Dim C Dim D Dim N Dim W1 Dim W2 Dim W3 (LSL-USL)

8mm 7" Dia 7.00177.8

0.0591.5

512 +0.020/-0.00813 +0.5/-0.2

0.79520.2

2.16555

0.331 +0.059/-0.0008.4 +1.5/0

0.56714.4

0.311 – 0.4297.9 – 10.9

8mm 13" Dia 13.00330

0.0591.5

512 +0.020/-0.00813 +0.5/-0.2

0.79520.2

4.00100

0.331 +0.059/-0.0008.4 +1.5/0

0.56714.4

0.311 – 0.4297.9 – 10.9

See detail AA

Dim Amax

13" Diameter Option

7" Diameter Option

Dim AMax

See detail AA

W3

W2 max Measured at Hub

W1 Measured at Hub

Dim N

Dim Dmin

Dim C

B Min

DETAIL AA

Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481rotational and lateral movement requirements (see sketches A, B, and C).

20 deg maximum component rotation

0.5mmmaximum

0.5mmmaximum

Sketch C (Top View)Component lateral movement

Typicalcomponentcavitycenter line

20 deg maximum

Typicalcomponentcenter line

B0

A0

Sketch B (Top View)Component Rotation

Sketch A (Side or Front Sectional View)Component Rotation


SOT-23 Embossed Carrier TapeConfiguration: Figure 3.0

SOT-23 Reel Configuration: Figure 4.0

P1 A0

D1

F W

E1

E2

Tc

Wc

K0

T

B0

D0P0 P2

SOT-23 Tape and Reel Data, continued

September 1999, Rev. C

SOT-23 (FS PKG Code 49)

SOT-23 Package Dimensions

September 1998, Rev. A1

1:1Scale 1:1 on letter size paper

Dimensions shown below are in:inches [millimeters]


©2000 Fairchild Semiconductor International

SOT-223 PackagingConfiguration: Figure 1.0

ComponentsLeader Tape500mm minimum or62 empty pockets

Trailer Tape300mm minimum or38 empty pockets

SOT-223 Tape Leader and TrailerConfiguration: Figure 2.0

Cover Tape

Carrier Tape

Note/Comments

Packaging Option

SOT-223 Packaging Information

Standard(no flow code) D84Z

Packaging type

Reel Size

TNR

13" Dia

TNR

7" Dia

Qty per Reel/Tube/Bag 2,500 500

Box Dimension (mm) 343x64x343 184x187x47

Max qty per Box 5,000 1,000

Weight per unit (gm) 0.1246 0.1246

Weight per Reel (kg) 0.7250 0.1532

SOT-223 Unit Orientation

F852014

F852014

F852014

F852014

F63TNR Label343mm x 342mm x 64mm

Intermediate box for Standard

184mm x 184mm x 47mmPizza Box for D84Z Option

F63TNR Label

LOT: CBVK741B019

FSID: PN2222A

D/C1: D9842 QTY1: SPEC REV:

SPEC:

QTY: 3000

D/C2: QTY2: CPN:N/F: F (F63TNR)3

F63TNR Label sample

F63TNR Label

Antistatic Cover Tape

Customized Label

Static Dissipative Embossed Carrier Tape

Packaging Description:

SOT-223 parts are shipped in tape. The carrier tape ismade from a dissipative (carbon filled) polycarbonateresin. The cover tape is a multilayer film (Heat ActivatedAdhesive in nature) primarily composed of polyester film,adhesive layer, sealant, and anti-static sprayed agent.These reeled parts in standard option are shipped with2,500 units per 13" or 330cm diameter reel. The reels aredark blue in color and is made of polystyrene plastic (anti-static coated). Other option comes in 500 units per 7" or177cm diameter reel. This and some other options arefurther described in the Packaging Information table.

These full reels are individually barcode labeled andplaced inside a standard intermediate box (illustrated infigure 1.0) made of recyclable corrugated brown paper.One box contains two reels maximum. And these boxesare placed inside a barcode labeled shipping box whichcomes in different sizes depending on the number of partsshipped.

SOT-223 Tape and Reel Data

September 1999, Rev. B©2000 Fairchild Semiconductor International

Dimensions are in millimeter

Pkg type A0 B0 W D0 D1 E1 E2 F P1 P0 K0 T Wc Tc

SOT-223(12mm)

6.83+/-0.10

7.42+/-0.10

12.0+/-0.3

1.55+/-0.05

1.50+/-0.10

1.75+/-0.10

10.25min

5.50+/-0.05

8.0+/-0.1

4.0+/-0.1

1.88+/-0.10

0.292+/-0.0130

9.5+/-0.025

0.06+/-0.02

P1A0 D1

P0

F

W

E1

D0

E2B0

Tc

WcK0

T

Dimensions are in inches and millimeters

Tape SizeReel

Option Dim A Dim B Dim C Dim D Dim N Dim W1 Dim W2 Dim W3 (LSL-USL)

12mm 7" Dia 7.00177.8

0.0591.5

512 +0.020/-0.00813 +0.5/-0.2

0.79520.2

5.906150

0.488 +0.078/-0.00012.4 +2/0

0.72418.4

0.469 – 0.60611.9 – 15.4

12mm 13" Dia 13.00330

0.0591.5

512 +0.020/-0.00813 +0.5/-0.2

0.79520.2

7.00178

0.488 +0.078/-0.00012.4 +2/0

0.72418.4

0.469 – 0.60611.9 – 15.4

See detail AA

Dim Amax

13" Diameter Option

7" Diameter Option

Dim AMax

See detail AA

W3

W2 max Measured at Hub

W1 Measured at Hub

Dim N

Dim Dmin

Dim C

B Min

DETAIL AA

Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481rotational and lateral movement requirements (see sketches A, B, and C).

20 deg maximum component rotation

0.5mmmaximum

0.5mmmaximum

Sketch C (Top View)Component lateral movement

Typicalcomponentcavitycenter line

20 deg maximum

Typicalcomponentcenter line

B0

A0

Sketch B (Top View)Component Rotation

Sketch A (Side or Front Sectional View)Component Rotation


SOT-223 Embossed Carrier TapeConfiguration: Figure 3.0

SOT-223 Reel Configuration: Figure 4.0

SOT-223 Tape and Reel Data, continued

July 1999, Rev. B

SOT-223 (FS PKG Code 47)

SOT-223 Package Dimensions

1 : 1

Scale 1:1 on letter size paper


September 1999, Rev. C©2000 Fairchild Semiconductor International

TRADEMARKSThe following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and isnot intended to be an exhaustive list of all such trademarks.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.As used herein:1. Life support devices or systems are devices orsystems which, (a) are intended for surgical implant intothe body, or (b) support or sustain life, or (c) whosefailure to perform when properly used in accordancewith instructions for use provided in the labeling, can bereasonably expected to result in significant injury to theuser.

2. A critical component is any component of a lifesupport device or system whose failure to perform canbe reasonably expected to cause the failure of the lifesupport device or system, or to affect its safety oreffectiveness.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification Product Status Definition

Advance Information

Preliminary

No Identification Needed

Obsolete

This datasheet contains the design specifications forproduct development. Specifications may change inany manner without notice.

This datasheet contains preliminary data, andsupplementary data will be published at a later date.Fairchild Semiconductor reserves the right to makechanges at any time without notice in order to improvedesign.

This datasheet contains final specifications. FairchildSemiconductor reserves the right to make changes atany time without notice in order to improve design.

This datasheet contains specifications on a productthat has been discontinued by Fairchild semiconductor.The datasheet is printed for reference information only.

Formative orIn Design

First Production

Full Production

Not In Production

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHERNOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILDDOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCTOR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENTRIGHTS, NOR THE RIGHTS OF OTHERS.

PowerTrenchQFET™QS™QT Optoelectronics™Quiet Series™SILENT SWITCHERSMART START™SuperSOT™-3SuperSOT™-6SuperSOT™-8

FASTr™GlobalOptoisolator™GTO™HiSeC™ISOPLANAR™MICROWIRE™OPTOLOGIC™OPTOPLANAR™PACMAN™POP™

Rev. G

ACEx™Bottomless™CoolFET™CROSSVOLT™DOME™E2CMOSTM

EnSignaTM

FACT™FACT Quiet Series™FAST

SyncFET™TinyLogic™UHC™VCX™

1Motorola Bipolar Power Transistor Device Data

. . . designed for use in general–purpose amplifier and switching circuits. Recom-mended for use in 5 to 20 Watt audio amplifiers utilizing complementary symmetrycircuitry.

• DC Current Gain — hFE = 40 (Min) @ IC = 1.0 Adc• MJE371 is Complementary to NPN MJE521

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ




MAXIMUM RATINGS

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ




Rating

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

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Symbol

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

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Value

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

Unit





Collector–Emitter Voltage

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

VCEO

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

40

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

Vdc





Collector–Base Voltage

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

VCB

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

40

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

Vdc





Emitter–Base Voltage

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

VEB

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

4.0

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

Vdc






Collector Current — Continuous— Peak

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

IC

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

4.08.0

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

AdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ




Base Current — Continuous

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

IB

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

2.0

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

Adc






Total Power Dissipation @ TC = 25CDerate above 25C

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

PD

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

40320

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

WattsmW/C





Operating and Storage Junction Temperature Range

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

TJ, Tstg

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

–65 to +150

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

C





THERMAL CHARACTERISTICS





Characteristic

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

Max

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

Unit





Thermal Resistance, Junction to Case

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

θJC

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

3.12

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

C/W





ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)





Characteristic

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

Symbol

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

Min

ÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎ

Max

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

Unit





OFF CHARACTERISTICS






Collector–Emitter Sustaining Voltage (1)(IC = 100 mAdc, IB = 0)

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

VCEO(sus)

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

40

ÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎ

—

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

VdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ




Collector–Base Cutoff Current(VCB = 40 Vdc, IE = 0)

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ICBO

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

—

ÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎ

100

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

µAdc






Emitter–Base Cutoff Current(VEB = 4.0 Vdc, IC = 0)

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

IEBO

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

—

ÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎ

100

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

µAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ




ON CHARACTERISTICS






DC Current Gain (1)(IC = 1.0 Adc, VCE = 1.0 Vdc)

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

hFE

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

40

ÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎ

—

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

—

(1) Pulse Test: Pulse Width 300 µs, Duty Cycle 2.0%.

SEMICONDUCTOR TECHNICAL DATA

Order this documentby MJE371/D

Motorola, Inc. 1995

4 AMPEREPOWER TRANSISTOR

PNP SILICON40 VOLTS40 WATTS

CASE 77–08TO–225AA TYPE

REV 2

2 Motorola Bipolar Power Transistor Device Data

10

VCE, COLLECTOR–EMITTER VOLTAGE (VOLTS)

0.5

400.1

0.3

BONDING WIRE LIMITSECOND BREAKDOWN LIMITTHERMAL LIMIT @ TC = 25°C

Figure 1. Active–Region Safe Operating Area

5.0

20106.02.0

TJ = 150°C

I C, C

OLL

ECTO

R C

UR

REN

T (A

MP)

1.0

2.03.0

0.2

604.0 8.0

1.0 ms

dc

100 µs

5.0 ms

There are two limitations on the power handling ability of atransistor: average junction temperature and second break-down. Safe operating area curves indicate IC – VCE limits ofthe transistor that must be observed for reliable operation;i.e., the transistor must not be subjected to greater dissipa-tion than the curves indicate.

The data of Figure 1 is based on TJ(pk) = 150C; TC is vari-able depending on conditions. Second breakdown pulse lim-its are valid for duty cycles to 10% provided TJ(pk) 150C.At high case temperatures, thermal limitations will reduce thepower that can be handled to values less then the limitationsimposed by second breakdown.

IC, COLLECTOR CURRENT (AMP)

h FE

, DC

CU

RR

ENT

GAI

N, N

OR

MAL

IZED

7.010

0.02 0.03 0.1 4.00.01

1.00.70.5

0.10.05 0.3 0.50.2

150°C TJ = 25°C

– 55°C

Figure 2. DC Current Gain Figure 3. “On” Voltage

2.0

IC, COLLECTOR CURRENT (AMP)

1.6

0.4

0

TJ = 25°C

VOLT

AGE

(VO

LTS)

VBE(sat) @ IC/IB = 10VBE(on) @ VCE = 1.0 V

5.0

0.3

0.2

1.2

0.8

t, TIME OR PULSE WIDTH (ms)

0.010.01 0.03 1.0 2.0 5.0 10 20 50 100 2000.1 0.50.2

1.0

0.2

0.1

0.05

r(t),

EFFE

CTI

VE T

RAN

SIEN

T

θJC(t) = r(t) θJCθJC = 3.12°C/W MAXD CURVES APPLY FOR POWERPULSE TRAIN SHOWNREAD TIME AT t1TJ(pk) – TC = P(pk) θJC(t)

P(pk)

t1t2

DUTY CYCLE, D = t1/t2

SINGLE PULSETHER

MAL

RES

ISTA

NC

E (N

OR

MAL

IZED

)

Figure 4. Thermal Response

0.5D = 0.5

0.1

0.01

0.3

0.7

0.07

0.03

0.02

3.0

2.0

1.0 3.02.0

VCE = 1.0 Vdc

VCE(sat) @ IC/IB = 10

0.01 0.02 0.05 4.00.005 0.03 0.2 0.30.1 0.5 2.0 3.01.0

0.02 0.05 0.3 3.0 500 1000

0.02

0.05

0.2

3Motorola Bipolar Power Transistor Device Data

PACKAGE DIMENSIONS

CASE 77–08TO–225AA TYPE

ISSUE V

STYLE 1:PIN 1. EMITTER

2. COLLECTOR3. BASE

NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.2. CONTROLLING DIMENSION: INCH.

–B–

–A–M

K

F C

Q

H

VG

S

D

JR

U

1 32

2 PL

MAM0.25 (0.010) B M

MAM0.25 (0.010) B M

DIM MIN MAX MIN MAXMILLIMETERSINCHES

A 0.425 0.435 10.80 11.04B 0.295 0.305 7.50 7.74C 0.095 0.105 2.42 2.66D 0.020 0.026 0.51 0.66F 0.115 0.130 2.93 3.30G 0.094 BSC 2.39 BSCH 0.050 0.095 1.27 2.41J 0.015 0.025 0.39 0.63K 0.575 0.655 14.61 16.63M 5 TYP 5 TYPQ 0.148 0.158 3.76 4.01R 0.045 0.055 1.15 1.39S 0.025 0.035 0.64 0.88U 0.145 0.155 3.69 3.93V 0.040 ––– 1.02 –––

4 Motorola Bipolar Power Transistor Device Data

How to reach us:USA / EUROPE: Motorola Literature Distribution; JAPAN : Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki,P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315

MFAX: [email protected] – TOUCHTONE (602) 244–6609 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, INTERNET: http://Design–NET.com 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in differentapplications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola doesnot convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components insystems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure ofthe Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any suchunintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmlessagainst all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or deathassociated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

MJE371/D

◊

TL/H/9341

LM

741

Opera

tionalA

mplifie

r

November 1994

LM741 Operational Amplifier

General DescriptionThe LM741 series are general purpose operational amplifi-

ers which feature improved performance over industry stan-

dards like the LM709. They are direct, plug-in replacements

for the 709C, LM201, MC1439 and 748 in most applications.

The amplifiers offer many features which make their appli-

cation nearly foolproof: overload protection on the input and

output, no latch-up when the common mode range is ex-

ceeded, as well as freedom from oscillations.

The LM741C/LM741E are identical to the LM741/LM741A

except that the LM741C/LM741E have their performance

guaranteed over a 0§C to a70§C temperature range, in-

stead of b55§C to a125§C.

Schematic Diagram

TL/H/9341–1

Offset Nulling Circuit

TL/H/9341–7

C1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

Absolute Maximum RatingsIf Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

(Note 5)

LM741A LM741E LM741 LM741C

Supply Voltage g22V g22V g22V g18V

Power Dissipation (Note 1) 500 mW 500 mW 500 mW 500 mW

Differential Input Voltage g30V g30V g30V g30V

Input Voltage (Note 2) g15V g15V g15V g15V

Output Short Circuit Duration Continuous Continuous Continuous Continuous

Operating Temperature Range b55§C to a125§C 0§C to a70§C b55§C to a125§C 0§C to a70§CStorage Temperature Range b65§C to a150§C b65§C to a150§C b65§C to a150§C b65§C to a150§CJunction Temperature 150§C 100§C 150§C 100§CSoldering Information

N-Package (10 seconds) 260§C 260§C 260§C 260§CJ- or H-Package (10 seconds) 300§C 300§C 300§C 300§CM-Package

Vapor Phase (60 seconds) 215§C 215§C 215§C 215§CInfrared (15 seconds) 215§C 215§C 215§C 215§C

See AN-450 ‘‘Surface Mounting Methods and Their Effect on Product Reliability’’ for other methods of soldering

surface mount devices.

ESD Tolerance (Note 6) 400V 400V 400V 400V

Electrical Characteristics (Note 3)

Parameter ConditionsLM741A/LM741E LM741 LM741C

UnitsMin Typ Max Min Typ Max Min Typ Max

Input Offset Voltage TA e 25§CRS s 10 kX 1.0 5.0 2.0 6.0 mV

RS s 50X 0.8 3.0 mV

TAMIN s TA s TAMAX

RS s 50X 4.0 mV

RS s 10 kX 6.0 7.5 mV

Average Input Offset15 mV/§C

Voltage Drift

Input Offset Voltage TA e 25§C, VS e g20Vg10 g15 g15 mV

Adjustment Range

Input Offset Current TA e 25§C 3.0 30 20 200 20 200 nA

TAMIN s TA s TAMAX 70 85 500 300 nA

Average Input Offset0.5 nA/§C

Current Drift

Input Bias Current TA e 25§C 30 80 80 500 80 500 nA

TAMIN s TA s TAMAX 0.210 1.5 0.8 mA

Input Resistance TA e 25§C, VS e g20V 1.0 6.0 0.3 2.0 0.3 2.0 MX

TAMIN s TA s TAMAX,0.5 MX

VS e g20V

Input Voltage Range TA e 25§C g12 g13 V

TAMIN s TA s TAMAX g12 g13 V

Large Signal Voltage Gain TA e 25§C, RL t 2 kX

VS e g20V, VO e g15V 50 V/mV

VS e g15V, VO e g10V 50 200 20 200 V/mV

TAMIN s TA s TAMAX,

RL t 2 kX,


VS e g15V, VO e g10V 25 15 V/mV


2

Electrical Characteristics (Note 3) (Continued)

Parameter ConditionsLM741A/LM741E LM741 LM741C

UnitsMin Typ Max Min Typ Max Min Typ Max

Output Voltage Swing VS e g20V

RL t 10 kX g16 V

RL t 2 kX g15 V

VS e g15V

RL t 10 kX g12 g14 g12 g14 V

RL t 2 kX g10 g13 g10 g13 V

Output Short Circuit TA e 25§C 10 25 35 25 25 mA

Current TAMIN s TA s TAMAX 10 40 mA

Common-Mode TAMIN s TA s TAMAX

Rejection Ratio RS s 10 kX, VCM e g12V 70 90 70 90 dB

RS s 50X, VCM e g12V 80 95 dB

Supply Voltage Rejection TAMIN s TA s TAMAX,

Ratio VS e g20V to VS e g5V

RS s 50X 86 96 dB

RS s 10 kX 77 96 77 96 dB

Transient Response TA e 25§C, Unity Gain

Rise Time 0.25 0.8 0.3 0.3 ms

Overshoot 6.0 20 5 5 %

Bandwidth (Note 4) TA e 25§C 0.437 1.5 MHz

Slew Rate TA e 25§C, Unity Gain 0.3 0.7 0.5 0.5 V/ms

Supply Current TA e 25§C 1.7 2.8 1.7 2.8 mA

Power Consumption TA e 25§CVS e g20V 80 150 mW

VS e g15V 50 85 50 85 mW

LM741A VS e g20V

TA e TAMIN 165 mW

TA e TAMAX 135 mW

LM741E VS e g20V

TA e TAMIN 150 mW

TA e TAMAX 150 mW

LM741 VS e g15V

TA e TAMIN 60 100 mW

TA e TAMAX 45 75 mW

Note 1: For operation at elevated temperatures, these devices must be derated based on thermal resistance, and Tj max. (listed under ‘‘Absolute Maximum

Ratings’’). Tj e TA a (ijA PD).

Thermal Resistance Cerdip (J) DIP (N) HO8 (H) SO-8 (M)

ijA (Junction to Ambient) 100§C/W 100§C/W 170§C/W 195§C/W

ijC (Junction to Case) N/A N/A 25§C/W N/A

Note 2: For supply voltages less than g15V, the absolute maximum input voltage is equal to the supply voltage.

Note 3: Unless otherwise specified, these specifications apply for VS e g15V, b55§C s TA s a125§C (LM741/LM741A). For the LM741C/LM741E, these

specifications are limited to 0§C s TA s a70§C.

Note 4: Calculated value from: BW (MHz) e 0.35/Rise Time(ms).

Note 5: For military specifications see RETS741X for LM741 and RETS741AX for LM741A.

Note 6: Human body model, 1.5 kX in series with 100 pF.

3

Connection Diagrams

Metal Can Package

TL/H/9341–2

Order Number LM741H, LM741H/883*,

LM741AH/883 or LM741CH

See NS Package Number H08C

Dual-In-Line or S.O. Package

TL/H/9341–3

Order Number LM741J, LM741J/883,

LM741CM, LM741CN or LM741EN

See NS Package Number J08A, M08A or N08E

Ceramic Dual-In-Line Package

TL/H/9341–5

Order Number LM741J-14/883*, LM741AJ-14/883**See NS Package Number J14A

*also available per JM38510/10101

**also available per JM38510/10102

Ceramic Flatpak

TL/H/9341–6

Order Number LM741W/883

See NS Package Number W10A

*LM741H is available per JM38510/10101

4

Physical Dimensions inches (millimeters)

Metal Can Package (H)

Order Number LM741H, LM741H/883, LM741AH/883, LM741CH or LM741EH

NS Package Number H08C

5

Physical Dimensions inches (millimeters) (Continued)

Ceramic Dual-In-Line Package (J)

Order Number LM741CJ or LM741J/883

NS Package Number J08A

Ceramic Dual-In-Line Package (J)

Order Number LM741J-14/883 or LM741AJ-14/883

NS Package Number J14A

6


Small Outline Package (M)

Order Number LM741CM

NS Package Number M08A

Dual-In-Line Package (N)

Order Number LM741CN or LM741EN

NS Package Number N08E

7

LM

741

Opera

tionalA

mplifier


10-Lead Ceramic Flatpak (W)

Order Number LM741W/883

NS Package Number W10A

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or 2. A critical component is any component of a life

systems which, (a) are intended for surgical implant support device or system whose failure to perform can

into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life

failure to perform, when properly used in accordance support device or system, or to affect its safety or

with instructions for use provided in the labeling, can effectiveness.

be reasonably expected to result in a significant injury

to the user.

National Semiconductor National Semiconductor National Semiconductor National SemiconductorCorporation Europe Hong Kong Ltd. Japan Ltd.1111 West Bardin Road Fax: (a49) 0-180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2309Arlington, TX 76017 Email: cnjwge@ tevm2.nsc.com Ocean Centre, 5 Canton Rd. Fax: 81-043-299-2408Tel: 1(800) 272-9959 Deutsch Tel: (a49) 0-180-530 85 85 Tsimshatsui, KowloonFax: 1(800) 737-7018 English Tel: (a49) 0-180-532 78 32 Hong Kong

Fran3ais Tel: (a49) 0-180-532 93 58 Tel: (852) 2737-1600Italiano Tel: (a49) 0-180-534 16 80 Fax: (852) 2736-9960

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

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