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ELEN654 ATM
Signal Integrity Issues»Capacitive Coupling, Resistance, Inductance»Cross talk
Routability design, Coding, and other Design Measures for protectionI/O DesignPackaging
Routing Considerations
ELEN654 ATM
Impact of Interconnect Parasitics
• Reduce Robustness
• Affect Performance• Increase delay• Increase power dissipation
Classes of Parasitics
• Capacitive
• Resistive
• Inductive
ELEN654 ATM
Capacitive Cross Talk
X
YVX
CXY
CY
ELEN654 ATM
Capacitive Cross TalkDynamic Node
3 x 1 m overlap: 0.19 V disturbance
CY
CXY
VDD
PDN
CLK
CLK
In1
In2
In3
Y
X
2.5 V
0 V
ELEN654 ATM
Capacitive Cross TalkDriven Node
XY = RY(CXY+CY)
Keep time-constant smaller than rise time
0
0.5
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
010.80.6
t (nsec)
0.40.2
X
YVXRY
CXY
CY
tr↑
ELEN654 ATM
Dealing with Capacitive Cross Talk
Avoid floating nodes Protect sensitive nodes Make rise and fall times as large as possible Differential signaling Do not run wires together for a long distance Use shielding wires Use shielding layers
ELEN654 ATM
Shielding
GND
GND
Shieldingwire
Substrate (GND )
Shieldinglayer
VDD
ELEN654 ATM
Cross Talk and Performance
Cc
- When neighboring lines switch in opposite direction of victim line, delay increases
DELAY DEPENDENT UPON ACTIVITY IN NEIGHBORING WIRES
Miller EffectMiller Effect
- Both terminals of capacitor are switched in opposite directions (0 Vdd, Vdd 0)
- Effective voltage is doubled and additional charge is needed (from Q=CV)
ELEN654 ATM
Impact of Cross Talk on Delay
r is ratio between capacitance to GND and to neighbor
ELEN654 ATM
Structured Predictable Interconnect
S
S SV V S
G
S
SV
G
VS
S SV V S
G
S
SV
G
VExample: Dense Wire Fabric ([Sunil Kathri])Trade-off:• Cross-coupling capacitance 40x lower, 2% delay variation• Increase in area and overall capacitance Also: FPGAs, VPGAs
ELEN654 ATM
Interconnect ProjectionsLow-k dielectrics
Both delay and power are reduced by dropping interconnect capacitance
Types of low-k materials include: inorganic (SiO2), organic (Polyimides) and aerogels (ultra low-k)
The numbers below are on the conservative side of the NRTS roadmap
ELEN654 ATM
Encoding Data Avoids Worst-Case
Conditions
Encoder
Decoder
Bus
In
Out
ELEN654 ATM
Information Theoretic Approach to Address Delay and Reliability in Long On-chip Interconnects
Interconnects
ELEN654 ATM
Overview
ELEN654 ATM
Sources of Error on Interconnects
Capacitive Coupling Inductive Coupling Process Variations Power Noise
ELEN654 ATM
Signal Integrity
Tradition:» Protect the signal on every single wire.» Design the clock period to be greater than the
worst case delay.
Questions asked?» Is it an overkill?» Can some errors be tolerated?» Can this be optimized?
ELEN654 ATM
Capacitive Coupling
Signals are influenced by the signals in the adjacent wires due to coupling capacitance
Phenomenon known as “Crosstalk” Results in “Deterministic” Delay Variations
ELEN654 ATM
Modeling Interconnects
I(s) G(s) O(s)
O(s) = G(s).I(s)
ELEN654 ATM
Modeling Interconnects
I(s) G(s) O(s)
Capacitive Coupling
Structure
ELEN654 ATM
Modeling Interconnects
I(s) G(s) O(s)
Inductive Coupling
Structure
ELEN654 ATM
Modeling Interconnects
I(s) G(s) O(s)
Power Noise
Randomness
ELEN654 ATM
Modeling Interconnects
I(s) G(s) O(s)
Process Variations
Randomness
ELEN654 ATM
Transfer Function
O(s) = F(s).I(s) F(s) = (1 + L(s)C(s))-
1
ELEN654 ATM
Bus Delay
ELEN654 ATM
Bus Delay
ELEN654 ATM
Waveforms
ELEN654 ATM
ELEN654 ATM
Problems in Interconnects
Delay Power Reliability
ELEN654 ATM
Binary Symmetric Channel
Inputs, Outputs Є {0,1} Crossover Probability pe
0
1
pe
1-pe1
0
pe
1-pe
ELEN654 ATM
Self Information(of an event)
Defined as » - log2(p)
– p is the probability of occurrence.
Example » if 1 occurs with p = ½, then every time it
occurs -log2(1/2) = 1 bits of information is conveyed.
ELEN654 ATM
Entropy
Entropy of a system of random events is the measure of uncertainty
Defined as» H(S)= -Σ p.log2(p)
– p is the probability of occurrence of each event in the system.
Example: » For a random binary system
– H = - p1.log2(p1) - p0.log2(p0)– If p1 = p0 = ½, H = 1 bit.
ELEN654 ATM
Conditional Entropy
The uncertainty in one system, given the outcome of the second system.
Defined as» H(S1|S2) = -Σ Σ pjk.log2(pjk/pk)
– J and k are events in systems 1 and 2 respectively.– The equation represents the entropy of system1
conditioned upon the outcome of system 2.
ELEN654 ATM
Channel Capacity
reduction in uncertainty about the input given the output
C = H(Si) – H(Si|So)
For p1 = p0 = ½
» C = 1 + pe.log2(pe) + (1-pe).log2(1-pe)
ELEN654 ATM
Channels with memory
Have multiple states» A1, A2,…, An
Each state has a probability of occurrence» p1,p2,…,pn
Each state has a probability of error» pe1,pe2,…,pen
Capacity of each state» Ci = 1 + pei log(pei) + (1+pei) log(1+pei)
Capacity of channel» C=Σ pi Ci
ELEN654 ATM
The States
ELEN654 ATM
Capacity
ELEN654 ATM
Capacity
ELEN654 ATM
ELEN654 ATM
ELEN654 ATM
Concluding Remark» Non of the simple ad-hoc codes are
approaching the capacity
Current/Future work» Capacity-approaching bus codes.. and bus
design
ELEN654 ATM
Driving Large Capacitances
V in Vout
CL
VDD
• Transistor Sizing• Cascaded Buffers
ELEN654 ATM
Using Cascaded Buffers
CL = 20 pF
In Out
1 2 N
0.25 m processCin = 2.5 fFtp0 = 30 ps
F = CL/Cin = 8000fopt = 3.6 N = 7tp = 0.76 ns
ELEN654 ATM
Output Driver Design
Trade off Performance for Area and Energy
Given tpmax find N and f Area
Energy
minminmin12
1
1
1
1...1 A
f
FA
f
fAfffA
NN
driver
22212
11
1...1 DD
LDDiDDi
Ndriver V
f
CVC
f
FVCfffE
ELEN654 ATM
Delay as a Function of F and N
101 3 5 7
Number of buffer stages N
9 11
10,000
1000
100
F = 100F = 1000
F = 10,000t p
/tp
0
ELEN654 ATM
Output Driver Design
Transistor Sizes for optimally-sized cascaded buffer tp = 0.76 ns
Transistor Sizes of redesigned cascaded buffer tp = 1.8 ns
0.25 m process, CL = 20 pF
ELEN654 ATM
How to Design Large Transistors
G(ate)
S(ource)
D(rain)
Multiple
Contacts
small transistors in parallel
Reduces diffusion capacitanceReduces gate resistance
ELEN654 ATM
Bonding Pad DesignBonding Pad
Out
InVDD GND
100 m
GND
Out
ELEN654 ATM
ESD Protection
When a chip is connected to a board, there is unknown (potentially large) static voltage difference
Equalizing potentials requires (large) charge flow through the pads
Diodes sink this charge into the substrate – need guard rings to pick it up.
ELEN654 ATM
ESD Protection
Diode
PAD
VDD
R D1
D2
X
C
ELEN654 ATM
Chip Packaging
ChipL
L ´
Bonding wire
Mountingcavity
Leadframe
Pin
•Bond wires (~25m) are used to connect the package to the chip
• Pads are arranged in a frame around the chip
• Pads are relatively large (~100m in 0.25m technology),with large pitch (100m)
•Many chips areas are ‘pad limited’
ELEN654 ATM
Pad Frame
Layout Die Photo
ELEN654 ATM
Chip Packaging An alternative is ‘flip-chip’:
» Pads are distributed around the chip» The soldering balls are placed on pads» The chip is ‘flipped’ onto the package» Can have many more pads
ELEN654 ATM
Tristate Buffers
InEn
En
VDD
Out
Out = In.En + Z.En
VDD
In
En
En
Out
Increased output drive
ELEN654 ATM
Reducing the swing
tpHL = CL Vswing/2
Iav
Reducing the swing potentially yields linear reduction in delay Also results in reduction in power dissipation Delay penalty is paid by the receiver Requires use of “sense amplifier” to restore signal level Frequently designed differentially (e.g. LVDS)
ELEN654 ATM
Single-Ended Static Driver and Receiver
CL
VDD
VDD VDD
driver receiver
VDDL
VDDLIn
OutOut
ELEN654 ATM
Dynamic Reduced Swing Network
fIn2.fIn1.
f M2
M1 M3
M4
Cbus Cout
Bus Out
VDD VDD
f
Vbus
Vasym
Vsym
2 4 6time (ns)
8 10 120
0.5
1
1.5
2
2.5
0
ELEN654 ATM
Impact of Resistance
We have already learned how to drive RC interconnect
Impact of resistance is commonly seen in power supply distribution:» IR drop» Voltage variations
Power supply is distributed to minimize the IR drop and the change in current due to switching of gates
ELEN654 ATM
RI Introduced Noise
M1
X
I
R9
RDV
fpre
DV
VDD
VDD 2 DV9
I
ELEN654 ATM19
ASP DAC 2000
Power Dissipation TrendsPower Dissipation Trends
Power consumption is increasingPower consumption is increasing Better cooling technology neededBetter cooling technology needed
Supply current is increasing faster!Supply current is increasing faster!
OnOn--chip signal integrity will be a major chip signal integrity will be a major issueissue
Power and current distribution are criticalPower and current distribution are critical
Opportunities to slow power growthOpportunities to slow power growth Accelerate Accelerate VddVdd scalingscaling
Low κ dielectrics & thinner (Cu) Low κ dielectrics & thinner (Cu) interconnectinterconnect
SOI circuit innovations SOI circuit innovations
Clock system designClock system design
micromicro--architecturearchitecture
Power Dissipation
020406080
100120140160
EV4 EV5 EV6 EV7 EV8
Po
we
r (W
)
0
0.5
1
1.5
2
2.5
3
3.5
Vol
tage
(V
)
Supply Current
0
20
40
60
80
100
120
140
EV4 EV5 EV6 EV7 EV8
Curr
ent (
A)
0
0.5
1
1.5
2
2.5
3
3.5
Vo
ltag
e (
V)
ELEN654 ATM
Resistance and the Power Distribution Problem
Source: Cadence
• Requires fast and accurate peak current predictionRequires fast and accurate peak current prediction• Heavily influenced by packaging technologyHeavily influenced by packaging technology
BeforeBefore AfterAfter
ELEN654 ATM
Power Distribution
Low-level distribution is in Metal 1 Power has to be ‘strapped’ in higher layers of
metal. The spacing is set by IR drop,
electromigration, inductive effects Always use multiple contacts on straps
ELEN654 ATM
Power and Ground Distribution
GND
VDD
Logic
GND
VDD
Logic
GND
VDD
(a) Finger-shaped network (b) Network with multiple supply pins
ELEN654 ATM
3 Metal Layer Approach (EV4)
3rd “coarse and thick” metal layer added to thetechnology for EV4 design
Power supplied from two sides of the die via 3rd metal layer
2nd metal layer used to form power grid
90% of 3rd metal layer used for power/clock routing
Metal 3
Metal 2
Metal 1
Courtesy Compaq
ELEN654 ATM
4 Metal Layers Approach (EV5)
4th “coarse and thick” metal layer added to thetechnology for EV5 design
Power supplied from four sides of the die
Grid strapping done all in coarse metal
90% of 3rd and 4th metals used for power/clock routing
Metal 3
Metal 2
Metal 1
Metal 4
Courtesy Compaq
ELEN654 ATM
2 reference plane metal layers added to thetechnology for EV6 designSolid planes dedicated to Vdd/Vss
Significantly lowers resistance of gridLowers on-chip inductance
6 Metal Layer Approach – EV6
Metal 4
Metal 2Metal 1
RP2/Vdd
RP1/Vss
Metal 3
Courtesy Compaq
ELEN654 ATM
Electromigration (1)
Limits dc-current to 1 mA/m
ELEN654 ATM
Electromigration (2)
ELEN654 ATM
Resistivity and Performance
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50
0.5
1
1.5
2
2.5
time (nsec)
volta
ge
(V
)
x= L/10
x = L/4
x = L/2
x= L
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50
0.5
1
1.5
2
2.5
time (nsec)
volta
ge
(V
)
x= L/10
x = L/4
x = L/2
x= L
Diffused signal Diffused signal propagationpropagation
Delay ~ LDelay ~ L22
CN-1 CNC2
R1 R2
C1
Tr
Vin
RN-1 RN
The distributed rc-lineThe distributed rc-line
ELEN654 ATM
The Global Wire Problem
Challenges No further improvements to be expected after the
introduction of Copper (superconducting, optical?) Design solutions
» Use of fat wires» Insert repeaters — but might become prohibitive (power, area)» Efficient chip floorplanning
Towards “communication-based” design » How to deal with latency?» Is synchronicity an absolute necessity?
outwwdoutdwwd CRCRCRCRT 693.0377.0
ELEN654 ATM
Interconnect Projections: Copper
Copper is planned in full sub-0.25 m process flows and large-scale designs (IBM, Motorola, IEDM97)
With cladding and other effects, Cu ~ 2.2 -cm vs. 3.5 for Al(Cu) 40% reduction in resistance
Electromigration improvement; 100X longer lifetime (IBM, IEDM97)
» Electromigration is a limiting factor beyond 0.18 m if Al is used (HP, IEDM95)
Vias
ELEN654 ATM
Interconnect:# of Wiring Layers
# of metal layers is steadily increasing due to:
• Increasing die size and device count: we need more wires and longer wires to connect everything
• Rising need for a hierarchical wiring network; local wires with high density and global wires with low RC
substrate
poly
M1
M2
M3
M4
M5
M6
Tins
H
WS
= 2.2 -cm
0.25 m wiring stack
Minimum Widths (Relative)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
M5
M4
M3
M2
M1
Poly
Minimum Spacing (Relative)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
M5
M4
M3
M2
M1
Poly
ELEN654 ATM
Diagonal Wiring
y
x
destination
Manhattan
source
diagonal
• 20+% Interconnect length reduction• Clock speed Signal integrity Power integrity • 15+% Smaller chips plus 30+% via reduction
Courtesy Cadence X-initiative
ELEN654 ATM
Using BypassesDriver
Polysilicon word line
Polysilicon word line
Metal word line
Metal bypass
Driving a word line from both sides
Using a metal bypass
WL
WL K cells
ELEN654 ATM
Reducing RC-delay
Repeater
ELEN654 ATM
Repeater Insertion (Revisited)
Taking the repeater loading into account
For a given technology and a given interconnect layer, there exists For a given technology and a given interconnect layer, there exists an optimal length of the wire segments between repeaters. The an optimal length of the wire segments between repeaters. The delay of these wire segments is delay of these wire segments is independent of the routing layer!independent of the routing layer!
ELEN654 ATM
Inductance IssuesL di/dt
Impact of inductance on supply voltages:• Change in current induces a change in voltage• Longer supply lines have larger LCL
V’DD
VDD
L i(t)
VoutVin
GND’
L
ELEN654 ATM
L di/dt: Simulation
0 0.5 1 1.5 2
x 10-9
0
0.5
1
1.5
2
2.5V
out (
V)
0 0.5 1 1.5 2
x 10-9
0
0.02
0.04
i L (A
)
0 0.5 1 1.5 2
x 10-9
0
0.5
1
VL (
V)
time (nsec)
0 0.5 1 1.5 2
x 10-9
0
0.5
1
1.5
2
2.5
0 0.5 1 1.5 2
x 10-9
0
0.02
0.04
0 0.5 1 1.5 2
x 10-9
0
0.5
1
time (nsec)
Input rise/fall time: 50 psec Input rise/fall time: 800 psec
decoupled
Without inductorsWith inductors
ELEN654 ATM
Dealing with Ldi/dt
Separate power pins for I/O pads and chip core. Multiple power and ground pins. Careful selection of the positions of the power
and ground pins on the package. Increase the rise and fall times of the off-chip
signals to the maximum extent allowable. Schedule current-consuming transitions. Use advanced packaging technologies. Add decoupling capacitances on the board. Add decoupling capacitances on the chip.
ELEN654 ATM
Choosing the Right Pin
ChipL
L ´
Bonding wire
Mountingcavity
Leadframe
Pin
ELEN654 ATM
Decoupling Capacitors
SUPPLY
Boardwiring
Bondingwire
Decouplingcapacitor
CHIPCd
1
2
Decoupling capacitors are added: • on the board (right under the supply pins)• on the chip (under the supply straps, near large buffers)
ELEN654 ATM
De-coupling Capacitor Ratios
EV4» total effective switching capacitance = 12.5nF» 128nF of de-coupling capacitance» de-coupling/switching capacitance ~ 10x
EV5» 13.9nF of switching capacitance » 160nF of de-coupling capacitance
EV6» 34nF of effective switching capacitance» 320nF of de-coupling capacitance -- not enough!
Source: B. Herrick (Compaq)
ELEN654 ATM
EV6 De-coupling Capacitance
Design for Idd= 25 A @ Vdd = 2.2 V, f = 600 MHz» 0.32-µF of on-chip de-coupling capacitance was
added– Under major busses and around major gridded clock
drivers– Occupies 15-20% of die area
» 1-µF 2-cm2 Wirebond Attached Chip Capacitor (WACC) significantly increases “Near-Chip” de-coupling
– 160 Vdd/Vss bondwire pairs on the WACC minimize inductance
Source: B. Herrick (Compaq)
ELEN654 ATM
EV6 WACC
587 IPGA
MicroprocessorWACC
Heat Slug
389 Signal - 198 VDD/VSS Pins389 Signal Bondwires
395 VDD/VSS Bondwires
320 VDD/VSS Bondwires
Source: B. Herrick (Compaq)
ELEN654 ATM
The Transmission Line
The Wave Equation
V in Voutr
g c
r r x
g c
r
g c g c
l l l l
ELEN654 ATM
Design Rules of Thumb
Transmission line effects should be considered when the rise or fall time of the input signal (tr, tf) is smaller than the time-of-flight of the transmission line (tflight).
tr (tf) << 2.5 tflight Transmission line effects should only be considered when the
total resistance of the wire is limited:R < 5 Z0
The transmission line is considered lossless when the total resistance is substantially smaller than the characteristic impedance,
R < Z0/2
ELEN654 ATM
Should we be worried?
Transmission line effects cause overshooting and non-monotonic behavior
Clock signals in 400 MHz IBM Microprocessor(measured using e-beam prober) [Restle98]
ELEN654 ATM
Matched Termination
Z 0 Z L
Z0
Series Source Termination
Z 0 Z 0
Z S
Parallel Destination Termination
ELEN654 ATM
Segmented Matched Line Driver
Z0
c1 c2
s0 s1 s2 sn
cn
ZL
GND
VDD
In
ELEN654 ATM
Parallel Termination─Transistors as Resistors
0.5 1
PMOS with-1V bias
NMOS-PMOS
PMOS only
NMOS only
1.5VR (Volt)
2 2.50
1.11
1.21.31.41.51.61.71.81.9
2
Out
M r
Vdd
Out
M r
Vdd
Vbb
Out
M rp M rn
Vdd
ELEN654 ATM
Output Driver with Varying Terminations
1 2 3 4
time (sec)
Revised design with matched driver impedance
Vs
Vd
Vin
5 6 7 80
1
0
1
2
3
4
1 2 3 4
Initial design
Vs
Vd
Vin
5 6 7 80
1
0
1
2
3
4
V in
L= 2.5 nH
VDD
V s V d
V DD
ClampingDiodes
CL= 5 pF CL
L = 2.5 nH
L = 2.5 nH Z 0 = 50
275
120
ELEN654 ATM
The “Network-on-a-Chip”
EmbeddedProcessorsEmbeddedProcessors
MemorySub-system
MemorySub-system
AccelatorsAccelatorsConfigurableAcceleratorsConfigurableAccelerators
PeripheralsPeripherals
Interconnect Backplane