Em636165

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E t r o n T ec h EM636165

Etron Technology, Inc.

No. 6, Technology Road V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C.TEL: (886)-3-5782345 FAX: (886)-3-5778671

1Mega x 16 Synchronous DRAM (SDRAM)Preliminary (Rev. 1.8, 11/2001)

FeaturesFast access time: 4.5/5/5/5.5/6.5/7.5 nsFast clock rate: 200/183/166/143/125/100 MHzSelf refresh mode: standard and low powerFully synchronous operation Internal pipelined architecture512K x 16 bit x 2-bankProgrammable Mode registers

- CAS# Latency: 1, 2, or 3

- Burst Length: 1, 2, 4, 8, or full page

- Burst Type: interleaved or linear burst

- Burst stop function Individual byte controlled by LDQM and UDQMAuto Refresh and Self Refresh4096 refresh cycles/64msCKE power down modeSingle +3.3V0.3V power supply Interface: LVTTL50-pin 400 mil plastic TSOP II package60-Ball, 6.4 mm x 10.1 mm VFBGA package

(Max total package height=1.0 mm)

Pin Assignment (Top View)

Key SpecificationsEM636165 -5/55/6/7/7L/8/10

tCK3Clock Cycle time(min.) 5/5.5/6/7/7/8/10 ns

tRASRow Active time(max.) 30/32/36/42/42/48/60 ns

tAC3Access time from CLK(max.) 4.5/5/5/5.5/5.5/6.5/7.5 ns

tRC Row Cycle time(min.) 48/48/54/63/63/72/90 ns

Ordering Information

1. Operating temperature : 0~70C

Part Number Frequency Package

EM636165TS/VE-5 200MHz TSOP II ,VFBGAEM636165TS/VE-55 183MHz TSOP II ,VFBGA

EM636165TS/VE -6 166MHz TSOP II ,VFBGA

EM636165TS/VE -7 143MHz TSOP II ,VFBGA

EM636165TS/VE-7L 143MHz TSOP II,VFBGA

EM636165TS/VE -8 125MHz TSOP II,VFBGA

EM636165TS/VE -10 100MHz TSOP II,VFBGA

2. Industrial Operating temperature : -40~85C

Part Number Frequency Package

EM636165TS/VE -10I 100MHz TSOP II,VFBGA

VDDDQ 0DQ 1VS SQDQ 2DQ 3VDDQDQ 4DQ 5VS SQDQ 6DQ 7VDDQ

LDQMWE#

CA S#RA S#

CS #A 1 1A 1 0

A 0A 1A 2A 3VDD

VssDQ15DQ14V SSQDQ13DQ12V DDQDQ11DQ10V SSQDQ 9DQ 8V DDQ

NCUDQMCL KCKENCA 9A 8A 7A 6A 5A 4Vss

1234567891 01 11 21 3

1 41 51 61 71 81 92 02 12 22 32 42 5

5 04 94 84 74 64 54 44 34 24 14 03 93 8

3 73 63 53 43 33 23 13 02 92 82 72 6

A

B

C

D

E

F

G

H

V DD

NC

A 5

A7

VS S

A8

DQ 6

DQ 7

CL K

DQ 8

DQ 9

DQ 3

DQ 1

NC

D Q 1 5

D Q 1 4

D Q 1 2

V D D Q

DQ 4

V D D Q

D Q 1 1

V D D Q

DQ 5V S S Q

U D Q M

V S S Q

D Q 1 0

V S S Q

A6

VD D

CK E

A9

A 0 A 1 0

NC NC

V S S Q

D Q 1 3

NC

NC

NC

A1 1

V S S A 4

NC

NC

V D D Q

DQ 2

NC

NC

NC

L D Q M W E #

C A S #R A S #

CS #

A3

A 2 A 1

J

K

L

M

N

P

R

1 2 3 4 5 6 7

DQ 0

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E t r o n T ec h 1M x 16 SDRAM EM636165Overview

The EM636165 SDRAM is a high-speed CMOS synchronous DRAM containing 16 Mbits. It is internally configuredas a dual 512K x 16 bit DRAM with a synchronous interface (all signals are registered on the positive edge of the clocksignal, CLK). Each of the 512K x 16 bit bank is organized as 2048 rows by 256 columns by 16 bits. Read and writeaccesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed numberof locations in a programmed sequence.

The EM636165 provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a bursttermination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated atthe end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. By having aprogrammable mode register, the system can choose the most suitable modes to maximize its performance. Thesedevices are well suited for applications requiring high memory bandwidth and particularly well suited to high performancePC applications.

Block Diagram

REFRESH

COUNTER

COLUMN

COUNTER

ADDRESS

BUFFER

A0

A11

CONTROL

SIGNAL

GENERATOR

LDQMUDQM

CLOCK

BUFFER

COMMAND

DECODER

Column Decoder

Sense Amplifier

Row

Decoder

2048 X 256 X 16

CELL ARRAY

(BANK #0)

Sense Amplifier

Column Decoder

Row

Decoder

2048 X 256 X 16

CELL ARRAY

(BANK #1)

CLK

CKE

CS#RAS#

CAS#

WE#

DQ0

D

DQ15

DQs Buffer

MODE

REGISTER

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E t r o n T ec h 1M x 16 SDRAM EM636165

Pin DescriptionsTable 1. Pin Details of EM636165

Symbol Type Description

CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampledon the positive edge of CLK. CLK also increments the internal burst counter andcontrols the output registers.

CKE Input Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK signal. IfCKE goes low synchronously with clock(set-up and hold time same as otherinputs), the internal clock is suspended from the next clock cycle and the state ofoutput and burst address is frozen as long as the CKE remains low. When bothbanks are in the idle state, deactivating the clock controls the entry to the PowerDown and Self Refresh modes. CKE is synchronous except after the deviceenters Power Down and Self Refresh modes, where CKE becomesasynchronous until exiting the same mode. The input buffers, including CLK, aredisabled during Power Down and Self Refresh modes, providing low standby

power.A11 Input Bank Select: A11(BS) defines to which bank the BankActivate, Read, Write, or

BankPrecharge command is being applied.

A0-A10 Input Address Inputs: A0-A10 are sampled during the BankActivate command (rowaddress A0-A10) and Read/Write command (column address A0-A7 with A10defining Auto Precharge) to select one location out of the 256K available in therespective bank. During a Precharge command, A10 is sampled to determine ifboth banks are to be precharged (A10 = HIGH). The address inputs also providethe op-code during a Mode Register Set command.

CS# Input Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) thecommand decoder. All commands are masked when CS# is sampled HIGH.

CS# provides for external bank selection on systems with multiple banks. It isconsidered part of the command code.

RAS# Input Row Address Strobe: The RAS# signal defines the operation commands inconjunction with the CAS# and WE# signals and is latched at the positive edgesof CLK. When RAS# and CS# are asserted "LOW" and CAS# is asserted"HIGH," either the BankActivate command or the Precharge command isselected by the WE# signal. When the WE# is asserted "HIGH," theBankActivate command is selected and the bank designated by BS is turned onto the active state. When the WE# is asserted "LOW," the Precharge commandis selected and the bank designated by BS is switched to the idle state after theprecharge operation.

CAS# Input Column Address Strobe: The CAS# signal defines the operation commands in

conjunction with the RAS# and WE# signals and is latched at the positive edgesof CLK. When RAS# is held "HIGH" and CS# is asserted "LOW," the columnaccess is started by asserting CAS# "LOW." Then, the Read or Write commandis selected by asserting WE# "LOW" or "HIGH."

WE# Input Write Enable: The WE# signal defines the operation commands in conjunctionwith the RAS# and CAS# signals and is latched at the positive edges of CLK.The WE# input is used to select the BankActivate or Precharge command andRead or Write command.

LDQM,

UDQM

Input Data Input/Output Mask: LDQM and UDQM are byte specific, nonpersistentI/O buffer controls. The I/O buffers are placed in a high-z state whenLDQM/UDQM is sampled HIGH. Input data is masked when LDQM/UDQM issampled HIGH during a write cycle. Output data is masked (two-clock latency)when LDQM/UDQM is sampled HIGH during a read cycle. UDQM masks DQ15-DQ8, and LDQM masks DQ7-DQ0.

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DQ0-DQ15 Input/Output Data I/O: The DQ0-15 input and output data are synchronized with the positiveedges of CLK. The I/Os are byte-maskable during Reads and Writes.

NC - No Connect: These pins should be left unconnected.

VDDQ Supply DQ Power: Provide isolated power to DQs for improved noise immunity.

( 3.3V 0.3V )

VSSQ Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity.

( 0 V )

VDD Supply Power Supply: +3.3V 0.3V

VSS Supply Ground

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Operation Mode

Fully synchronous operations are performed to latch the commands at the positive edges of CLK.Table 2 shows the truth table for the operation commands.

Table 2. Truth Table (Note (1), (2) )

Command State CKEn-1CKEn DQM(6) A11 A10 A0-9 CS# RAS# CAS# WE#

BankActivate Idle(3) H X X V V V L L H H

BankPrecharge Any H X X V L X L L H L

PrechargeAll Any H X X X H X L L H L

Write Active(3) H X X V L V L H L L

Write and AutoPrecharge Active(3) H X X V H V L H L L

Read Active(3) H X X V L V L H L H

Read and Autoprecharge Active(3) H X X V H V L H L H

Mode Register Set Idle H X X V V V L L L LNo-Operation Any H X X X X X L H H H

Burst Stop Active(4) H X X X X X L H H L

Device Deselect Any H X X X X X H X X X

AutoRefresh Idle H H X X X X L L L H

SelfRefresh Entry Idle H L X X X X L L L H

SelfRefresh Exit Idle L H X X X X H X X X

(SelfRefresh) L H H H

Clock Suspend Mode Entry Active H L X X X X X X X X

Power Down Mode Entry Any(5) H L X X X X H X X X

L H H H

Clock Suspend Mode Exit Active L H X X X X X X X X

Power Down Mode Exit Any L H X X X X H X X X

(PowerDown) L H H H

Data Write/Output Enable Active H X L X X X X X X X

Data Mask/Output Disable Active H X H X X X X X X X

Note: 1. V=Valid X=Don't Care L=Low level H=High level2. CKEn signal is input level when commands are provided.

CKEn-1 signal is input level one clock cycle before the commands are provided.

3. These are states of bank designated by BS signal.4. Device state is 1, 2, 4, 8, and full page burst operation.5. Power Down Mode can not enter in the burst operation.

When this command is asserted in the burst cycle, device state is clock suspend mode.6. LDQM and UDQM

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Commands

1 BankPrecharge command

(RAS# = "L", CAS# = "H", WE# = "L", A11 = V, A10 = "L", A0-A9 = Don't care)The BankPrecharge command precharges the bank disignated by A11 signal. The precharged

bank is switched from the active state to the idle state. This command can be asserted anytime aftertRAS(min.) is satisfied from the BankActivate command in the desired bank. The maximum time anybank can be active is specified by tRAS(max.). Therefore, the precharge function must be performedin any active bank within tRAS(max.). At the end of precharge, the precharged bank is still in the idlestate and is ready to be activated again.

2 PrechargeAll command

(RAS# = "L", CAS# = "H", WE# = "L", A11 = Don't care, A10 = "H", A0-A9 = Don't care)The PrechargeAll command precharges both banks simultaneously and can be issued even if

both banks are not in the active state. Both banks are then switched to the idle state.

3 Read command

(RAS# = "H", CAS# = "L", WE# = "H", A11= V, A9 = "L", A0-A7 = Column Address)The Read command is used to read a burst of data on consecutive clock cycles from an active

row in an active bank. The bank must be active for at least t RCD(min.) before the Read command isissued. During read bursts, the valid data-out element from the starting column address will beavailable following the CAS# latency after the issue of the Read command. Each subsequent data-out element will be valid by the next positive clock edge (refer to the following figure). The DQs gointo high-impedance at the end of the burst unless other command is initiated. The burst length,burst sequence, and CAS# latency are determined by the mode register, which is alreadyprogrammed. A full-page burst will continue until terminated (at the end of the page it will wrap tocolumn 0 and continue).

CLK

COMMAND

CAS# latency=1

tCK1, DQ's

CAS# latency=2

tCK2, DQ's

CAS# latency=3

tCK3, DQ's

T0 T 1 T2 T3 T4 T5 T6 T7 T8

READ A NOP NOP NOP NOP NOP NOP NOP NOP

DOUT A0 DOUT A1 DOUT A2 DOUT A3



Burst Read Operation(Burst Length = 4, CAS# Latency = 1, 2, 3)

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The read data appears on the DQs subject to the values on the LDQM/UDQM inputs two clocksearlier (i.e. LDQM/UDQM latency is two clocks for output buffers). A read burst without the autoprecharge function may be interrupted by a subsequent Read or Write command to the same bankor the other active bank before the end of the burst length. It may be interrupted by a

BankPrecharge/ PrechargeAll command to the same bank too. The interrupt coming from the Readcommand can occur on any clock cycle following a previous Read command (refer to the followingfigure).

CLK

COMMAND

CAS# latency=1

tCK1, DQ's

CAS# latency=2tCK2, DQ's

CAS# latency=3

tCK3, DQ's

T0 T 1 T2 T3 T4 T5 T6 T7 T8

READ A READ B NOP NOP NOP NOP NOP NOP NOP

DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3



Read Interrupted by a Read (Burst Length = 4, CAS# Latency = 1, 2, 3)

The LDQM/UDQM inputs are used to avoid I/O contention on the DQ pins when the interruptcomes from a Write command. The LDQM/UDQM must be asserted (HIGH) at least two clocks priorto the Write command to suppress data-out on the DQ pins. To guarantee the DQ pins against I/Ocontention, a single cycle with high-impedance on the DQ pins must occur between the last read

data and the Write command (refer to the following three figures). If the data output of the burst readoccurs at the second clock of the burst write, the LDQM/UDQM must be asserted (HIGH) at leastone clock prior to the Write command to avoid internal bus contention.

READ A NOP NOP NOP NOP WRITE B NOP NOP

CLK

DQM

COMMAND

DQ's

T0 T 1 T2 T3 T4 T5 T6 T7 T8

NOP

DOUT A0 DINB0DINB1 DINB2

Must be Hi-Z before

the Write Command

: "H" or "L"

Read to Write Interval (Burst Length 4, CAS# Latency = 3)

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CLK

DQM

COMMAND

CAS# latency=1

tCK1, DQ's

T0 T 1 T2 T3 T4 T5 T6 T7 T8

NOP NOP NOP READ A WRITE A NOP NOP NOPBANKA

ACTIVATE

DIN A0 DIN A1 DIN A2 DIN A3

DIN A0 DIN A1 DIN A2 DIN A3

Must be Hi-Z before

the Write Command

1 Clk Interval

CAS# latency=2

tCK2, DQ's

: "H" or "L"

Read to Write Interval (Burst Length 4, CAS# Latency = 1, 2)

CLK

DQM

COMMAND

CAS# latency=1

tCK1, DQ's

T0 T 1 T2 T3 T4 T5 T6 T7 T8

NOP READ A NOP WRITE B NOP NOP NOP

DIN B0 DIN B1 DIN B2 DIN B3

DIN B0 DIN B1 DIN B2 DIN B3

Must be Hi-Z before

the Write CommandCAS# latency=2

tCK2, DQ's

NOP NOP

DOUT A0

: "H" or "L"

Read to Write Interval (Burst Length 4, CAS# Latency = 1, 2)

A read burst without the auto precharge function may be interrupted by a BankPrecharge/PrechargeAll command to the same bank. The following figure shows the optimum time thatBankPrecharge/ PrechargeAll command is issued in different CAS# latency.

CLK

COMMAND

CAS# latency=2

tCK2, DQ's

T0 T 1 T2 T3 T4 T5 T6 T7 T8

READ A NOP NOP NOP NOP Activate NOPNOP Precharge

CAS# latency=3

tCK3, DQ's




ADDRESS

CAS# latency=1

tCK1, DQ's

tRP

Bank,Col A

Bank(s)Bank,Row

Read to Precharge (CAS# Latency = 1, 2, 3)

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4 Read and AutoPrecharge command

(RAS# = "H", CAS# = "L", WE# = "H", A11 = V, A10 = "H", A0-A7 = Column Address)The Read and AutoPrecharge command automatically performs the precharge operation after

the read operation. Once this command is given, any subsequent command cannot occur within a

time delay of {tRP(min.) + burst length}. At full-page burst, only the read operation is performed in thiscommand and the auto precharge function is ignored.

5 Write command

(RAS# = "H", CAS# = "L", WE# = "L", A11 = V, A10 = "L", A0-A7 = Column Address)The Write command is used to write a burst of data on consecutive clock cycles from an active

row in an active bank. The bank must be active for at least t RCD(min.) before the Write command isissued. During write bursts, the first valid data-in element will be registered coincident with the Writecommand. Subsequent data elements will be registered on each successive positive clock edge(refer to the following figure). The DQs remain with high-impedance at the end of the burst unlessanother command is initiated. The burst length and burst sequence are determined by the moderegister, which is already programmed. A full-page burst will continue until terminated (at the end of

the page it will wrap to column 0 and continue).

CLK

COMMAND

T0 T 1 T2 T3 T4 T5 T6 T7 T8

DIN A3

NOP WRITE A NOP NOP NOP NOP NOPNOP NOP

DIN A0 DIN A1 DIN A2DQ0 - DQ3

The first data element and the write

are registered on the same clock edge.Extra data is masked.

don't care

Burst Write Operation (Burst Length = 4, CAS# Latency = 1, 2, 3)

A write burst without the auto precharge function may be interrupted by a subsequent Write,BankPrecharge/PrechargeAll, or Read command before the end of the burst length. An interruptcoming from Write command can occur on any clock cycle following the previous Write command(refer to the following figure).

CLK

COMMAND

T0 T 1 T2 T3 T4 T5 T6 T7 T8

DIN B2

NOP WRITE A NOP NOP NOP NOP NOPWRITE B NOP

DIN A0 DIN B0 DIN B1DQ's DIN B3

1 Clk Interval

Write Interrupted by a Write (Burst Length = 4, CAS# Latency = 1, 2, 3)

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The Read command that interrupts a write burst without auto precharge function should beissued one cycle after the clock edge in which the last data-in element is registered. In order to avoiddata contention, input data must be removed from the DQs at least one clock cycle before the firstread data appears on the outputs (refer to the following figure). Once the Read command is

registered, the data inputs will be ignored and writes will not be executed.

CLK

COMMAND

T0 T 1 T2 T3 T4 T5 T6 T7 T8

DOUT B2

NOP WRITE A NOP NOP NOP NOP NOPREAD B NOP

DIN A0

DOUT B0 DOUT B1CAS# latency=1

tCK1, DQ'sDOUT B3

don't care

DIN A0

DOUT B2DOUT B0 DOUT B1 DOUT B3

DIN A0 don't care don't care DOUT B2DOUT B0 DOUT B1 DOUT B3

Input data for the write is masked.

Input data must be removed from the DQ's at least one clock

cycle before the Read data appears on the outputs to avoid

data contention.

CAS# latency=2

tCK2, DQ's

CAS# latency=3

tCK3, DQ's

Write Interrupted by a Read (Burst Length = 4, CAS# Latency = 1, 2, 3)

The BankPrecharge/PrechargeAll command that interrupts a write burst without the autoprecharge function should be issued m cycles after the clock edge in which the last data-in elementis registered, where m equals tWR/tCK rounded up to the next whole number. In addition, theLDQM/UDQM signals must be used to mask input data, starting with the clock edge following the

last data-in element and ending with the clock edge on which the BankPrecharge/PrechargeAllcommand is entered (refer to the following figure).

CLK

T0 T 1 T2 T3 T4 T5 T6

WRITECOMMAND

BANK (S) ROW

NOP NOPPrecharge NOP NOP Activate

BANKCOL n

DIN

n

DIN

n + 1

DQM

ADDRESS

DQ

tWR

tRP

: don't care

Note: The LDQM/UDQM can remain low in this example if the length of the write burst is 1 or 2.

Write to Precharge

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E t r o n T ec h 1M x 16 SDRAM EM6361656 Write and AutoPrecharge command (refer to the following figure)

(RAS# = "H", CAS# = "L", WE# = "L", A11 = V, A10 = "H", A0-A7 = Column Address)The Write and AutoPrecharge command performs the precharge operation automatically after

the write operation. Once this command is given, any subsequent command can not occur within atime delay of {(burst length -1) + tWR + tRP(min.)}. At full-page burst, only the write operation is

performed in this command and the auto precharge function is ignored.

CLK

COMMAND

T0 T 1 T2 T3 T4 T5 T6 T7 T8

NOP NOP NOP NOP NOPNOP NOP

DIN A0 DIN A1CAS# latency=1

tCK1, DQ's

CAS# latency=2

tCK2, DQ's

CAS# latency=3

tCK3

, DQ's

DIN A0 DIN A1

DIN A0 DIN A1

tDAL

*

*

*tDAL= tWR + tRP * Begin AutoPrechargeBank can be reactivated at completion of tDAL

Bank AActivate

Write AAutoPrecharge

tDAL

tDAL

Burst Write with Auto-Precharge (Burst Length = 2, CAS# Latency = 1, 2, 3)

7 Mode Register Set command

(RAS# = "L", CAS# = "L", WE# = "L", A11 = V, A10 = V, A0-A9 = Register Data)The mode register stores the data for controlling the various operating modes of SDRAM. The

Mode Register Set command programs the values of CAS# latency, Addressing Mode and BurstLength in the Mode register to make SDRAM useful for a variety of different applications. The defaultvalues of the Mode Register after power-up are undefined; therefore this command must be issuedat the power-up sequence. The state of pins A0~A9 and A11 in the same cycle is the data written tothe mode register. One clock cycle is required to complete the write in the mode register (refer to thefollowing figure). The contents of the mode register can be changed using the same command andthe clock cycle requirements during operation as long as both banks are in the idle state.

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RAS#

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10

CLK

CKE

CS#

CAS#

WE#

A11

A10

A0-A9

DQM

DQ

tCK2

Clock min.

Address Key

tRPHi-Z

PrechargeAll Mode Register

Set CommandAny

Command

Mode Register Set Cycle (CAS# Latency = 1, 2, 3)

The mode register is divided into various fields depending on functionality.

Burst Length Field (A2~A0)

This field specifies the data length of column access using the A2~A0 pins and selects theBurst Length to be 1, 2, 4, 8, or full page.

A2 A1 A0 Burst Length

0 0 0 1

0 0 1 2

0 1 0 4

0 1 1 8

1 0 0 Reserved

1 0 1 Reserved

1 1 0 Reserved

1 1 1 Full Page

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Addressing Mode Select Field (A3)

The Addressing Mode can be one of two modes, Interleave Mode or Sequential Mode.Sequential Mode supports burst length of 1, 2, 4, 8, or full page, but Interleave Mode onlysupports burst length of 4 and 8.

A3 Addressing Mode

0 Sequential

1 Interleave

--- Addressing Sequence of Sequential Mode

An internal column address is performed by increasing the address from the columnaddress which is input to the device. The internal column address is varied by the BurstLength as shown in the following table. When the value of column address, (n + m), inthe table is larger than 255, only the least significant 8 bits are effective.

Data n 0 1 2 3 4 5 6 7 - 255 256 257 -

Column Address n n+1 n+2 n+3 n+4 n+5 n+6 n+7 - n+255 n n+1 -

2 words:

Burst Length 4 words:

8 words:

Full Page: Column address is repeated until terminated.

--- Addressing Sequence of Interleave Mode

A column access is started in the input column address and is performed by invertingthe address bits in the sequence shown in the following table.

Data n Column Address Burst Length

Data 0 A7 A6 A5 A4 A3 A2 A1 A0Data 1 A7 A6 A5 A4 A3 A2 A1 A0# 4 words

Data 2 A7 A6 A5 A4 A3 A2 A1# A0

Data 3 A7 A6 A5 A4 A3 A2 A1# A0# 8 words

Data 4 A7 A6 A5 A4 A3 A2# A1 A0

Data 5 A7 A6 A5 A4 A3 A2# A1 A0#

Data 6 A7 A6 A5 A4 A3 A2# A1# A0

Data 7 A7 A6 A5 A4 A3 A2# A1# A0#

CAS# Latency Field (A6~A4)

This field specifies the number of clock cycles from the assertion of the Read command tothe first read data. The minimum whole value of CAS# Latency depends on the frequencyof CLK. The minimum whole value satisfying the following formula must be programmed

into this field. tCAC(min) CAS# Latency X tCK

A6 A5 A4 CAS# Latency

0 0 0 Reserved

0 0 1 1 clock

0 1 0 2 clocks

0 1 1 3 clocks

1 X X Reserved

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E t r o n T ec h 1M x 16 SDRAM EM636165 Test Mode field (A8~A7)

These two bits are used to enter the test mode and must be programmed to "00" in normaloperation.

A8 A7 Test Mode

0 0 normal mode

0 1 Vendor Use Only

1 X Vendor Use Only

Single Write Mode (A9)

This bit is used to select the write mode. When the BS bit is "0", the Burst-Read-Burst-Write mode is selected. When the BS bit is "1", the Burst-Read-Single-Write mode isselected.

A9 Single Write Mode

0 Burst-Read-Burst-Write

1 Burst-Read-Single-Write

Note: A10 and A11 should stay L during mode set cycle.

8 No-Operation command

(RAS# = "H", CAS# = "H", WE# = "H")

The No-Operation command is used to perform a NOP to the SDRAM which is selected (CS#

is Low). This prevents unwanted commands from being registered during idle or wait states.

9 Burst Stop command

(RAS# = "H", CAS# = "H", WE# = "L")The Burst Stop command is used to terminate either fixed-length or full-page bursts. This

command is only effective in a read/write burst without the auto precharge function. The terminatedread burst ends after a delay equal to the CAS# latency (refer to the following figure). Thetermination of a write burst is shown in the following figure.

CLK

COMMAND

T0 T 1 T2 T3 T4 T5 T6 T7 T8

READ A NOP NOP NOP NOP NOP NOPNOP Burst Stop

DOUT A0 DOUT A1 DOUT A2 DOUT A3CAS# latency=1

tCK1, DQ's

CAS# latency=2

tCK2, DQ's

CAS# latency=3

tCK3, DQ's



The burst ends after a delay equal to the CAS# latency.

Termination of a Burst Read Operation (Burst Length 4, CAS# Latency = 1, 2, 3)

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E t r o n T ec h 1M x 16 SDRAM EM63616514 Clock Suspend Mode Entry / PowerDown Mode Entry command (refer to Figures 6, 7, and 8 in

Timing Waveforms)

(CKE = "L")When the SDRAM is operating the burst cycle, the internal CLK is suspended(masked) from the

subsequent cycle by issuing this command (asserting CKE "LOW"). The device operation is held

intact while CLK is suspended. On the other hand, when both banks are in the idle state, thiscommand performs entry into the PowerDown mode. All input and output buffers (except the CKEbuffer) are turned off in the PowerDown mode. The device may not remain in the Clock Suspend orPowerDown state longer than the refresh period (64ms) since the command does not perform anyrefresh operations.

15 Clock Suspend Mode Exit / PowerDown Mode Exit command (refer to Figures 6, 7, and 8 in TimingWaveforms, CKE= "H")

When the internal CLK has been suspended, the operation of the internal CLK is reinitiatedfrom the subsequent cycle by providing this command (asserting CKE "HIGH"). When the device isin the PowerDown mode, the device exits this mode and all disabled buffers are turned on to theactive state. tPDE(min.) is required when the device exits from the PowerDown mode. Anysubsequent commands can be issued after one clock cycle from the end of this command.

16 Data Write / Output Enable, Data Mask / Output Disable command (LDQM/UDQM = "L", "H")

During a write cycle, the LDQM/UDQM signal functions as a Data Mask and can control everyword of the input data. During a read cycle, the LDQM/UDQM functions as the controller of outputbuffers. LDQM/UDQM is also used for device selection, byte selection and bus control in a memorysystem. LDQM controls DQ0 to DQ7, UDQM controls DQ8 to DQ15.

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E t r o n T ec h 1M x 16 SDRAM EM636165Absolute Maximum Rating

Symbol Item Rating Unit Note

-5/55/6/7/7L/8/10 -10I

VIN, VOUT Input, Output Voltage - 1.0 ~ 4.6 V 1

VDD, VDDQ Power Supply Voltage -1.0 ~ 4.6 V 1

TOPR Operating Temperature 0 ~ 70 -40 ~ 85 C 1

TSTG Storage Temperature - 55 ~ 125 C 1

PD Power Dissipation 1 0.6 W 1

IOUT Short Circuit Output Current 50 mA 1

Recommended D.C. Operating Conditions (Ta = -40~85C)

Symbol Parameter Min. Typ. Max. Unit Note

VDD Power Supply Voltage 3.0 3.3 3.6 V 2

VDDQ Power Supply Voltage(for I/O Buffer) 3.0 3.3 3.6 V 2VIH LVTTL Input High Voltage 2.0 VDDQ+0.3 V 2

VIL LVTTL Input Low Voltage - 0.3 0.8 V 2

Capacitance (VDD = 3.3V, f = 1MHz, Ta = 25C)

Symbol Parameter Min. Max. Unit

CI Input Capacitance 2 5 pF

CI/O Input/Output Capacitance 4 7 pF

Note: These parameters are periodically sampled and are not 100% tested.

Recommended D.C. Operating Conditions (VDD = 3.3V 0.3V)1. Ta = 0~70C

- 5/55/6/7/8/10 - 7LDescription/Test condition Symbol

Max. Unit Note

Operating Current

tRC tRC(min), Outputs Open, Inputsignal one transition per one cycle

1 bankoperation IDD1

130/125/115/100/95 /85 40 3

Precharge Standby Current in non-power down mode

tCK = tCK(min), CS# VIH, CKE = VIHInput signals are changed once during 30ns.

IDD2N115/110/90/85/75/60 15 3

Precharge Standby Current in power down mode

tCK = tCK(min), CKE VIL(max) IDD2P2 0.8

3Precharge Standby Current in power down mode

tCK = - CKE VIL(max) IDD2PS2 0.8

Active Standby Current in power down mode

CKE VIL(max), tCK = tCK(min) IDD3P2 1.5

mA

3

Active Standby Current in non-power down mode

CKE VIH(min), tCK = tCK(min) IDD3N105/100/90/80/70/55 20

Operating Current (Burst mode)tCK=tCK(min), Outputs Open, Multi-bank interleave,gapless data IDD4

165/160/150/140/130/115 40 3, 4

Refresh Current

tRC tRC(min) IDD5115/110/100/90/90 /80 40 3

Self Refresh Current

VIH VDD - 0.2, 0V VIL 0.2V IDD62 0.5

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E t r o n T ec h 1M x 16 SDRAM EM6361652. Industrial Operating temperature : Ta = -40~85C

EM636165-10IDescription/Test condition Symbol

Max. Unit Note

Operating Current

tRC tRC(min), Outputs Open, Input

signal one transition per one cycle

1 bank operation IDD1 80 3

Precharge Standby Current in non-power down mode

tCK = tCK(min), CS# VIH, CKE = VIHInput signals are changed once during 30ns.

IDD2N 35 3


tCK = tCK(min), CKE VIL(max)IDD2P 3 3


tCK = - CKE VIL(max)IDD2PS 2 mA

Active Standby Current in power down mode

CKE VIL(max), tCK = tCK(min)IDD3P 7 3

Active Standby Current in non-power down mode

CKE VIH(min), tCK = tCK(min)IDD3N 51

Operating Current (Burst mode)tCK=tCK(min), Outputs Open, Multi-bank interleave,gapless data IDD4 100 3, 4

Refresh Current

tRC tRC(min)IDD5 80 3

Self Refresh Current

VIH VDD - 0.2, 0V VIL 0.2V IDD6 2

Parameter Description Min. Max. Unit Note

IIL Input Leakage Current

( 0V VIN VDD, All other pins not under test = 0V )- 10 10 A

IOL Output Leakage CurrentOutput disable, 0V VOUT VDDQ)

- 10 10 A

VOH LVTTL Output "H" Level Voltage( IOUT = -2mA )

2.4 V

VOL LVTTL Output "L" Level Voltage( IOUT = 2mA )

0.4 V

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Electrical Characteristics and Recommended A.C. Operating Conditions(VDD = 3.3V 0.3V, Ta = -40~85C) (Note: 5, 6, 7, 8)

- 5/55/6/7/7L/8/10Symbol A.C. Parameter

Min. Max. Unit NotetRC Row cycle time

(same bank)48/48/54/63/63/72/90 9

tRCD RAS# to CAS# delay

(same bank)15/16/16/16/16/16/30 9

tRP Precharge to refresh/row activatecommand (same bank)

15/16/16/16/16/16/30 ns 9

tRRD Row activate to row activate delay

(different banks)10/11/12/14/14/16/20 9

tRAS Row activate to precharge time

(same bank)30/32/36/42/42/48/60 100,000

tWR Write recovery time 1 Cycle

tCK1 CL* = 1 -/19/20/20/20/20/30

tCK2 Clock cycle time CL* = 2 -/7/7.5/8/8/8/15 10

tCK3 CL* = 3 5/5.5/6/7/7/8/10

tCH Clock high time 2/2/2/2.5/2.5/3/3.5 ns 11

tCL Clock low time 2/2/2/2.5/2.5/3/3.5 11

tAC1 Access time from CLK CL* = 1 -/7/8/13/13/18/27

tAC2 (positive edge) CL* = 2 -/5.5/6/6.5/6.5/7/12 11

tAC3 CL* = 3 4.5/5/5/5.5/5.5/6.5/7.5

tCCD CAS# to CAS# Delay time 1 Cycle

tOH Data output hold time 1.8/2/2/2/2/2/3 10

tLZ Data output low impedance 1/1/1/1/1/2/2

tHZ Data output high impedance 3/3.5/4/5/5/6/8 8

tIS Data/Address/Control Input set-up time 2/2/2/2/2/2.5/3 ns 11

tIH Data/Address/Control Input hold time 1 11

tPDE PowerDown Exit set-up time 5/5.5/6/7/7/8/10

tREF Refresh time 64 ms

+

CL is CAS# Latency.

Note:

1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to thedevice.

2. All voltages are referenced to VSS.VIH(Max)=4.6 for pulse width5ns.VIL(Min)=-1.5Vfor pulse width5ns.

3. These parameters depend on the cycle rate and these values are measured by the cycle rate under theminimum value of tCK and tRC. Input signals are changed one time during tCK.

4. These parameters depend on the output loading. Specified values are obtained with the output open.

5. Power-up sequence is described in Note 10.

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6. A.C. Test Conditions

LVTTL Interface

Reference Level of Output Signals 1.4V / 1.4V

Output Load Reference to the Under Output Load (B)

Input Signal Levels 2.4V / 0.4V

Transition Time (Rise and Fall) of Input Signals 1ns

Reference Level of Input Signals 1.4V

3.3V

1.2k

87 030pF

Output

1.4V

50

Output

30pF

50Z0=

LVTTL D.C. Test Load (A) LVTTL A.C. Test Load (B)

7. Transition times are measured between VIH and VIL. Transition(rise and fall) of input signals are in a fixedslope (1 ns).

8. tHZ defines the time in which the outputs achieve the open circuit condition and are not at reference levels.

9. These parameters account for the number of clock cycle and depend on the operating frequency of the

clock as follows:

the number of clock cycles = specified value of timing/Clock cycle time

(count fractions as a whole number)

10.If clock rising time is longer than 1 ns, ( tR / 2 -0.5) ns should be added to the parameter.

11.Assumed input rise and fall time tT ( tR & tF ) = 1 ns

If tR or tF is longer than 1 ns, transient time compensation should be considered, i.e.,

12. Power up Sequence

Power up must be performed in the following sequence.

1) Power must be applied to VDD and VDDQ(simultaneously) when all input signals are held "NOP" state

and both CKE = "H" and LDQM/UDQM = "H." The CLK signals must be started at the same time.

2) After power-up, a pause of 200seconds minimum is required. Then, it is recommended that

LDQM/UDQM is held "HIGH" (VDD levels) to ensure DQ output is in high impedance.

3) Both banks must be precharged.

4) Mode Register Set command must be asserted to initialize the Mode register.

5) A minimum of 2 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of the

device.

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Timing Waveforms

Figure 1. AC Parameters for Write Timing (Burst Length=4, CAS# Latency=2)

A11

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

tCH tCL tCK2

t IS

tIS tIH

Begin AutoPrechargeBank A

Begin AutoPrechargeBank B

t IS

tIH

tIS

RAx RBx

RBx CAx RBx CBx RAy

RAy

CAy

RAz

RAz RBy

RBy

tRCD tDALtRC tIS tIH

tWR tRP tRRD

Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3 Ay0 Ay1 Ay2 Ay3

ActivateCommand

Bank A

Write withAutoPrecharge

CommandBank A

ActivateCommand

Bank B

Write withAutoPrecharge

CommandBank B

ActivateCommand

Bank A

WriteCommand

Bank A

PrechargeCommand

Bank A

ActivateCommandBank A

ActivateCommand

Bank B

CLK

CKE

CS#

RAS#

CAS#

WE#

A10

A0-A9

DQM

DQ

Hi-Z

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Figure 2. AC Parameters for Read Timing (Burst Length=2, CAS# Latency=2)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13

CLK

CKE

CS#

RAS#

CAS#

WE#

A11

A10

A0-A9

DQM

DQ

tCH tCL tCK2

t IS

t IS

tIH


tIH

tIH

tIS

RAx

RAx CAx RBx

RBx

CBx

RAy

RAy

tRRDtRAS

tRC

tRCDtAC2tLZ

tOH

tHZ

Ax0 Ax1 Bx0 Bx1

tRP

ActivateCommand

Bank A

ReadCommand

Bank A

ActivateCommand

Bank B

Read withAuto Precharge

CommandBank B

PrechargeCommand

Bank A

ActivateCommand

Bank A

Hi-Z

tAC2

tHZ

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Figure 3. Auto Refresh (CBR) (Burst Length=4, CAS# Latency=2)


CLK

CKE

CS#

RAS#

CAS#

WE#

A11

A10

A0-A9

DQM

DQ

tCK2

RAx

RAx

tRP tRC

Ax0 Ax1 Ax2

PrechargeAllCommand

AutoRefreshCommand

AutoRefreshCommand

ActivateCommand

Bank A

ReadCommand

Bank A

tRC

Ax3

CAx

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Figure 4. Power on Sequene and Auto Refresh (CBR)


CLK

CKE

CS#

RAS#

CAS#

WE#

BS

A10

A0-A9

DQM

DQ

tCK2

High level

is reauiredMinimum of 2 Refresh Cycles are required

Hi-ZtRP tRC

Address Key

Inputs must bestable for 200s

PrechargeALLCommand

1st AutoRefreshCommand

2nd Auto RefreshCommand

Mode RegisterSet Command

AnyCommand

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Figure 5. Self Refresh Entry & Exit Cycle

CLK

CKE

CS#

RAS#

CAS#

A11

A0-A9

WE#

DQM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19

DQ

*Note 1

*Note 2

tIS

*Note 3

*Note 4 tRC(min) *Note 7

*Note 5

*Note 6

*Note 8*Note 8

Hi-Z Hi-Z

Self Refresh Enter SelfRefresh Exit AutoRefresh

tSRXtPDE

Note: To Enter SelfRefresh Mode

1. CS#, RAS# & CAS# with CKE should be low at the same clock cycle.2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.3. The device remains in SelfRefresh mode as long as CKE stays "low".

Once the device enters SelfRefresh mode, minimum tRAS is required before exit from SelfRefresh.

To Exit SelfRefresh Mode1. System clock restart and be stable before returning CKE high.2. Enable CKE and CKE should be set high for minimum time of tSRX.3. CS# starts from high.4. Minimum tRC is required after CKE going high to complete SelfRefresh exit.5. 2048 cycles of burst AutoRefresh is required before SelfRefresh entry and after SelfRefresh exit if the

system uses burst refresh.

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Figure 6.1. Clock Suspension During Burst Read (Using CKE)(Burst Length=4, CAS# Latency=1)

T0 T 1 T2 T3 T4 T5 T6 T8 T9 T10 T11 T13 T14 T15 T16 T17 T19 T20 T21 T22

CLK

CKE

CS#

RAS#

CAS#

WE#

A11

A10

A0-A9

DQM

DQ

tCK1

RAx

RAx CAx

Hi-ZAx0 Ax1 Ax2 Ax3

ActivateCommand

Bank ARead

CommandBank A

Clock Suspend1 Cycle

Clock Suspend2 Cycles


tHZ

T7 T12 T18

Note: CKE to CLK disable/enable = 1 clock

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CLK

CKE

CS#

RAS#

CAS#

WE#

A11

A10

A0-A9

DQM

DQ

tCK2

RAx

RAx CAx

Hi-ZAx0 Ax1 Ax2 Ax3

ActivateCommand

Bank A

ReadCommand

Bank A




tHZ


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T0 T 1 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

CKE

CS#

RAS#

CAS#

WE#

A11

A10

A0-A9

DQM

DQ

tCK3

RAx

RAx CAx

Hi-ZAx0 Ax1 Ax2 Ax3

ActivateCommand

Bank A

ReadCommand

Bank A




tHZ

T 2


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Figure 7.1. Clock Suspension During Burst Write (Using CKE)

(Burst Length = 4, CAS# Latency = 1)


CLK

CKE

CS#

RAS#

CAS#

WE#

A11

A10

A0-A8

DQM

DQ

tCK1

RAx

RAx CAx

Hi-ZDAx0

ActivateCommand

Bank A

WriteCommand

Bank A



DAx1 DAx2 DAx3



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Figure 7.2. Clock Suspension During Burst Write (Using CKE)(Burst Length=4, CAS# Latency=2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21

CLK

CKE

CS#

RAS#

CAS#

WE#

A11

A10

A0-A9

DQM

DQ

tCK2

RAx

RAx CAx

Hi-ZDAx0


WriteCommand

Bank A



DAx1 DAx2 DAx3


T22


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Figure 7.3. Clock Suspension During Burst Write (Using CKE)(Burst Length=4, CAS# Latency=3)


CLK

CKE

CS#

RAS#

CAS#

WE#

A11

A10

A0-A9

DQM

DQDAx1 DAx2 DAx3

tCK3

RAx

RAx CAx

Hi-Z

ActivateCommand

Bank A WriteCommand

Bank A




DAx0


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Figure 8. Power Down Mode and Clock Mask (Burst Lenght=4, CAS# Latency=2)


CLK

CKE

CS#

RAS#

CAS#

WE#

A11

A10

A0~A8

DQM

DQ

tCK2 tIS tPDE

RAx

RAx CAx

tHZ

Ax3Ax2Ax1Ax0


Power DownMode Entry

Power DownMode Exit

ReadCommand

Bank A

Clock MaskStart

Clock MaskEnd

PrechargeCommandBank A

Power DownMode Entry

PRECHARGESTANDBY

AnyCommand

Power DownMode Exit

Hi-Z

Valid

ACTIVESTANDBY

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Figure 9.1. Random Column Read (Page within same Bank)(Burst Length=4, CAS# Latency=1)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

CKE

CS#

RAS#

CAS#

WE#

A10

A0~A8

DQM

DQ

A11

tCK1

ActivateCommand

Bank A

ReadCommand

Bank A

ReadCommand

Bank A

PrechargeCommand

Bank A

Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3

RAw

RAw CAw CAx CAy

ReadCommand

Bank A

Hi-Z

CAz

Az0 Az1 Az2 Az3

ReadCommand

Bank A

ActivateCommand

Bank A

RAz

RAz

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CLK

CKE

CS#

RAS#

CAS#

WE#

A10

A0~A8

DQM

DQ

A11

tCK2

ActivateCommand

Bank A

ReadCommand

Bank A

ReadCommand

Bank A

PrechargeCommand

Bank A


RAw

RAw CAw CAx CAy

ReadCommand

Bank A

Hi-Z

CAz

Az0 Az1 Az2 Az3

ReadCommand

Bank A

ActivateCommand

Bank A

RAz

RAz

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CLK

CKE

CS#

RAS#

CAS#

WE#

A10

A0~A9

DQM

DQ

A1

1

tCK3

ActivateCommand

Bank A

ReadCommand

Bank A

ReadCommand

Bank A

PrechargeCommand

Bank A


RAw

RAw CAw CAx CAy

ReadCommand

Bank A

Hi-Z

CAz

ReadCommand

Bank A

ActivateCommand

Bank A

RAz

RAz

Az0

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Figure 10.1. Random Column Write (Page within same Bank)(Burst Length=4, CAS# Latency=1)


CLK

CKE

CS#

RAS#

CAS#

WE#

A10

A0~A9

DQM

DQ

A11

tCK1

ActivateCommand

Bank A

WriteCommand

Bank A

WriteCommand

Bank B

PrechargeCommand

Bank B

DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3

RBw

RBw CBw CBx CBy

WriteCommand

Bank B

Hi-Z

CBz

DBz0 DBz1 DBz2 DBz3

WriteCommand

Bank B

ActivateCommand

Bank B

RBz

RBz

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CLK

CKE

CS#

RAS#

CAS#

WE#

A10

A0~A8

DQM

DQ

A11

tCK2

ActivateCommand

Bank A

WriteCommand

Bank B

WriteCommand

Bank B

PrechargeCommand

Bank B


RBw

RBw CBw CBx CBy

WriteCommand

Bank B

Hi-Z

CBz

DBz0 DBz1 DBz2 DBz3

WriteCommand

Bank B

ActivateCommand

Bank B

RBz

RBz

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CLK

CKE

CS#

RAS#

CAS#

WE#

A10

A0~A9

DQM

DQ

A11

tCK3

ActivateCommand

Bank A

WriteCommand

Bank B

WriteCommand

Bank B

PrechargeCommand

Bank B


RBw

RBw CBw CBx CBy

WriteCommand

Bank B

Hi-Z

CBz

DBz0 DBz1

WriteCommand

Bank B

ActivateCommand

Bank B

RBz

RBz

DBz2

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Figure 11.1. Random Row Read (Interleaving Banks)(Burst Length=8, CAS# Latency=1)


CLK

CKE

CS#

RAS#

CAS#

WE#

A10

A0~A9

DQM

DQ

A11

tCK1

ActivateCommand

Bank B

ActivateCommand

Bank A

PrechargeCommand

Bank B

Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1

RBx

RBx RBy

ReadCommand

Bank B

Hi-Z

CBy

ReadCommand

Bank B

PrechargeCommand

Bank A

High

RAx

ReadCommand

Bank A

ActivateCommand

Bank B

By0 By1 By2Ax2 Ax3 Ax4 Ax5 Ax6 Ax7

CBx CAxRAx

RBy

tRCDtAC1 tRP

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CLK

CKE

CS#

RAS#

CAS#

WE#

A10

A0~A9

DQM

DQ

A11

tCK2

ActivateCommand

Bank B

ActivateCommand

Bank A

PrechargeCommand

Bank B


RBx

RBx RBy

ReadCommand

Bank B

Hi-Z

CBy

ReadCommand

Bank B

High

RAx

ReadCommand

Bank A

ActivateCommand

Bank B

By0 By1Ax2 Ax3 Ax4 Ax5 Ax6 Ax7

CBx CAxRAx

RBy

tRCD tAC2 tRP

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CLK

CKE

CS#

RAS#

CAS#

WE#

A10

A0~A9

DQM

DQ

A11

tCK3

ActivateCommand

Bank B

ActivateCommand

Bank A

PrechargeCommand

Bank B


RBx

RBx RBy

ReadCommand

Bank B

Hi-Z

CBy

ReadCommand

Bank B

High

RAx

ReadCommand

Bank A

ActivateCommand

Bank B

Ax7 By0Ax2 Ax3 Ax4 Ax5 Ax6

CBx CAxRAx

RBy

tRCD tAC3 tRP

PrechargeCommand

Bank A

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Figure 12.1. Random Row Write (Interleaving Banks)(Burst Length=8, CAS# Latency=1)


CLK

CKE

CS#

RAS#

CAS#

WE#

A10

A0~A9

DQM

DQ

A11

tCK1

ActivateCommand

Bank A

ActivateCommand

Bank B

PrechargeCommand

Bank A

DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1

RAx

RAx RAy

WriteCommand

Bank A

Hi-Z

CAy

High

RBx

PrechargeCommand

Bank B

DBx7 DAy3DBx2 DBx3 DBx4 DBx5 DBx6

CAx CBxRBx

RAy

tRCD

DAy0 DAy1 DAy2

WriteCommand

Bank A

WriteCommand

Bank B

ActivateCommand

Bank A

tRP tWR

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CLK

CKE

CS#

RAS#

CAS#

WE#

A10

A0~A8

DQM

DQ

A11

tCK2

ActivateCommand

Bank A

ActivateCommand

Bank BPrechargeCommand

Bank A


RAx

RAx RAy

WriteCommand

Bank A

Hi-Z

CAy

High

RBx

PrechargeCommand

Bank B

DBx7DBx2 DBx3 DBx4 DBx5 DBx6

CAx CBxRBx

RAy

tRCD

WriteCommand

Bank A

WriteCommand

Bank B

ActivateCommand

Bank A

DAy3DAy0 DAy1 DAy2 DAy4

tWR* tRP tWR*

* tWR > tWR(min.)

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CLK

CKE

CS#

RAS#

CAS#

WE#

A10

A0~A9

DQM

DQ

A11

tCK3

ActivateCommand

Bank A

ActivateCommand

Bank B

PrechargeCommand

Bank A


RAx

RAx RAy

WriteCommand

Bank A

Hi-Z

CAy

High

RBx

PrechargeCommand

Bank B

DBx7DBx2 DBx3 DBx4 DBx5 DBx6

CAx CBxRBx

RAy

tRCD

WriteCommand

Bank A

WriteCommand

Bank B

ActivateCommand

Bank A

DAy3DAy0 DAy1 DAy2

tWR* tRP tWR*

* tWR > tWR(min.)

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Figure 13.1. Read and Write Cycle (Burst Length=4, CAS# Latency=1)


CLK

CKE

CS#

RAS#

CAS#

WE#

A10

A0~A9

DQM

DQ

A11

tCK1

ActivateCommand

Bank A

The Write Datais Masked with a

Zero ClockLatency

ReadCommand

Bank A

Ax0 Ax1 Ax2 Ax3 DAy0 DAy1Hi-Z

PrechargeCommand

Bank B

Az3DAy3 Az0 Az1

ReadCommand

Bank A

WriteCommand

Bank A

The Read Datais Masked with a

Two ClockLatency

RAx

RAx CAx CAy CAz

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CLK

CKE

CS#

RAS#

CAS#

WE#

A10

A0~A9

DQM

DQ

A11

tCK2

ActivateCommand

Bank A


Zero ClockLatency

ReadCommand

Bank A


Az3DAy3 Az0 Az1

ReadCommand

Bank A

WriteCommand

Bank A


Two ClockLatency

RAx

RAx CAx CAy CAz

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CLK

CKE

CS#

RAS#

CAS#

WE#

A10

A0~A9

DQM

DQ

A11

tCK3

ActivateCommand

Bank A


Zero ClockLatency

ReadCommand

Bank A


Az3DAy3 Az0 Az1

ReadCommand

Bank A

WriteCommand

Bank A


Two ClockLatency

RAx

RAx CAx CAy CAz

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Figure 14.1. Interleaving Column Read Cycle (Burst Length=4, CAS# Latency=1)


CLK

CKE

CS#

RAS#

CAS#

WE#

A10

A0~A9

DQM

DQ

A11

tCK1


ReadCommand

Bank B

PrechargeCommandBank A

Bw0 Bw1 Bx0 Bx1 By1 Ay0Hi-Z

Bz0

ReadCommand

Bank A

ReadCommand

Bank A

RAx

RAx

Ax0 Ax1 Ax2 Ax3 By0 Ay1 Bz1 Bz2 Bz3

ActivateCommandBank B

ReadCommand

Bank B

ReadCommand

Bank B

ReadCommandBank B

PrechargeCommand

Bank B

tRCD tAC1

RAx RBw

RBw

CBw CBx CBy CAy CBz

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Figure 14.2. Interleaving Column Read Cycle (Burst Length=4, CAS# Latency=2)


CLK

CKE

CS#

RAS#

CAS#

WE#

A10

A0~A9

DQM

DQ

A11

tCK2

ActivateCommand

Bank A

ReadCommand

Bank B

PrechargeCommand

Bank A

Bw0 Bw1 Bx0 Bx1 By1 Ay0Hi-Z

Bz0

ReadCommand

Bank A

ReadCommand

Bank A

RAx

RAx

Ax0 Ax1 Ax2 Ax3 By0 Ay1 Bz1 Bz2 Bz3

ActivateCommand

Bank B

ReadCommand

Bank B

ReadCommand

Bank B

ReadCommand

Bank B

PrechargeCommand

Bank B

tRCD tAC2

CAy RAx

RAx

CBw CBx CBy CAy CBz

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Figure 14.3. Interleaved Column Read Cycle (Burst Length=4, CAS# Latency=3)


CLK

CKE

CS#

RAS#

CAS#

WE#

A10

A0~A9

DQM

DQ

A11

tCK3

ActivateCommand

Bank A

PrechaergeCommand

Bank B

Bx0 Bx1 By0 By1 Bz1 Ay0Hi-Z

Ay2

ReadCommand

Bank A

ReadCommand

Bank A

RAx

RAx

Ax0 Ax1 Ax2 Ax3 Bz0 Ay1 Ay3

ActivateCommand

Bank B

ReadCommand

Bank B

ReadCommand

Bank B

ReadCommand

Bank B

PrechargeCommand

Bank A

tRCD tAC3

CAx RBx

RBx

CBx CBy CBz CAy

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Figure 15.1. Interleaved Column Write Cycle (Burst Length=4, CAS# Latency=1)


CLK

CKE

CS#

RAS#

CAS#

WE#

A10

A0~A9

DQM

DQ

A11

tCK1


WriteCommand

Bank B

DBw0 DBw1 DBx0 DBx1 DBy1 DAy0Hi-Z

WriteCommand

Bank A

PrechargeCommand

Bank A

RAx

RAx

DAx0 DAx1 DAx2 DAx3 DBy0 DAy1 DBz0

ActivateCommand

Bank B

WriteCommandBank B

WriteCommandBank B

WriteCommandBank A

PrechargeCommand

Bank B

tRCD

CAx RBw

RBw

CBw CBx CBy CAy

DBz1 DBz2 DBz3

WriteCommand

Bank B

tRRD

tRP

tWR tRP

CBz

T6

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Figure 15.2. Interleaved Column Write Cycle (Burst Length=4, CAS# Latency=2)


CLK

CKE

CS#

RAS#

CAS#

A10

A0~A9

DQM

DQ

A11

tCK2

ActivateCommand

Bank A

WriteCommandBank B

DBw0 DBw1 DBx0 DBx1 DBy1 DAy0Hi-Z

WriteCommand

Bank APrechargeCommand

Bank A

RAx

RAx

DAx0 DAx1 DAx2 DAx3 DBy0 DAy1 DBz0

ActivateCommand

Bank B

WriteCommand

Bank B

WriteCommand

Bank B

WriteCommand

Bank A

PrechargeCommand

Bank B

tRCD

CAx RBw

RBw

CBw CBx CBy CAy

DBz1 DBz2 DBz3

WriteCommand

Bank B

tRRD

tRP tWR tRP

CBz

WE#

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Figure 16.1. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=1)


CLK

CKE

CS#

RAS#

CAS#

WE#

A10

A0~A9

DQM

DQ

A11

tCK1

ActivateCommand

Bank A

ActivateCommand

Bank B

Bx0 Bx1 Bx2 Bx3 Ay1 Ay2Hi-Z

ReadCommand

Bank A

RAx

RAx

RBx

Ax0 Ax1 Ax2 Ax3 Ay0 Ay3 By0

ActivateCommand

Bank B

ActivateCommand

Bank B

RBx CBx CAy RBy CBy

By1 By2 By3

RBz

High

Bz0 Bz1 Bz2 Bz3


CommandBank B


CommandBank A


CommandBank B Read with

Auto PrechargeCommand

Bank B

CAx

RBy RBz

CBz

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CLK

CKE

CS#

RAS#

CAS#

WE#

A10

A0~A9

DQM

DQ

A11

tCK2

ActivateCommand

Bank A

ActivateCommand

Bank A


ReadCommand

Bank A

RAx

RAx

RBx


ActivateCommand

Bank B

ActivateCommand

Bank B

RBx CBx RByRAy CBy

By1 By2 By3

High

Az0 Az1 Az2


CommandBank B


CommandBank A


CommandBank B


CommandBank A

CAx

RBy RAz

CAzRAz

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CLK

CKE

CS#

RAS#

CAS#

A10

A0~A9

DQM

DQ

A11

tCK3

ActivateCommand

Bank A


ReadCommand

Bank A

RAx

RAx

RBx


ActivateCommand

Bank B

ActivateCommand

Bank B

RBx CBx

By1 By2 By3

High


CommandBank B Read with


Bank A


CommandBank B

CAx

RBy

CByRByCAy

WE#

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Figure 17.1. Auto Precharge after Write Burst (Burst Length=4, CAS# Latency=1)


CLK

CKE

CS#

RAS#

CAS#

WE#

A10

A0~A9

DQM

DQ

A11

tCK1

ActivateCommand

Bank A

DBx0 DBx1 DBx2 DBx3 DAy1 DAy2Hi-Z

WriteCommand

Bank A

RAx

RAx

RBx

DAx0 DAx1 DAx2 DAx3 DAy0 DAy3 DBy0

ActivateCommand

Bank B

ActivateCommand

Bank B

CBx CAy

DBy1 DBy2 DBy3

High

Write withAuto Precharge

CommandBank B Write with


Bank A


CommandBank B

RBy

CAzCByRBy

DAz0 DAz0

ActivateCommand

Bank A


CommandBank A

DAz0 DAz0

CAx RBx

RAz

RAz

T11

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CLK

CKE

CS#

RAS#

CAS#

A10

A0~A9

DQM

DQ

A11

tCK2

ActivateCommand

Bank A


WriteCommand

Bank A

RAx

RAx

RBx


ActivateCommand

Bank B

ActivateCommand

Bank B

CBx CAy

DBy1 DBy2 DBy3

High


CommandBank B


CommandBank A


CommandBank B

RBy

CByRBy

DAz0 DAz1

ActivateCommand

Bank A


CommandBank A

DAz2 DAz3

CAx RBx CAz

RAz

RAz

WE#

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CLK

CKE

CS#

RAS#

CAS#

WE#

A9

A0~A9

DQM

DQ

A11

tCK3

ActivateCommand

Bank A


WriteCommand

Bank A

RAx

RAx

RBx


ActivateCommand

Bank B

ActivateCommand

Bank B

CBx

DBy1 DBy2 DBy3

High


CommandBank B


CommandBank A


CommandBank B

CAyCAx RBx CBy

RBy

RBy

`

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Figure 18.1. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=1)


CLK

CKE

CS#

RAS#

CAS#

WE#

A10

A0~A9

DQM

DQ

A11

ActivateCommand

Bank A

Ax Ax+1 Bx Bx+1 Bx+3 Bx+4Hi-Z

ReadCommand

Bank A

RAx

RAx

RBx

Ax+1 Ax+2 Ax-2 Ax-1 Bx+2 Bx+5

ActivateCommand

Bank B

Burst StopCommand

CBx

High

ReadCommand

Bank B

PrechargeCommand

Bank B

CAx RBx RBy

RBy

Ax Bx+6 Bx+7

The burst counter wrapsfrom the highest orderpage address back to zeroduring this time interval

Full Page burst operation does notterminate when the burst length is satisfied;the burst counter increments and continuesbursting beginning with the starting address.

ActivateCommand

Bank B

tCK1

tRRD tRP

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CLK

CKE

CS#

RAS#

CAS#

WE#

A10

A0~A9

DQM

DQ

A11

ActivateCommand

Bank A


ReadCommandBank A

RAx

RAx


ActivateCommand

Bank B

Burst StopCommand

CBx

High

ReadCommandBank B

PrechargeCommand

Bank B

RBxCAx RBy

RBy

Ax Bx+6


Full Page burst operation does notterminate when the burst length is satisfied;the burst counter increments and continuesbursting beginning with the starting address.

ActivateCommand

Bank B

tCK2

tRP

RBx

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CLK

CKE

CS#

RAS#

CAS#

WE#

A10

A0~A9

DQM

DQ

A11

ActivateCommand

Bank A


ReadCommand

Bank A

RAx

RAx


ActivateCommand

Bank B

Burst StopCommand

CBx

High

ReadCommand

Bank B

PrechargeCommand

Bank B

RBxCAx RBy

RBy

Ax


Full Page burst operation does notterminate when the burst length issatisfied; the burst counterincrements and continuesbursting beginning with thestarting address.

ActivateCommand

Bank B

tCK3

tRP

RBx

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Figure 19.2. Full Page Write Cycle (Burst Length=Full Page, CAS# Latency=2)


CLK

CKE

CS#

RAS#

CAS#

WE#

A10

A0~A9

DQM

DQ

A11

DAx+1DAx

ActivateCommand

Bank A

Hi-Z

ActivateCommand

Bank B

RAx

RAx

Burst StopCommand

CBx

High

WriteCommand

Bank B

PrechargeCommand

Bank B

RBxCAx RBy

RBy


Full Page burst operation doesnot terminate when the burstlength is satisfied; the burst counterincrements and continues burstingbeginning with the starting address.

ActivateCommand

Bank B

tCK2

DAx+2DAx+3 DAx-1 DAx DAx+1 DBx DBx+1 DBx+2 DBx+3 DBx+4 DBx+5 DBx+6

WriteCommand

Bank A

Data is ignored

RBx

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Figure 19.3. Full Page Write Cycle (Burst Length=Full Page, CAS# Latency=3)


CLK

CKE

CS#

RAS#

CAS#

WE#

A10

A0~A9

DQM

DQ

A11

DAx+1DAx

ActivateCommand

Bank A

Hi-Z

ActivateCommand

Bank B

RAx

RAx

Burst StopCommand

CBx

High

RBxCAx

WriteCommand

Bank B

PrechargeCommand

Bank B

RBy

RBy


Full Page burst operation doesnot terminate when the burstlength is satisfied; the burst counterincrements and continues burstingbeginning with the starting address.

ActivateCommand

Bank B

tCK3

RBx

DAx+2 DAx+3 DAx-1 DAx DAx+1 DBx DBx+1 DBx+2 DBx+3 DBx+4 DBx+5

WriteCommand

Bank A

Data is ignored

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Figure 20. Byte Write Operation (Burst Length=4, CAS# Latency=2)


CLK

CKE

CS#

RAS#

CAS#

WE#

A10

A0~A9

LDQM

UDQM

A11

RAx

RAx CAy

High

CAx

tCK2

CAz


ReadCommandBank A

Upper 3 Bytesare masked WriteCommandBank A

Upper 3 Bytesare masked ReadCommandBank A

Lower Byteis masked Lower Byteis masked Lower Byteis masked

Ax0 Ax1 Ax2

Ax1 Ax2 Ax3

DAy1 DAy2

DAy0 DAy1 DAy3

Az1 Az2

Az1 Az2Az0 Az3

DQ0 - DQ7

DQ8 - DQ15

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Figure 21. Random Row Read (Interleaving Banks)

(Burst Length=2, CAS# Latency=1)


CLK

CKE

CS#

RAS#

CAS#

WE#

A10

A0~A8

DQM

DQ

A11

High

tCK1

Bu0 Bu1 Au0 Au1 Bv0 Bv1 Av0 Av1 Bw0 Bw1 Aw0 Aw1 Bx0 Bx1 Ax0 Ax1 By0 By1 Ay0 Ay1 Bz0

ActivateCommand

Bank B

ReadBank B

with AutoPrecharge

ActivateCommand

Bank A

ReadBank A

with AutoPrecharge

ActivateCommand

Bank B

ReadBank B

with AutoPrecharge

ActivateCommand

Bank A

ReadBank A

with AutoPrecharge

ActivateCommand

Bank B

ReadBank B

with AutoPrecharge

ActivateCommand

Bank A

ReadBank A

with AutoPrecharge

ActivateCommand

Bank B

ReadBank B

with AutoPrecharge

ActivateCommand

Bank A

ReadBank A

with AutoPrecharge

ActivateCommand

Bank B

ReadBank B

with AutoPrecharge

ActivateCommand

Bank A

ReadBank A

with AutoPrecharge

ActivateCommand

Bank B

ReadBank B

with AutoPrecharge


RBu

RBu CBu

RAu

RAu CAu

RBv

RBv CBv

RAv

RAv CAv

RBw

RBw CBw

RAw

RAw CAw

RBx

RBx CBx

RAx

RAx CAx

RBy

RBy CBy

RAy

RAy CAy

RBz

RBz CBz

RAz

RAz

tRP tRP tRP tRP tRP tRP tRP tRP tRP tRP

Begin AutoPrecharge

Bank B

Begin AutoPrecharge

Bank A


Begin AutoPrecharge

Bank A


Begin AutoPrecharge

Bank A


Begin AutoPrecharge

Bank A


Begin AutoPrecharge

Bank A

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Figure 22. Full Page Random Column Read (Burst Length=Full Page, CAS# Latency=2)


CLK

CKE

CS#

RAS#

CAS#

WE#

A10

A0~A8

DQM

DQ

A11

tCK2

Ax0 Bx0 Ay0 Ay1 By0 By1 Az0 Az1 Az2 Bz0 Bz1 Bz2


ReadCommandBank A

ActivateCommand

Bank B

ReadCommandBank B

ReadCommand

Bank B

ReadCommand

Bank A

ReadCommandBank B

PrechargeCommand Bank B

(Precharge Temination)

tRP

ReadCommand

Bank A

ActivateCommandBank B

tRRD tRCD

RAx

RAx

RBx

RBx CAx CBx CAy CBy CAz CBz

RBw

RBw

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Figure 23. Full Page Random Column Write (Burst Length=Full Page, CAS# Latency=2)


CLK

CKE

CS#

RAS#

CAS#

WE#

A10

A0~A9

DQM

DQ

A11

tCK2

DAx0 DBx0 DAy0 DAy1 DBy0 DBy1 DAz0 DAz1 DAz2 DBz0 DBz1 DBz2

ActivateCommand

Bank AWrite

CommandBank A

ActivateCommand

Bank B

WriteCommand

Bank B

WriteCommand

Bank B

WriteCommand

Bank A

WriteCommand

Bank B

PrechargeCommand Bank B

(Precharge Temination)

tRP

WriteCommand

Bank A

ActivateCommand

Bank B

tRRD tRCD

RAx

RAx

RBx

RBx CAx CBx CAy CBy CAz CBz

RBw

RBw

tWR

Write Datais masked

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Figure 24.1. Precharge Termination of a Burst (Burst Length=Full Page, CAS# Latency=1)


CLK

CKE

CS#

RAS#

CAS#

WE#

A10

A0~A9

DQM

DQ

A11

tCK1

DAx0 DAx1 DAx2 DAx3 DAx4 Ay0 Ay1 Ay2 DAz3DAz2DAz0

ActivateCommand

Bank AWrite

CommandBank A

PrechargeCommand

Bank A

ReadCommand

Bank A

PrechargeCommand

Bank A

WriteCommand

Bank A

RAx

RAx

RAy

CAx RAy CAy RAz

DAz1 DAz4 DAz5 DAz6 DAz7

Precharge Terminationof a Write Burst.

Write data is masked.Activate

CommandBank A

ActivateCommand

Bank A

tWR tRP tRP PrechargeTermination ofa Read Burst.

RAz

CAz

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Figure 24.2. Precharge Termination of a Burst(Burst Length=8 or Full Page, CAS# Latency=2)


CLK

CKE

CS#

RAS#

CAS#

WE#

A10

A0~A8

DQM

DQ

A11

tCK2

DAx0 DAx1 DAx2 DAx3 Ay2Ay0 Ay1

ActivateCommand

Bank A

WriteCommand

Bank A

PrechargeCommand

Bank A

ReadCommand

Bank A

PrechargeCommand

Bank A

ActivateCommand

Bank A

RAx

RAx

RAy

CAx RAy CAy

Az0 Az1 Az2

Precharge Terminationof a Write Burst.

Write data is masked.

ActivateCommand

Bank A

tWR tRP tRP

RAz

CAz

High

ReadCommand

Bank A

PrechargeCommand

Bank A

Precharge Terminationof a Read Burst

tRPRAz

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Figure 24.3. Precharge Termination of a Burst(Burst Length=4, 8 or Full Page, CAS# Latency=3)


CLK

CKE

CS#

RAS#

CAS#

WE#

A10

A0~A9

DQM

DQ

A11

tCK3

DAx0 Ay0 Ay1 Ay2

ActivateCommand

Bank A

WriteCommand

Bank A

Precharge Terminationof a Write Burst

ReadCommand

Bank A

PrechargeCommand

Bank A

RAx

RAx

RAy

CAx RAy CAy

Write Datais masked

ActivateCommand

Bank A

tWR tRP tRP

RAz

RAz

High

ActivateCommand

Bank A

PrechargeCommand

Bank A

Precharge Terminationof a Read Burst

DAx1

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50 Pin TSOP II Package Outline Drawing Information

y

50

1D

E HE

0.2

54

L

L1

A

A1

A2

S B e L L1

C

25

26

Symbol Dimension in inch Dimension in mm

Min Normal Max Min Normal Max

A 0.048 1.20

A1 0.002 0.005 0.008 0.05 0.125 0.20

A2 0.037 0.042 0.94 1.07

B 0.012 0.015 0.018 0.3 0.375 0.45

c 0.006 0.155

D 0.82 0.825 0.83 20.82 20.95 21.08

E 0.395 0.400 0.405 10.03 10.16 10.29

e 0.031 0.80

HE 0.455 0.463 0.471 11.56 11.76 11.96L 0.016 0.020 0.024 0.40 0.50 0.60

L1 0.0315 0.80

S 0.035 0.88

y 0.004 0.10

0 5 0 5Notes :

1. Dimension D&E do not include interiead flash.2. Dimension B does not include dambar protrusion/intrusion.3. Dimension S includes end flash.4. Controlling dimension : mm

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]

7 6 5 4 3 21 2 3 4 5 6

TOP V IEWA 1 C O R N E R

BOTTOM VIEW

= 0.300.16

0.08

M

M C

C A B

A 1 C O R N E R

0.65

3.90

A

B

0.10(4X)

SEAT IN G PL AN E0.10

17

J

K

L

M

N

P

R

J

K

L

M

N

P

R

C

C

1Mx16 SDRAM Pack age Diagrams

60-Ball (6.4m m x 10.1mm )VFBGA

Units in m m

C

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This datasheet has been downloaded from:

www.DatasheetCatalog.com

Datasheets for electronic components.
http://www.datasheetcatalog.com/http://www.datasheetcatalog.com/

Documents

Em636165