Embedded Microcontroller

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EMBEDDED MICROCONTROLLER – P89C51RD2

Bluetooth Based Temperature Control system is implemented by using

P89C51RD2 microcontroller, which is the 8-bit microcontroller developed by Philips.

89C51 Microcontroller:

The microcontroller used here is P89C51RD2BN.The expansion of the part

number of this microcontroller is given below.

The P89C51RD2BN contains a non-volatile 64KB Flash program memory that is both

parallel programmable and serial In-System and In-Application Programmable. In-System

Programming (ISP) allows the user to download new code while the microcontroller sits in the

application. In-Application Programming (IAP) means that the microcontroller fetches new program code and reprograms itself while in the system. This allows for remote programming

over a modem link. A default serial loader (boot loader) program in ROM allows serial In-

System programming of the Flash memory via the UART without the need for a loader in the

Flash code. For In-Application Programming, the user program erases and reprograms the Flash

memory by use of standard routines contained in ROM.

The device supports 6-clock/12-clock mode selection by programming a Flash bit using

parallel programming or In-System Programming. In addition, an SFR bit (X2) in the clock

control register (CKCON) also selects between 6-clock/12-clock mode. Additionally, when in 6-

clock mode, peripherals may use either 6 clocks per machine cycle or 12 clocks per machine

cycle. This choice is available individually for each peripheral and is selected by bits in the

CKCON register. This device is a Single-Chip 8-Bit Microcontroller manufactured in an

advanced CMOS process and is a derivative of the 80C51 microcontroller family. The



instruction set is 100% compatible with the 80C51 instruction set. The device also has four 8-bit

I/O ports, three 16-bit timer/event counters, a multi-source, four-priority-level, nested interrupt

structure, an enhanced UART and on-chip oscillator and timing circuits. The added features of

the P89C51RD2BN make it a powerful microcontroller for applications that require pulse width

modulation, high-speed I/O and up/down counting capabilities such as motor control.

When the 89C51 microcontroller is connected to a crystal oscillator and is powered up,

we can observe the frequency on the XTAL2 pins using the oscilloscope.

CPU clock cycles

The time to execute the instruction is calculated by using the following expression,

MC Number of Machine Cycles for an instruction to execute and Cn is the number of clock cycles for one machine cycle. For 89C51RD2BN the number of clock cycles for one

machine cycle is 12. For example, If the number of machine cycles to execute a instruction is 1and the oscillator frequency used is 11.0592MHz, the time to execute an instruction is 1.085s.

Basic Features of 89C51

80C51 Central Processing Unit

On-chip Flash Program Memory with In-System Programming (ISP)

In Application Programming (IAP) capability

Boot ROM contains low-level Flash programming routines for downloading via

the UART

Supports 6-clock/12-clock mode via parallel programmer (default clock mode

after Chip Erase is 12-clock

6-clock/12-clock mode Flash bit erasable and programmable via

ISP

6-clock/12-clock mode programmable “on-the-fly” by SFR bit

State State

2

State

3

State

4

State

5

State

6One

Machine

C cle

Oscillator

Frequency f

P2 P2 P2 P1P2P2 P2P2 P1P1 P1P1 P1 P1

T (inst) = (MC Cn) / (cr stal fre uenc )



Peripherals (PCA, timers, UART) may use either 6-clock or 12-clock mode while

the CPU is in 6-clock mode

Speed up to 20 MHz with 6-clock cycles per machine cycle (40 MHz equivalent

performance); up to 33 MHz with 12 clocks per machine cycle

Fully static operation

RAM expandable externally to 64-kilo bytes

Four interrupt priority levels

Seven interrupt sources

Four 8-bit I/O ports

Full-duplex enhanced UART

Framing error detection

Automatic address recognition

Power control modes

Clock can be stopped and resumed

Idle mode

Power down mode

Programmable clock-out pin

Second DPTR register

Asynchronous port reset

Low EMI (inhibit ALE)

Programmable Counter Array (PCA)

PWM

Capture/compare

Pin Description

Examining the following figure, note that of the 40 pins a total of 32 pins are set aside for

the four ports P0, P1, P2 and P3, where each port takes 8 pins. The rest of the pins are

designated as Vcc, GND, XTAL1, XTAL2, RST, EA, ALE, and PSEN. Of these 8 pins, all 8051





Pin 6: CEX2 (P1.5) - External I/O for PCA module 2



9: RST (Reset Signal): High logical state on this input halts the MCU and clears all the

registers. Bringing this pin back to logical state zero starts the program a new as if the power had

just been turned on. In another words, positive voltage impulse on this pin resets the MCU.

Depending on the device's purpose and environs, this pin is usually connected to the push-button,

reset-upon-start circuit or a brown out reset circuit.

10-17: P3.0 to P3.7 (Port 3): As with Port 1, each of these pins can be used as universal input or

output. However, each pin of Port 3 has an alternative function:

Pin 10: RxD(P3,0) - Serial input for asynchronous communication

Pin 11: TxD(P3.1) - Serial output for asynchronous communication

Pin 12: INT0(P3.2) - Input for interrupt 0

Pin 13: INT1(P3.3) - Input for interrupt 1

Pin 14: T0(P3.4) - Clock input of counter 0

Pin 15: T1(P3.5) - Clock input of counter 1

Pin 16: WR(P3.6) - Signal for writing to external RAM memory

Pin 17: RD(P3.7) - Signal for reading from external RAM memory

18-19: XTAL2 and XTAL1 (Crystal input and output): Input and output of internal oscillator.

Quartz crystal controlling the frequency commonly connects to these pins.

20: VSS: Ground

21- 28: P2.0 to P2.7 (Port 2): If external memory is not present, pins of Port 2 act as universalinput/output. If external memory is connected, this is the location of the higher address byte, i.e.

addresses A8 – A15. It is important to note that in cases when not all the 8 bits are used for

addressing the memory (i.e. memory is smaller than 64kB), the rest of the unused bits are not

available as input/output.



29: PSEN (Program Store Enable): MCU activates this bit (brings to low state) upon each

reading of byte instruction from program memory. If external ROM is used for storing the

program, PSEN is directly connected to its control pins.

30: ALE (Address Latch Enable): Before each reading of the external memory, MCU sends

the lower byte of the address register (addresses A0 – A7) to port P0 ,and activates the output

ALE. External Chip (eg: 74HC373), memorizes the state of port P0 upon receiving a signal from

ALE pin, and uses it as part of the address for memory chip. During the second part of the MCU

cycle, signal on ALE is off, and port P0 is used as Data Bus. In this way, by adding only one

integrated circuit, data from port can be multiplexed and the port simultaneously used for

transferring both addresses and data.

31: EA (External Access Enable): Bringing this pin to the logical state zero designates the

ports P2 and P3 for transferring addresses regardless of the presence of the internal memory.

This means that even if there is a program loaded in the MCU it will not be executed, but the one

from the external ROM will be used instead. Conversely, bringing the pin to the high logical

state causes the controller to use both memories, first the internal, and then the external (if

present).

32-39: P0.7 to P0.0 (Port 0): Similar to Port 2, pins of Port 0 can be used as universalinput/output, if external memory is not used. If external memory is used, P0 behaves as address

output (A0 – A7) when ALE pin is at high logical level, or as data output (Data Bus) when ALE

pin is at low logical level.

40: VCC: Power +5V

Architecture of 89C51 Microcontroller

The architecture of the 8051 family of microcontrollers (8051 derivatives) is referred to

as the MCS-51 architecture (Micro Controller Series – 51), or sometimes simply as MCS-51.

The block diagram of 89C51 microcontroller is shown below.



Architecture of 89C51 microcontroller

ACCUMULATOR (ACC): Accumulator is a general-purpose register, which stores runtime

results. Before performing any operation upon an operand, operand has to be stored in the

accumulator. Results of arithmetical operations are also stored in the accumulator. When

transferring data from one register to another, it has to go through the accumulator. Due to its

versatile role, this is the most frequently used register, essential part of every MCU.





P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

T2

T2EX

ECI

CEX0

CEX1

CEX2

CEX3

CEX4

Serial input

Serial output

External interrupt 0


Timer 0 external input


Signal write to external memory

Signal read from external memory

Port 2 (P2): When using external memory, this port contains the higher address byte (addresses

A8 – A15), similar to Port 0. Otherwise, it can be used as universal I/O port.

Port 3 (P3): Beside its role as universal I/O port, each pin of Port 3 has an alternate function. In

order to use one of these functions, the pin in question has to be designated as input, i.e. the

appropriate bit of register P3 needs to be set. By selecting one of the functions the other one is

disabled. From a hardware standpoint, Port 3 is similar to Port 0. The alternate functions of Port

3 is given below

Pin Alternate Name Alternate Function

P3.0

P3.1

P3.2

P3.3

P3.4

P3.5

P3.6

P3.7

RXD

TXD

INT0

INT1

T0

T1

WR

RD

Serial input

Serial output





Signal write to external memory

Signal read from external memory

Data Pointer (DPTR) : The Data pointer register is made up of two 8 bit registers, named DPH

(Data Pointer High) and DPL (Data Pointer Low). These registers are used to give addresses of

the internal or external memory. The DPTR is under the control of program. DPTR is also



manipulated as one 16 bit register, DPH & DPL are each assigned an address. The 89C51

microcontroller has additional DPTR. The dual DPTR structure is a way by which the chip will

specify the address of an external data memory location. There are two 16-bit DPTR registers

that address the external memory, and a single bit called DPS (bit0 in AUXR1) that allows the

program code to switch between them.

Stack Pointer (SP) : The stack refers to an area of internal RAM that is used in conjunction with

certain opcodes to store and retrieve data quickly. The register used to access the stack is called

Stack Pointer. The 8 bit stack pointer register is used by the 89C51 to hold an internal RAM

address that is called then top of the stack. The stack pointer increments before storing the data

on the stack. As retrieved from the stack the SP is decremented by one. The number in Stack

Pointer points to the location of the last "valid" address within the Stack. With the beginning of

every new routine, Stack Pointer increases by 1; upon return from routine, SP decreases by 1.

Upon reset (or turning the power on), the stack pointer contains the value 07h.

Program Counter (PC): Used to access code memory. Program counter always points to the

address of the next instruction in memory to be executed. Upon reset (or turning the power on),

the program counter resets to the starting location of the program.

Instruction Register: When an instruction is fetched from the Flash memory, it is loaded in the

instruction register.

Timing & Control unit: The timing and control unit synchronizes the operation of the

microcontroller and generates control signals necessary for communication between the

microcontroller and the peripherals.

Program Status Word (PSW): The Program Status Word (PSW) register is an 8 bit register. It

is also referred to as the flag register. It contains the math flags, user program flag F0, and the

register select bits that identify which of the four general purpose register banks is currently in

use by the program.

Oscillator: Oscillator circuit is used for providing a microcontroller with a clock. Clock is

needed so that microcontroller could execute a program or program instructions. Stable pace

provided by the oscillator allows harmonious and synchronous functioning of all other parts of

MCU. The manufacturers make available 89C51 designs that can run at specified maximum and

minimum frequencies, typically 1 megahertz to 33 megahertz. Minimum frequencies imply that



some internal memories are dynamic and must always operate above a minimum frequency or

data will be lost.

Interrupts: An interrupt is a signal from a device attached to a computer or from a program

within the computer that causes the main program that operates the computer to stop and points

out what to do next. In general, there are hardware interrupts and software interrupts. A hardware

interrupt is related to the hardware of the system. For example, when an I/O operation is

completed such as reading some data into the computer from a keyboard interrupt the main

program. As the name implies the software interrupts related to the software of the system. It

occurs when an application program terminates or requests certain services from the operating

system.

Timers/Counters: Timers are usually the most complicated parts of a microcontroller.

Physically, timer is a register whose value is continually increasing to FFFFh, and then it starts

all over again: 0h, 1h, 2h, 3h, 4h...FFFFh....0h, 1h, 2h, 3h......etc. The 89C51 MCU clock

employs a quartz crystal. As this frequency is highly stable and accurate, it is ideal for time

measuring. Since one instruction takes 12 oscillator cycles to complete, the math is easy. 89C51

has three Timers/Counters marked as T0, T1 & T2. Their purpose is to measure time and count

external occurrences, but can also be used as clock in serial communication purpose called as,

Baud Rate.

Serial Port: Serial port is used to provide communication among two devices. Serial data

communication has been widely used for long distance communication because of the ease and

the economy of using only one wire to transmit data. Serial port is also referred as RS232 port.

RS232 is a asynchronous way of communication. Asynchronous transmission allows data to be

transmitted without the sender having to send a clock signal to the receiver. Instead, the sender

and receiver must agree on timing parameters in advance and special bits are added to each

word, which are used to synchronize the sending and receiving units.

When a word is given to the UART for Asynchronous transmissions, a bit called the

"Start Bit" is added to the beginning of each word that is to be transmitted. The Start Bit is used

to alert the receiver that a word of data is about to be sent, and to force the clock in the receiver

into synchronization with the clock in the transmitter.

TRANSMITTER USES AN INTERNAL CLOCK TO DETERMINE WHEN

TO SEND EACH BIT



RECEIVER DETECTS THE FALLING EDGE OF START, THEN

USES ITS INTERNAL CLOCK TO READ THE FOLLOWING BITS

Data

(61h ) START BIT 0 BIT 7 STOP

BIT BIT

1 0 0 0 0 1 1 0

ASYNCHRONOUS TRANSMISSION SEND LSB FIRST

Asynchronous Transmission

Memory Organization:

RAM (Data Memory)

RAM is used for storing temporary data and auxiliary results generated during the

runtime. The P89C51RD2BN has internal data memory that is mapped into four separate

segments: the lower 128 bytes of RAM, upper 128 bytes of RAM, 128 bytes Special Function

Register (SFR), and 768 bytes expanded RAM (ERAM). The four segments are:

1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are directly and indirectly

addressable.

2. The Upper 128 bytes of RAM (addresses 80H to FFH) are indirectly addressable

only.

3. The Special Function Registers, SFRs, (addresses 80H to FFH) are directly

addressable only.

4. The 768-bytes expanded RAM (ERAM, 00H – 2FFH) are indirectly accessed by

move external instruction, MOVX, and with the EXTRAM bit in the AUXR register

cleared.



RAM Organization

The Lower 128 bytes can be accessed by either direct or indirect addressing. The Upper

128 bytes can be accessed by indirect addressing only. The Upper 128 bytes occupy the same

address space as the SFR. That means they have the same address, but are physically separate

from SFR space. The ERAM can be accessed by indirect addressing, with EXTRAM bit in the

AUXR register cleared and MOVX instructions. This part of memory is physically located on-

chip, logically occupies the first 7936-bytes of external data memory. With EXTRAM = 0, the

ERAM is indirectly addressed, using the MOVX instruction in combination with any of the

registers R0, R1 of the selected bank or DPTR. An access to ERAM will not affect portsP0, P3.6

(WR) and P3.7 (RD). P2 SFR is output during external addressing. The stack pointer (SP) may

be located anywhere in the 256 bytes RAM (lower and upper RAM) internal data memory. The

stack may not be located in the ERAM.



Internal RAM Architecture

Flash Memory (Program Memory):

89C51 have built-in 64-kilo bytes of Flash memory. The P89C51RD2BN Flash memory

augments EPROM functionality with in-circuit electrical erasure and programming. The Flash

can be read and written as bytes. The Chip Erase operation will erase the entire program

memory. The Block Erase function can erase any Flash block. In-system programming and

standard parallel programming are both available. On-chip erase and write timing generation

contribute to a user-friendly programming interface. The P89C51RD2BN Flash reliably stores

memory contents even after 10,000 erase and program cycles. The cell is designed to optimize

the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide

processing and low internal electric fields for erase and programming operations produces



reliable cycling. The P89C51RD2BN uses a +5 V VPP supply to perform the Program/Erase

algorithms.

89C51 Program Memory

Special Function Registers:

Special Function Register (SFR) can be seen as a sort of control panel for managing and

monitoring the microcontroller. Every register and each of the belonging bits has its name,

specified address in RAM and strictly defined role (e.g. controlling the timer, interrupt, serial

communication, etc). Although there are 128 available memory slots for allocating SFR

registers. The rest has been left open intentionally to allow future upgrades while retaining thecompatibility with earlier models. This fact makes possible to use programs developed for

obsolete models long ago.

SYMBOL DESCRIPTION DIRECT ADDRESS

ACC Accumulator E0H



AUXR

AUXR1

B

CCAP0H

CCAP1H

CCAP2H

CCAP3H

CCAP4H

CCAP0L

CCAP1L

CCAP2L

CCAP3L

CCAP4L

CCAPM0

CCAPM1

CCAPM2

CCAPM3

CCAPM4

CCONCH

CKCON

CL

CMOD

DPH

DPL

IE

IP

IPH

P0

P1

P2

Auxiliary

Auxiliary 1

B register

Module 0 Capture High





Module 0 Capture Low





Module 0 Mode

Module 1 Mode

Module 2 Mode

Module 3 Mode

Module 4 Mode

PCA Counter ControlPCA Counter High

Clock control

PCA Counter Low

PCA Counter Mode

Data Pointer High

Data Pointer Low

Interrupt Enable 0

Interrupt Priority

Interrupt Priority High

Port 0

Port 1

Port 2

8EH

A2H

F0H

FAH

FBH

FCH

FDH

FEH

EAH

EBH

ECH

EDH

EEH

DAH

DBH

DCH

DDH

DEH

D8HF9H

8FH

E9H

D9H

83H

82H

A8H

B8H

B7H

80H

90H

A0H



P3

PCON

PSW

RCAP2H

RCAP2L

SADDR

SADEN

SBUF

SCON

SP

TCON

T2CON

T2MOD

TH0

TH1

TH2

TL0

TL1

TL2TMOD

WDTRST

Port 3

Power Control

Program Status Word

Timer 2 Capture High

Timer 2 Capture Low

Slave Address

Slave Address Mask

Serial Data Buffer

Serial Control

Stack Pointer

Timer Control

Timer 2 Control

Timer 2 Mode Control

Timer High 0

Timer High 1

Timer High 2

Timer Low 0

Timer Low 1

Timer Low 2Timer Mode

Watchdog Timer Reset

B0H

87H

D0H

CBH

CAH

A9H

B9H

99H

98H

81H

88H

C8H

C9H

8CH

8DH

CDH

8AH

8BH

CCH89H

A6H

Addressing Modes and Instruction Set

The CPU can access data in various ways. The data could be in a register, or in memory,

or to be provided as an immediate value. These various ways of accessing data are called



addressing modes. The various addressing modes are determined when it is designed and

therefore cannot be changed by the programmer. The 89C51 provide a total of five distinct

addressing modes. They are:

Immediate Addressing: Immediate addressing is so-named because the value to be stored in

memory immediately follows the operation code in memory.

Example: MOV A, #20H

Direct Addressing: In Direct addressing the value to be stored in memory is obtained by

directly retrieving it from another memory location.

Example: MOV A, 30H

Register Addressing: Register addressing accesses the eight working registers (R0 - R7) of the

selected register bank.

Example: MOV A, R0

Register indirect Addressing: Register indirect addressing is a very powerful addressing mode,

which in many cases provides an exceptional level of flexibility. Indirect addressing is also the

only way to access the extra 128 bytes of Internal RAM.

Example: MOV A, @R0

Indexed Addressing: Indexed addressing mode is widely used in accessing data elements of

look-up table entries located in the program ROM space of the 89C51.

Example: MOVC A, @A+DPTR, MOVC A, @A+PC

The 89C51 instruction set includes 111 instructions, 49 of which are single-byte, 45 two-

byte and 17 three-byte instructions. The instruction set is divided into four functional groups:

Data transfer - None of the data transfer operations affects the PSW flag settings

except a POP or MOV directly to the PSW.

Arithmetic - The 89C51 microcontrollers have four basic mathematical operations.

Only 8-bit operations using unsigned arithmetic are supported directly.



Logic - The 89C51 perform logic operations on both bit and byte operands

Control transfer - All control transfer operations, some upon a specific condition,

cause the program execution to continue a non-sequential location in program

memory.

Data Transfer Instructions:

Mnemonic Description Byte Cycle Op-

code



MOV A, R0 Move Register R0 to Accumulator 1 1 E8

MOV A, R1 Move Register R1 to Accumulator 1 1 E9

MOV A, R2 Move Register R2 to Accumulator 1 1 EA

MOV A, R3 Move Register R3 to Accumulator 1 1 EB

MOV A, R4 Move Register R4 to Accumulator 1 1 EC

MOV A, R5 Move Register R5 to Accumulator 1 1 EDMOV A, R6 Move Register R6 to Accumulator 1 1 EE

MOV A, R7 Move Register R7 to Accumulator 1 1 EF

MOV A, direct Move direct byte to A 2 1 E5

MOV A, @R0 Move indirect RAM to A 1 1 E6

MOV A, @R1 Move indirect RAM to A 1 1 E7

MOV A, #data Move immediate data to A 2 1 74

MOV R0, A Move Accumulator to Register R0 1 1 F8

MOV R1, A Move Accumulator to Register R1 1 1 F9

MOV R2, A Move Accumulator to Register R2 1 1 FA

MOV R3, A Move Accumulator to Register R3 1 1 FB

MOV R4, A Move Accumulator to Register R4 1 1 FCMOV R5, A Move Accumulator to Register R5 1 1 FD

MOV R6, A Move Accumulator to Register R6 1 1 FE

MOV R7, A Move Accumulator to Register R7 1 1 FF

MOV R0, direct Move direct byte to Register R0 2 2 A8

MOV R1, direct Move direct byte to Register R1 2 2 A9

MOV R2, direct Move direct byte to Register R2 2 2 AA

MOV R3, direct Move direct byte to Register R3 2 2 AB

MOV R4, direct Move direct byte to Register R4 2 2 AC

MOV R5, direct Move direct byte to Register R5 2 2 AD

MOV R6, direct Move direct byte to Register R6 2 2 AE

MOV R7, direct Move direct byte to Register R7 2 2 AF

MOV R0, #data Move immediate data to Register

R0

2 1 78


R1

2 1 79


R2

2 1 7A


R3

2 1 7B


R4

2 1 7C




R5

2 1 7D


R6

2 1 7E


R7

2 1 7F

MOV direct, A Move Accumulator to direct byte 2 1 F5

MOV direct, R0 Move Register R0 to direct byte 2 2 88

MOV direct, R1 Move Register R1 to direct byte 2 2 89

MOV direct, R2 Move Register R2 to direct byte 2 2 8A

MOV direct, R3 Move Register R3 to direct byte 2 2 8B

MOV direct, R4 Move Register R4 to direct byte 2 2 8C

MOV direct, R5 Move Register R5 to direct byte 2 2 8D

MOV direct, R6 Move Register R6 to direct byte 2 2 8E

MOV direct, R7 Move Register R7 to direct byte 2 2 8F

MOV direct, direct Move direct byte to direct byte 3 2 85

MOV direct, @R0 Move indirect RAM to direct byte 2 2 86MOV direct, @R1 Move indirect RAM to direct byte 2 2 87

MOV direct, #data Move immediate data to direct

byte

3 2 75

MOV @R0, A Move A to indirect RAM 1 1 F6

MOV @R1, A Move A to indirect RAM 1 1 F7

MOV @R0, direct Move direct byte to indirect RAM 2 2 A6

MOV @R1, direct Move direct byte to indirect RAM 2 2 A7

MOV @R0, #data Move immediate data to indirect

RAM

2 1 76

MOV @R1, #data Move immediate data to indirect

RAM

2 1 77

MOV DPTR, #da16 Load data pointer with 16-bit 3 2 90

MOVC A, @A+DPTR Move code byte related to Data

pointer to Accumulator

1 2 93

MOVC A, @A+PC Move code byte related to PC to A 1 2 83

MOVX A, @R0 Move External RAM (8-bit) to A 1 2 E2

MOVX A, @R1 Move External RAM (8-bit) to A 1 2 E3

MOVX A, @DPTR Move External RAM (16-bit) to A 1 2 E0

MOVX @R0, A Move A to External RAM (8-bit) 1 2 F2

MOVX @R1, A Move A to External RAM (8-bit) 1 2 F3

MOVX @DPTR, A Move A to External RAM (16-bit) 1 2 F0PUSH direct Push direct byte onto stack 2 2 C0

POP direct Pop direct byte from stack 2 2 D0

XCH A, R0 Exchange Register R0 with A 1 1 C8

XCH A, R1 Exchange Register R1 with A 1 1 C9

XCH A, R2 Exchange Register R2 with A 1 1 CA

XCH A, R3 Exchange Register R3 with A 1 1 CB

XCH A, R4 Exchange Register R4 with A 1 1 CC





SUBB A, R1 Subtract Register R1 from A with

borrow

1 1 99


borrow

1 1 9A


borrow

1 1 9B


borrow

1 1 9C


borrow

1 1 9D


borrow

1 1 9E


borrow

1 1 9F

SUBB A, direct Subtract direct byte from A with borrow

2 1 95

SUBB A, @R0 Subtract indirect RAM from A with

borrow

1 1 96

SUBB A, @R1 Subtract indirect RAM from A with borrow

1 1 97

SUBB A, #data Subtract immediate data from A with borrow

2 1 94

INC A Increment Accumulator 1 1 04

INC R0 Increment Register R0 1 1 08

INC R1 Increment Register R1 1 1 09

INC R2 Increment Register R2 1 1 0AINC R3 Increment Register R3 1 1 0B

INC R4 Increment Register R4 1 1 0C

INC R5 Increment Register R5 1 1 0D

INC R6 Increment Register R6 1 1 0E

INC R7 Increment Register R7 1 1 0F

INC direct Increment direct byte 2 1 05

INC @R0 Increment indirect RAM 1 1 06

INC @R1 Increment indirect RAM 1 1 07

DEC A Decrement Accumulator 1 1 14

DEC R0 Decrement Register R0 1 1 18

DEC R1 Decrement Register R1 1 1 19

DEC R2 Decrement Register R2 1 1 1A

DEC R3 Decrement Register R3 1 1 1B

DEC R4 Decrement Register R4 1 1 1C

DEC R5 Decrement Register R5 1 1 1D

DEC R6 Decrement Register R6 1 1 1E

DEC R7 Decrement Register R7 1 1 1F



DEC direct Decrement direct byte 2 1 15

DEC @R0 Decrement indirect RAM 1 1 16

DEC @R1 Decrement indirect RAM 1 1 17

INC DPTR Increment data pointer 1 2 A3

MUL AB Multiply A and B and put the lower-

byte of the product in A and thehigher-byte in B.

1 4 A4

DIV AB Divide A by B and put the Quotient in

A and the Remainder in B

1 4 84

DA A Adjust the sum of two packed

numbers found in A

1 1 D4

Logical Instructions:

Mnemonic Description Byte Cycle Opcode

ANL A, R0 AND Register R0 to Accumulator 1 1 58ANL A, R1 AND Register R1 to Accumulator 1 1 59

ANL A, R2 AND Register R2 to Accumulator 1 1 5A

ANL A, R3 AND Register R3 to Accumulator 1 1 5B

ANL A, R4 AND Register R4 to Accumulator 1 1 5C

ANL A, R5 AND Register R5 to Accumulator 1 1 5D

ANL A, R6 AND Register R6 to Accumulator 1 1 5E

ANL A, R7 AND Register R7 to Accumulator 1 1 5F

ANL A, direct AND direct byte to A and put theresult in A

2 1 55

ANL A, @R0 AND indirect RAM to A 1 1 56

ANL A, @R1 AND indirect RAM to A 1 1 57ANL A, #data AND immediate data to A 2 1 54

ANL direct, A AND Accumulator to direct byte and

put the result in memory

2 1 52

ANL direct, #data AND immediate data to direct byte 3 2 53

ORL A, R0 OR Register R0 to Accumulator 1 1 48

ORL A, R1 OR Register R1 to Accumulator 1 1 49

ORL A, R2 OR Register R2 to Accumulator 1 1 4A

ORL A, R3 OR Register R3 to Accumulator 1 1 4B

ORL A, R4 OR Register R4 to Accumulator 1 1 4C

ORL A, R5 OR Register R5 to Accumulator 1 1 4D

ORL A, R6 OR Register R6 to Accumulator 1 1 4E

ORL A, R7 OR Register R7 to Accumulator 1 1 4F

ORL A, direct OR direct byte to A and put the result

in A

2 1 45

ORL A, @R0 OR indirect RAM to A 1 1 46

ORL A, @R1 OR indirect RAM to A 1 1 47

ORL A, #data OR immediate data to A 2 1 44



ORL direct, A OR Accumulator to direct byte and

put the result in memory

2 1 42

ORL direct, #data OR immediate data to direct byte 3 2 43

XRL A, R0 Exclusive OR Register R0 to A 1 1 68

XRL A, R1 Exclusive OR Register R1 to A 1 1 69

XRL A, R2 Exclusive OR Register R2 to A 1 1 6AXRL A, R3 Exclusive OR Register R3 to A 1 1 6B

XRL A, R4 Exclusive OR Register R4 to A 1 1 6C

XRL A, R5 Exclusive OR Register R5 to A 1 1 6D

XRL A, R6 Exclusive OR Register R6 to A 1 1 6E

XRL A, R7 Exclusive OR Register R7 to A 1 1 6F

XRL A, direct Ex - OR direct byte to A 2 1 65

XRL A, @R0 Exclusive OR indirect RAM to A 1 1 66

XRL A, @R1 Exclusive OR indirect RAM to A 1 1 67

XRL A, #data Exclusive OR immediate data to A 2 1 64

XRL direct, A Exclusive OR Accumulator to direct

byte and put the result in memory

2 1 62

XRL direct, #data Ex - OR immediate data to direct byte 3 2 63

CLR A Clear Accumulator 1 1 E4

CPL A Complement Accumulator 1 1 F4

RL A Rotate Accumulator Left 1 1 23

RLC A Rotate Accumulator left through carry 1 1 33

RR A Rotate Accumulator Right 1 1 03

RRC A Rotate Accumulator Right through

carry

1 1 13

SWAP A Swap the nibbles of Accumulator 1 1 C4

Boolean Variable Manipulation Instructions:

Mnemonic Description Byte Cycle Opcode

CLR C Clear carry flag 1 1 C3

CLR bit Clear direct bit 2 1 C2

SETB C Set carry flag 1 1 D3

SETB bit Set direct bit 2 1 D2

CPL C Complement carry flag 1 1 B3

CPL bit Complement direct bit 2 1 B2

ANL C, bit AND direct bit to carry flag 2 2 82ANL C, /bit AND complement of direct bit to carry 2 2 B0

ORL C, bit OR direct bit to carry flag 2 2 72

ORL C, /bit OR complement of direct bit to carry 2 2 A0

MOV C, bit Move direct bit to carry flag 2 1 A2

MOV bit, C Move carry flag to direct bit 2 2 92



Program and Machine Control Instructions:

Mnemonic Description Byte Cycle Op-

code

ACALL addr11 Absolute Subroutine call (If thecalling Address is within FFh)

2 2 11

ACALL addr11 Calling Address is within 1FFh 2 2 31ACALL addr11 Calling Address is within 2FFh 2 2 51

ACALL addr11 Calling Address is within 3FFh 2 2 71

ACALL addr11 Calling Address is within 4FFh 2 2 91

ACALL addr11 Calling Address is within 5FFh 2 2 B1

ACALL addr11 Calling Address is within 6FFh 2 2 D1

ACALL addr11 Calling Address is within 7FFh 2 2 F1

LCALL addr16 Long Subroutine call 3 2 12

RET Return from Subroutine 1 2 22

RETI Return from Interrupt 1 2 32

AJMP addr11 Absolute jump (If the jumping

Address is within 0FFh)

2 2 01

AJMP addr11 Absolute jump (If the jumpingAddress is within 0FFh)

2 2 21


2 2 41


2 2 61



2 2 81



2 2 A1


2 2 C1



2 2 E1

LJMP addr16 Long jump 3 2 02

SJMP rel Short jump to relative address 2 2 80

JMP @A+DPTR Jump indirect relative to DPTR 1 2 73

JZ rel Jump if Accumulator is zero 2 2 60

JNZ rel Jump if Accumulator is not zero 2 2 70

JC rel Jump if carry flag is set 2 2 40

JNC rel Jump if carry flag is reset 2 2 50

JB bit, rel Jump if direct bit is set 3 2 20

JNB bit, rel Jump if direct bit is not set 3 2 30

JBC bit, rel Jump if direct bit is set and clear

bit

3 2 10

CJNE A, direct, rel Compare direct byte to A and

jump if not equal

3 2 B5



CJNE A, #data, rel Compare immediate data to A and jump if not equal

3 2 B4

CJNE R0, #data, rel Compare immediate data toRegister R0 and jump if not equal

3 2 B8

CJNE R1, #data, rel Compare immediate data toRegister R1 and jump if not equal

3 2 B9

CJNE R2, #data, rel Compare immediate data to

Register R2 and jump if not equal

3 2 BA



3 2 BB



3 2 BC



3 2 BD



3 2 BE



3 2 BF

CJNE @R0, #data, rel Compare immediate data to RAM

and jump if not equal

3 2 B6

CJNE @R1, #data, rel Compare immediate data to RAM

and jump if not equal

3 2 B7

DJNZ R0, rel Decrement Register R0 and jump

if not zero

2 2 D8


if not zero

2 2 D9

DJNZ R2, rel Decrement Register R2 and jumpif not zero

2 2 DA


2 2 DB


2 2 DC


2 2 DD


if not zero

2 2 DE


if not zero

2 2 DF

DJNZ direct, rel Decrement direct byte and jump if not zero

3 2 D5

NOP No Operation 1 1 00



Liquid Crystal Display (LCD)

Liquid crystals are a phase of matter whose order is intermediate between that of a liquid

and that of a crystal. The molecules are typically rod-shaped organic matters about 25 Angstroms

in length and their ordering is a function of temperature. The molecular orientation can be

controlled with applied electric fields. LCD is made up of two sheets of polarizing material with

the liquid crystal solution between them. An electric current passed through the liquid causes the

crystals to align so that light cannot pass through them, which results in display of character as

per the applied voltage in its data lines. The driver is provided to drive the LCD. It stores the

display data transferred from the microcontroller in the internal display RAM and generates dot

matrix liquid crystal driving signals. Each bit data of display RAM corresponds to on/off state of

a dot of a liquid crystal display.

LCD pin description

LCD is used in widespread applications replacing LEDs (Seven segment LEDs or other

multisegment LEDs) nowadays. This is due to the following reasons:

1. The declining prices of LCDs.

2. The ability to display numbers, characters, and graphics. This is in contrast to LEDs,

which are limited to numbers and a few characters.



3. Incorporation of a refreshing controller into the LCD, thereby relieving the CPU of

the task of refreshing the LCD.

4. Ease of programming for characters and graphics.

Pin Description:

Pin Symbol I/O Description

1 GND -- Ground

2 VCC -- +5V Power Supply

3 V0 -- LCD driving voltage

4 RS I RS = 0 to select command register

RS = 1 to select data register

5 RW I RW = 0 for write

RW = 1 for read

6 EN I Enable

7-14 D0-D7 I / O The 8-bit Data Bus

15 VCC -- +5V Power Supply

16 GND -- Ground

VCC, GND AND V0: While VCC and VSS provide +5V and ground, respectively, V0 is used

for controlling LCD contrast.

RS (Register Select): If RS = 0, the instruction command code register is selected, allowing

the user to send a command such as clear display, cursor at home, etc. If RS = 1, the data

register is selected, allowing the user to send data to be displayed on the LCD.

RW (Read/Write): RW allows the user to write information to the LCD or read information

from it. R W=1 when reading; RW=0 when writing.

EN (Enable): The LCD to latch information presented to its data pins uses the enable pin. When

data is supplied to data pins, a high to low pulse must be applied to this pin in order for the LCD

to latch in the data present at the data pins.



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Embedded Microcontroller