Embedded Systems: Hardware

Combinational Logic

(Peckol 2.5-2.8 & 10.11-10.15 + notes)

Testing

(notes)

Main issues in performance of combinational logic:

The world is ANALOG, not digital; even in designing combination logic, we need to take analog effects into account

Software doesn’t change but hardware does:--different manufacturers of the same component--different batches from the same manufacturer--environmental effects--aging--noise

main areas of concern:--signal levels (“0”, “1”—min, typical, and max values; fan-in, fan-out)--timing—rise & fall times; propagation delay; hazards and race conditions--how to deal with effects of unwanted resistance, capacitance, induction

Race conditions and hazards (“glitches”)Critical: state or output depends on order of arrival at decision point

Noncritical: output value does not depend on order of arrival of inputs

Hazard: (also called a decoding spike or a glitch): present in a circuit if the circuit has the possibility of giving an incorrect output

2 types of hazards:Static: glitch may occur because of race between 2 or more input signals when output expected to remain at steady levelStatic-0: may produce erroneous 1; static-1: the opposite

Dynamic: output may erroneously change more than once as result of one single input transition

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Examples:

static-0 hazard:Extra delay through inverter

Static-1 hazard:

Adding buffers to match delays Will not work because ofParameter variations occurringIn real physical parts

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Additional examples for analysis:

fig_02_16_01

fig_02_16_02

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Example: dynamic hazard

One slow path and one fast path; other devices are assumed to have typical delays, all of the same value

If B 0 1 there will be 3 state changes in the output before it settles

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“LEGACY OF THE EARLY PHYSICISTS”: RESISTANCE, CAPACITANCE, COUPLING (“micro view”, passive components)

Ampere: current flowing in a wire produces magnetic field

Faraday, Lenz: wire moving in magnetic field has induced current

Gauss et al.: capacitance

Situations to examine:Coupling between two adjacent wiresMutual capacitance between adjacent circuits…etc.

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PHYSICAL PROPERTIES: RESISTANCE R

R = (L / A)

Q: what does this say about:--length of wires?--feature sizes?--noise margins for low voltage?

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Modeling resistance (first-order model, includes inherent parasitic devices): for DC, L and C can be ignored; but in our circuits we will have time-varying signals

We are assuming a lumped system (all resistance considered to be “lumped” at one node)

For a distributed system we would look at

R(x)dx, L(x)dx, C(x)dx

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Capacitance: C = A/d

Many instances of capacitors on chip:

--Power/ground planes--parallel wires--adjacent pins--etc.

Example: part of signal in top wire shows up as noise in adjacent wire:

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First-order (lumped) model:

Using Laplace transform gives

Z(s) = 1/Cs + Ls + R; inductor dominates at higher frequencies

For C =

1 muf, 0,1 muf, 0.01 muf:

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How do these effects change logic circuit?

Example: 2 inverters in series

Resistor: connecting path

Capacitor: device, wire, IC package, coupling to other devices

VOUT (s) = [1/Cs] / [R + 1/Cs] * V(s)IN

= [1/(RCs+1)] * V(s)IN

= [1/(RCs+1)] * [VIN/s]

for VIN a step function

VOUT(t) = VIN(1-exp(-t/RC))

Rise (and fall) times are slowedComponents can be damaged orData rate can be reduced

fig_02_27: interconnect

fig_02_28:interconnect, driver

fig_02_29: rise time

Example: tristate driver

Enable different data sources to use system bus

If driver disables, pullup resistor controls bus

VOUT(t) = VIN(1-exp(-t/RC))

Rise time is increased and

Receiving device can enter metastable region where there is oscillation in its output

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Example: why you should never leaveGate inputs floating (using a 3-inputAND gate for a 2-input application):

3 methods:

1

2

3

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1:

VOUT(s) = C1/(C1+C2)*VIN(s);

If voltage too low, output is always 0

2.Cap = C1 + C2

This doubles time constant, reduces rise/fall time; can give metastable behavior on switching

3. State of unused pin defined by pullup resistor, this will work

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Second-order: add parallel inductor

This adds a damping factor:

Natural frequency wn = 1/ (LC)1/2 ; damping d = (R/2) * (L/C)1/2

d < 1: underdamped—can have oscillation, noise;

d = 1: damped okay;

d > 1: overdamped—can have metastability

fig_02_37

Testing combinational circuits

Fault-unsatisfactory condition or state; can be constant, intermittent, or transient; can be static or dynamic

Error: static; inherent in system; most can be caught

Failure: undesired dynamic event occurring at a specific time—typically random—often occurs from breakage or age; cannot all be designed away

Physical faults: one-fault model

Logical faults:

Structural—from interconnections

Functional: within a component

Structural faults:

Stuck-at model: (a single fault model)

s-a-1; s-a-0; may be because circuit is open or there is a short

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Testing combinational circuits: s-a-0 fault

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Modeling s-a-0 fault:

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S-a-1 fault

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Modeling s-a-1 fault:

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Open circuit fault; appears as a s-a-0 fault

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Bridging fault: bad connections, broken flakes, errant wire pieces

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Examples of bridging faults

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Bridging faults can be feedback or non-feedback faults

Non-feedback faults

Between input or output and power rail: use stuck-at model

Between signal traces or logic pins:

inputs: model as common signal to both inputs

internal: who wins?

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Modeling a “competitive” fault: result of fault depends on logic family being used

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Feedback bridging faults:

Number of inversions is important

Circuit A Circuit B

In A there are an odd number of inversions on the path; this can cause oscillation; can sometimes be modeled as competing signals

In B there are an even number of inversions; this can often be modeled as a stuck-at fault

fig_02_49 fig_02_50

Functional faults:

Example: hazards, race conditions

Two possible methods:

A: consider devices to be delay-free, add spike generator

B: add delay elements on paths

Method A Method B

As frequencies increase, eliminating hazards through good design iseven more important

Testing:

General Requirements

DFT

Multilevel Testing--

System, Black Box, White Box Tests

Testing--General Requirements

Testing--general requirements:

•thorough

•ongoing

•DEVELOPED WITH DESIGN (DFT--design for test)note: this implies that several LEVELS of testing will be carried out

•efficient

Good, Bad, and Successful Tests

•good test: has a high probability of finding an error

•("bad test": not likely to find anything new)

•successful test: finds a new error

Most Effective Testing Is Independent

most effective testing:

by an "independent” third party

Question: what does this imply about your team testing strategy for the quarter project?

How Thoroughly Can We Test?

how thoroughly can we test?

example:

VLSI chip

200 inputs

2000 flipflops (one-bit memory cells)

# exhaustive tests?

What is the overall time to test if we can do1 test / msec? 1 test / sec?testsec?

Design for Testability (DFT)

Design for Testability (DFT)--what makes component "testable"?

operability: few bugs, incremental test

observability: you can see the results of the test

controllability: you can control state + input to test

decomposability: you can decompose into smaller problems and test each separately

simplicity: you choose the “simplest solution that will work”

stability: same test will give same results each time

understandability: you understand component, inputs, and outputs

Testing strategies

testing strategies:

verification--functions correctly implemented

validation--we are implementing the correct functions (according to requirements)

Spiral design/testing strategy

A general design/testing strategy can be described as a "spiral”:requirements design codesystem test module,integ. tests unit test (system) (black (white

box) box)

when is testing complete?One model:"logarithmic Poisson model”

f(t)=(1/p)ln(I0pt+1)

f(t) = cumulative expected failures at time tI0 = failures per time unit at beginning of testingp = reduction rate in failure intensity

START

END

Requirements, Specs/System Tests

Design/Integration Tests

Implement/Unit Tests

Design/Module Tests

Types of testing

Types of testing:

white box--"internals” (also called "glass box")

black box—modules and their "interfaces” (also called "behavioral")

system--”functionality” (can be based on specs, use cases)

(application-specific)

Good testing strategy

steps in good test strategy:

•quantified requirements

•test objectives explicit

•user requirements clear

•use "rapid cycle testing"

•build self-testing software

•filter errors by technical reviews

•review test cases and strategy formally also

•continually improve testing process

Black box testing guidelines

General guidelines:

test BOUNDARIES

test output also

choose "orthogonal” cases if possible