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Embedding of Embedding of Asynchronous Wave Pipelines into Asynchronous Wave Pipelines into
Synchronous Data ProcessingSynchronous Data Processing
Stephan Hermanns, Sorin Alexander HussStephan Hermanns, Sorin Alexander Huss
University of Technology Darmstadt, GermanyUniversity of Technology Darmstadt, Germany
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Some Notations...Some Notations...
generator pulse of time evaluationt
register of time holdholdt
register of time up-setsetupt
register ofdelay npropagatiodelay.regt
register atskew clock eduncontrollskewt
clock output and input betweendelay iΔoΔΔ
registers output and input atskew lintentionaoΔ,iΔ
time cycle or period clockclkT
eval
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Asynchronous Wave Pipeline (AWP)Asynchronous Wave Pipeline (AWP)
Wave LogicWave Logic
Wave Latch
Wave Latch
Wave Latch
Wave Latch
Data
req_in req_outmatched delaymatched delay
More than one data and request propagating coherently
One-sided cycle time constraint
Delay must track logic over PTV corners
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CircuitsCircuits
Logic style used has to minimize delay variation Earlier work focused on bipolar logic (ECL, CML), but
CMOS is mainstream Static CMOS is not well suited for wave piping, fixing the
problem results in more power and slower speed Pass transistor logic gives slopy edges thereby
introducing delay variation Dynamic logic is attractive as only output high transition is
data-dependant, output pulldown is done by precharge What is needed is a dynamic logic family without
precharge overhead: SRCMOS
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SRCMOSSRCMOS
Distinguishing property of our SRCMOS circuits: precharge feedback is fully local, and NMOS trees are delay balanced
Ninputs
output
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Generic Synchronous PipelineGeneric Synchronous Pipeline
LogicLogic
Latch/Reg
Latch/Reg
Latch/Reg
Latch/Reg
Data
Clk
i o
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Static Static Pulse Conversion: Transistor Level Pulse Conversion: Transistor LevelData input has to Data input has to be stable during be stable during evaluation time evaluation time ttevaleval after rising after rising
edge ofedge ofclkclkaa or clk or clkbb
Pulse width is Pulse width is defined by defined by feedback path of feedback path of SRCMOSSRCMOS
Generates pulse according to data input Generates pulse according to data input after rising edge of clka or clkbafter rising edge of clka or clkb
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Pulse Pulse Static Conversion: Schematic Level Static Conversion: Schematic Level
Data pulse is catched asynchronous and output Data pulse is catched asynchronous and output statically in synchronization with request pulsestatically in synchronization with request pulse
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Request Generation: Register is omittedRequest Generation: Register is omitted
Input to Register is stable in [MInput to Register is stable in [MTTclkclk-t-tsetupsetup,M,MTTclkclk+t+tholdhold]]
This has to be sufficient to Pulse Generator to evaluate This has to be sufficient to Pulse Generator to evaluate Input DataInput Data
Hold time tHold time tholdhold is crucial is crucial Further Investigation Further Investigation
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Request Generation: Register is keptRequest Generation: Register is keptOnly non-inverting Only non-inverting outputs used to form outputs used to form clock-like Signal to clock-like Signal to Pulse-Gen. Pulse-Gen. no Skew no Skew
Request and Data Pulses Request and Data Pulses are generated uniformlyare generated uniformly
No additionally Reset of No additionally Reset of Register neededRegister needed
Delay Variations among Delay Variations among FFs are handled simplyFFs are handled simply
Input to Pulse-Gen. is to be stable after rising clock edgeInput to Pulse-Gen. is to be stable after rising clock edge
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Overall DelayOverall Delay
Includes delay Includes delay ofof
D-FFD-FF
static static pulse pulse converterconverter
empty AWP empty AWP logiclogic
pulse pulse static static converterconverter
Problem: Delay variation may as large as clock period TProblem: Delay variation may as large as clock period Tclkclk
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Request Pulses: Maximum Skew Request Pulses: Maximum Skew Request skew Request skew primarly results primarly results of skew between of skew between rising edges at rising edges at clkclkaa and clk and clkbb
input of pulse input of pulse generatorgenerator
Exponential Exponential behavior at low behavior at low levellevel
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ConclusionConclusion
Integration of pulsed logic into environment of statical Integration of pulsed logic into environment of statical datadata
Generation of data pulses by different waysGeneration of data pulses by different ways
Generation of request pulses coherently to data pulsesGeneration of request pulses coherently to data pulseswith low skew with low skew
Conversion of pulsed data back to statical dataConversion of pulsed data back to statical data
Further investigation is needed:Further investigation is needed:
synchronization of static output and output register‘s clocksynchronization of static output and output register‘s clock
Possibility to replace register by pulse generator generallyPossibility to replace register by pulse generator generally