EMI Driven by PI - url.t drive by PI.pdf · © 2008 Ansoft, LLC All rights reserved. Ansoft, LLC Proprietary Outline • SI + PI = EMI – These disciplines are no longer independent

© 2008 Ansoft, LLC All rights reserved. Ansoft, LLC Proprietary

EMI Driven by PI


Outline

• SI + PI = EMI

– These disciplines are no longer independent of each other

• Fundamentals of EMI

– Where does it come from and how is it minimized

– Five Step EMC Design Flow

• Power Integrity design methodology to reduce EMI

– Fundamentals of Power Integrity

– Design Process to meet design specs in the Time and Frequency

domain

• 2nd Presentation on EMI Driven by SI

– Fundamentals of Signal Integrity

• Crosstalk is the main contributor to EMI

– Case studies that show perils of crosstalk in real world designs


SI/PI/EMI Design Overview

Driver ICControl IC Memory

Power Supplies

Display Panel

Signal Integrity- Impedance

- Crosstalk

- Reflection

- Termination

- Dielectric Losses

Power Integrity- Switching Noise

- Impedance Profile

- Power/Gnd Plane Resonance

- Decoupling Capacitors

EMI/EMC- Common mode radiation

- Differential mode radiation

PCB

Pwr Noise

Signal

Signal Integrity

Time DomainFrequency Domain

Power Integrity

PCB

Electromagnetic

Interference


Three Basic Elements of EMC

EMI sourceEMI source

Capacitive Inductive RadiativeConductive

Space & FieldConduction

EMSEMS

Low & Middle Frequency

LC Resonance

High FrequencyLow, Middle & High

Frequency

Coupling process

Immunity

Emission

ShieldsldShieldsEMI FiltersEMI Filters

ShieldsShields ShieldsShields ShieldsShieldsEMI FiltersEMI Filters


Loop Mode & Common Mode Noise

A PC Board & Cables

A Driver & Receiver

A victim device

Loop mode

current

Common mode

current

by AC Analysis of

Q3D Extractor

Differential mode current flows --- Loop

Common mode current flows --- Open

We can see Common mode current is

more serious than Normal mode.


Antenna theory

r

AI)(f.E

- sin106131 216

r

lIfE

sin)(104 7

-A Differential mode current flow Loop antenna theory

-A Common mode current flow Dipole antenna theory

Illustration of a loop antenna Illustration of a dipole antenna

r : distancer

Length :l

A : area of the loop

FCC B level Mag. E limit :40dBuV/m @ 3m

Mag. E( Loop antenna) : 20mA

Mag. E( Dipole antenna) : 8uA

II


EMC Design Flow

Planes deliver power to ICs and return

path for signal

Ensure that Plane impedance is smooth

and low over broad frequency range

Resonance Analysis

Emissions Analysis

Impedance Analysis

Signal Extraction

Enclosure Simulation


EMC Design Flow

Resonance Analysis

Emissions Analysis

Impedance Analysis

Signal Extraction


Resonances indicate areas of high

impedance and EMI potential

Ensure power planes do not resonant in

critical locations


EMC Design Flow

If signal is not at the receiver, it went

somewhere else

Ensure clean signal transmission and

good return path for critical nets

Resonance Analysis

Emissions Analysis

Impedance Analysis

Signal Extraction



EMC Design Flow

Non-ideal planes and tight routing can

lead to unintentional signals

Ensure there are no unintentional

radiators

Resonance Analysis

Emissions Analysis

Impedance Analysis

Signal Extraction



EMC Design Flow

Real enclosures are non-ideal and

can pass radiation

Ensure minimal radiation from PCB

escapes the chassis holes

Resonance Analysis

Emissions Analysis

Impedance Analysis

Signal Extraction



Electromagnetic

InterferencePower Integrity

PI Methodology

Signal Integrity


Power Integrity – A Case Study

• Active devices require clean power to operate

correctly

• Power distribution system (PDS) design engineers

must ensure that all parts receive voltage between

certain limits and that noise is kept sufficiently low

• Today’s designs with many separate power domains

of high current and low voltage devices complicate

power integrity analysis


Board Imported from Layout

Measuring

impedance at

the six VCC

pins on U41

VRM


PDS Design Flow

EM extraction of impedance

for critical devices

Determinefrequencies of specification

violations

Simulate in time domain to

check for compliance

Choose capacitor or geometric

change to address violations

Alter design

according to

findings

Start Finish

No

Yes


1MHz1KHz

Switching

Power

Supply

Electrolytic

Bulk

Capacitors

High

Frequency

Ceramic

Capacitors

Power/Ground

Planes

BuriedCapacitance

1 GHz

100MHz

f

|Z|

targetZ

Mag. of Z Current

RippleAllowedVoltageSupplyPowerZ

___Target

Frequency Domain PDS Targets


Defining the Target Impedance

0

0

0

VR

M

VR

M

VR

M

50

R5

V33

DC=VCC

V35

io

pullup

pulldown

logic_in

enableout_of_in

Cpkg

C58

Lpkg

L59

Rpkg

R60

AN

am

e=

vrm

• To define the target

impedance we need to

consider two factors:

– Peak current

• Determines maximum

impedance

– Spectral power

• Determines cutoff

frequency

Package Model

Driver

VRM


• Peak driver current

37.87 mA

• Example:

– Six drivers and 0.18 V

maximum voltage swing:

Peak Current

0.00 5.00 10.00 15.00 20.00 25.00 30.00 35.00 40.00 45.00 50.00Time [ns]

0.00

5.00

10.00

15.00

20.00

25.00

30.00

35.00

40.00

ma

g(I

po

sitiv

e(v

rm))

[m

A]

Ansoft Corporation DriverDriver Current

Curve Info max

mag(Ipositive(vrm))

Transient37.8706

m 800mA 87.376

V 18.0


0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 20.4

0.5

0.6

0.7

0.8

0.9

1

Frequency [GHz]

CDF

0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00Spectrum [GHz]

1.00E-012

1.00E-011

1.00E-010

1.00E-009

1.00E-008

1.00E-007

1.00E-006

1.00E-005

1.00E-004

1.00E-003

mag(v

rm_power)

Ansoft Corporation DriverXY Plot 4

Curve Info

mag(vrm_pow er)

Transient

Driver Spectrum

0.8 1 1.2 1.4 1.6 1.8 2

Frequency [GHz]

0.80 1.00 1.20 1.40 1.60 1.80 2.00Spectrum [GHz]

DriverXY Plot 4

Curve Info

mag(vrm_pow er)mag(vrmag(vr

TransientTransTransChoose a frequency below

which most of the signal

energy lies

667 MHz = 97% of Spectrum

667 MHz

CDF


Power Integrity Investigation

Added two bulk

47 uF capacitors

as specified by

VRM

manufacturer


Bare Board vs. Bulk Capacitors

Resonance @ 50 MHz Bare Board

Board w/

Bulk Caps

Target

impedance 800

mOhm to 667

MHz


V33

DC=VCC0

J5_V

CC

Time Domain Schematic

VCC_U41-21

VCC_U41-42

VCC_U41-44

VCC_U41-63

VCC_U41-84

J5_V

CC

VCC_U41-2

J5_V

CC

VCC_U41-2

VCC_U41-21

VCC_U41-42

VCC_U41-44

VCC_U41-63

VCC_U41-840

50

R5

VC

C_

U4

1-2

V35

io

pullup

pulldown

logic_in

enableout_of_in

VC

C_

U4

1-2

0

Cpkg

C58

Lpkg

L59

Rpkg

R60

x6

800 Mbps data rate

DDR2 IBIS driver into ideal

termination used as load for PDS

Package decoupling modeled

using a capacitor w/ ESR, ESL

Driver

VRM

Board


Switching Power Noise

0.00 10.00 20.00 30.00 40.00 50.00 60.00 70.00 80.00 90.00 100.00Time [ns]

1.20

1.40

1.60

1.80

2.00

2.20

2.40

Y1

[V

]

Ansoft Corporation BulkU41 Power

Curve Info pk2pk

V(VCC_U41-2)

Transient0.6787

V(VCC_U41-21)

Transient0.6995

V(VCC_U41-42)0.8191

V(VCC_U41-44)

V(VCC_U41-63)

Transient0.7882

V(VCC_U41-84)

Transient0.6858

Curve Info pk2pk

V(VCC_U41-2)

Transient67870.6767

V(VCC_U41-21)

Transient0.6995

-42)V(VCC_U41-4-40.819

C_U41-44)V(VCC_C_

Shaded area represents time

domain violation of 1.8 V ± 10%

~11-12 ns

period

Bulk Only

3Meter FF


Choosing a Decoupling Capacitor

• To reduce the effect of a

resonance, choose a

capacitor with a low

impedance at the

resonant frequency

Board w/

Bulk Caps

22 nF

Capacitor


Bulk vs. HF Capacitors 1

No Resonance @ 50 MHz

Board w/

Bulk Caps

Board w/

HF Caps 1

Target

impedance 800

mOhm to 667

MHz


0.00 10.00 20.00 30.00 40.00 50.00 60.00 70.00 80.00 90.00 100.00Time [ns]

1.20

1.40

1.60

1.80

2.00

2.20

2.40

Y1 [

V]

Ansoft Corporation HF1U41 Power

Curve Info pk2pk

V(VCC_U41-2)

Transient0.6481

V(VCC_U41-21)

Transient0.6979

V(VCC_U41-42)

Transient0.8802

V(VCC_U41-44)0.9182

V(VCC_U41-63)

Transient0.6925

V(VCC_U41-84)

Transient0.7319


)1-2))

pkpk2ppCurve Info

V(VCC_U4

Transient.6480..))))

1-21)11V(VCC_U4

Transient0.697

))

_U41-42)V(VCC__

Transient0.8802

))

CC_U41-44)V(VCC0.9182

))

Shaded area represents time

domain violation of 1.8 V ± 10%

Bulk Only

3Meter FF


Extending Low Impedance

• 10 1.2 nF capacitors

were added across the

board to extend

minimum high-frequency

impedance

• 1.2 nF capacitor was

chosen due to low

impedance at 200 MHz

• 4 of these were located

near U41


HF 1 vs. HF 2

New resonance @ 80 MHz

Impedance exceeds

800 mOhm @ 350 MHz

Board w/

HF Caps 1

Board w/

HF Caps 2

Target

impedance 800

mOhm to 667

MHz



0.00 10.00 20.00 30.00 40.00 50.00 60.00 70.00 80.00 90.00 100.00Time [ns]

1.20

1.40

1.60

1.80

2.00

2.20

2.40

Y1

[V

]

Ansoft Corporation HF2U41 Power

Curve Info pk2pk

V(VCC_U41-2)

Transient0.2552

V(VCC_U41-21)

Transient0.2857

V(VCC_U41-42)

Transient0.2930

V(VCC_U41-44)

Transient0.4047

V(VCC_U41-63)

Transient0.3083

V(VCC_U41-84)

Transient0.3359

0.4047

0.2930

0.2857

25520.2525

Curve Info pk2pk

V(VCC_U41-2)

Transient

V(VCC_U41-21)

Transient

-42)V(VCC_U41-4-4

Transient

C_U41-44)V(VCC_C_

Transient

Shaded area represents time domain specification 1.8 V ± 10%


Removing a Resonance

• Six 8 nF capacitors were

added near U41 to

cancel resonance at 80

MHz

Added capacitors

U41


HF 2 vs. HF 3

No resonance @ 80 MHz

Impedance crosses

800 mOhm @ 500

MHz

Board w/

HF Caps 2

Board w/

HF Caps 3

Target

impedance 800

mOhm to 667

MHz


0.00 10.00 20.00 30.00 40.00 50.00 60.00 70.00 80.00 90.00 100.00Time [ns]

1.20

1.40

1.60

1.80

2.00

2.20

2.40

Y1

[V

]

Ansoft Corporation FinalU41 Power

Curve Info pk2pk

V(VCC_U41-2)

Transient0.2416

V(VCC_U41-21)

Transient0.2685

V(VCC_U41-42)

Transient0.2660

V(VCC_U41-44)

Transient0.3264

V(VCC_U41-63)

Transient0.3709

V(VCC_U41-84)

Transient0.3142


0.3264

0.2660

0.2685

24160.2424

pk2pkCurve Info

V(VCC_U41-2)

Transient

V(VCC_U41-21)

Transient

-42)V(VCC_U41-4-4

Transient

C_U41-44)V(VCC_C_

Transient

Shaded area represents time domain specification 1.8 V ± 10%

Maximum peak to peak noise of 371 mV


Buried Capacitance

• Due to parasitic inductance it is impossible to decouple the board with capacitors at frequencies greater than a few hundred MHz

• Using a thinner dielectric layer between power and ground planes introduces additional capacitance and reduces high frequency impedance

d

AC

Capacitance of

parallel plates:


HF 3 vs. Buried Capacitance

Impedance crosses

800 mOhm @ >667

MHz

Board w/

HF Caps 3Board w/

Buried

Capacitance

Target

impedance 800

mOhm to 667

MHz

Target impedance specification met


0.00 10.00 20.00 30.00 40.00 50.00 60.00 70.00 80.00 90.00 100.00Time [ns]

1.20

1.40

1.60

1.80

2.00

2.20

2.40

Y1

[V

]

Ansoft Corporation BuriedU41 Power

Curve Info pk2pk

V(VCC_U41-2)

Transient0.2177

V(VCC_U41-21)

Transient0.2295

V(VCC_U41-42)

Transient0.2418

V(VCC_U41-44)

Transient0.2549

V(VCC_U41-63)

Transient0.2729

V(VCC_U41-84)

Transient0.2169


0.2549

0.2418

0.2295

21770.22

Curve Info pk2pk

V(VCC_U41-2)

Transient

V(VCC_U41-21)

Transient

-42)V(VCC_U41-4-4

Transient

C_U41-44)V(VCC_C_

Transient

Maximum peak to peak noise 273 mV

24% smaller than limit

Shaded area represents time domain

specification 1.8 V ± 10%

Time-domain noise specification met

3Meter FF

SpecificationSpecification

Met!Met!


Conclusions

• SI / PI / EMI are all based on the same

electromagnetic fundamentals and cannot be

separated

• Impedance and resonant mode simulations connect

the frequency domain to the spatial domain and allow

selection of capacitor value and placement

• Frequency domain extractions are useful for quickly

optimizing PDS designs, but time domain simulations

are necessary to ensure compliance with device specs

• Using a single design environment can help reuse the

same models for SI/PI/EMI simulations


Questions

Any Questions?Any Questions?

Documents

EMI Driven by PI - url.t drive by PI.pdf · © 2008 Ansoft, LLC All rights reserved. Ansoft, LLC Proprietary Outline • SI + PI = EMI – These disciplines are no longer independent