EMT 367 Microelectronic fabrication - portal.unimap.edu.myportal.unimap.edu.my/portal/page/portal30/Lecture Notes/KEJURUTERAAN... · EMT 367 : Microelectronic Fabrication Sem 2 2017/18

EMT 367Microelectronic

fabrication

LECTURE 5 CMOS ISOLATION

TECHNOLOGY

Lecture Outline1. Understand why isolation is needed in

CMOS process2. Understand the isolation requirements

and related design rules3. Able to describe wafer cross section, the

process steps for Semi Recessed LOCOS,Fully Recessed LOCOS and ShallowTrench Isolation (STI).

4. Issues in LOCOS isolation such as bird’sbeak length (active areaencroachment) and Kooi’s Effect.

EMT 367 : Microelectronic Fabrication Sem 2 2017/18

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Main Process Modules (CMOS 1P2M 3.3V)1. Wells Formation2. Active Area Definition 3. Device Isolation (LOCOS)4. Vt Adjust5. Polygate Definition6. Source & Drain Formation7. Pre Metal Dielectrics Deposition (PMD)8. Contact Definition9. Metal-1 Deposition & Patterning10.Inter-Metal Dielectrics Deposition (IMD)11.Via Definition12.Metal-2 Deposition & Patterning13.Passivation14.Pad Definition

Full integration may require 300-500 process steps

FRONT END PROCESS(creating an electrically isolated devices)

BACK END PROCESS(connecting the devices to form the desiredcircuit function.)

Standard CMOS Process Flow


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The threshold voltage of a MOSFET is defined as the gate voltage where an inversion region forms at the surface of the transistor’s channel.

p-well

n+ n+

VG

VD

VB = 0

p-well

n+ n+

VG = VT

VD

VB = 0

What is Threshold Voltage of MOS Transistor ?

Quick Review

Cross Section A to A”


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A A”Metal 1

Metal 1

Which one is Isolation part

?


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MOS device isolation PWELL NWELL

p+

p+n+

n+ n+

n+

n+

n+

n+

n+LW p+p+

p+p+

p+

p+

A

A’B B’Active

WellPolySi

Isolation

N+ S/DP+ S/D


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MOS device isolation PWELL NWELL

p+

p+n+

n+ n+

n+

n+

n+

n+

n+LW p+p+

p+p+

p+

p+

A

A’B B’Active

WellPolySi

Isolation

N+ S/DP+ S/D

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CROSS SECTION A TO A’ LINE

p-well

n+ n+n+n+

NMOSNMOS

Device with the similar polarity –simpler


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9CROSS SECTION

B TO B’ LINE

n or p-substrate

p-well

p+n+

PMOSNMOS

n-well

Device with the different polarity – more complicated


• VTF is the threshold (minimum) voltage to turn on the parasitic MOS (field transistor)

• VTF is normally at least 8 V above supply voltage to ensure less than 1 pA/um between isolated MOS device

• 2 methods of increasing the VTF;• making a thicker field oxide• Increase the doping beneath field oxide (channel stop

implant)

NMOS#2

DRAIN SOURCE

NMOS#1

Field transistorM-1

LOCOS


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Why MOS device isolation is needed?

Isolation Requirement11

1. Source-substrate and drain-substrate pn junctions are held at reverse bias

2. Unwanted channels are prevented from forming among adjacent devices

NMOS#2

DRAIN SOURCE

NMOS#1


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4. Electric circuit in VLSI technology is implemented by connecting isolated devices through specific conducting path.

5. To fabricate monolithic ICs, electrically isolated devices must be created in the silicon substrate and connected at a later stage

6. Improper isolated device will result:• total circuit failure• high leakage (large dc power dissipation)• noise margin degradation• voltage shift, cross talk between transistors and etc.


137. The challenge is VLSI device only

allows single transistor leakage < 10 pA/um. On the other hand, process integration imposed a stringent requirement on the isolation technology:• spacing between actives should be as small as possible• to produce the surface topography as planar as possible• isolation process module must be simple to implement and easy to control


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poly polyn+ n+n+ n+ Aluminum


Test Structures for NMOS Isolation

MOS Device Isolation Characterization

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1) The purpose;• To find the VTF : The gate voltage at which the maximum allowable leakage current arise• To find the optimum n+ to n+ spacing

2) Gate voltage (VTF) at drain current @ 1nA or 1pA, at VD = Vcc, is measured

3) VTF is plotted against n+ to n+ spacing to find the optimum n+ to n+ at certain VDS values


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VTF

5

10

15

20

25Volts

0.1 u A

1 n A10 p A

n+ to n+ spacing in micron0.5 1 1.5 2 2.5 3 3.5 4

Channel current


MOS Device Isolation Technique


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1) Grow and etch thick oxide (1970) 2) Locos isolation technology

§ Semi recessed LOCOS (1980)ü Basic LOCOSü Poly bufferedü SILO and etc

§ Fully recessed LOCOS (1980)ü Side Wall Mask Isolation (SWAMI)ü Self Aligned Planar Oxidation (SPOT)ü FUROX (Fully Recessed Oxide)

3) Shallow Trench (STI) (1990)4) SOI + STI (2000)


18 (A) Grow and Etch Technique

substrate

substrate

a) Grow thick oxide

b) Pattern and etch

c) S/D diffusion

Overview on CMOS Isolation Techniques


19A) Grow and etch (used until late 70s)

• Thick oxide is grown thermally in the furnace• Wafer is patterned and etch

Disadvantages

• Sharp corners, difficult to cover in the latter process steps

• Channel stop must be implanted before oxide is grown (active to be aligned with channel stop region – low packing density)


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oxidation

nitride removal

oxidation

nitride removal

a) Semi recessed LOCOS

b) Fully recessed LOCOS

Overview on CMOS Isolation Techniques

(B) LOCOS Isolation Technology

Basic Semi-recessed LOCOS Process

Silicon substrate


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Step-1: Pad Oxide Layer• Wafer is cleaned using RCA cleaning technique• 200-500A SiO2 (called pad or buffer oxide) is thermally grown• The function of this oxide is to cushion the transition of stress between the silicon substrate and the subsequently deposited nitride.

Silicon substrate


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Step-2: Silicon Nitride Layer

• 1000-2000A thick layer of CVD silicon nitride is deposited.• The function of this nitride is as mask to the oxidation process.• Silicon nitride is very effective as oxidation mask because oxygen and water vapor diffuse very slowly through it, preventing oxidising species from reaching the silicon surface under the nitride.• Silicon nitride however exhibiting a very high tensile stress (1010 dynes/cm2), hence used with minimal thickness.

Silicon substrate Silicon substrate


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Step-3: Photolithography-Active Area DefinitionTo define the active area (where the transistors to be put)

Step-4: Nitride Etch

• To cover the active regions, expose areas to form LOCOS

Silicon substrate


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Silicon substrate


25Step-5: Channel stop implant• To create a channel stop doping layer under Field Oxide.• In NMOS circuit, a p implant (boron, 60-100 keV) is used, while in PMOS, arsenic is used.• PR is removed after the implant•


26Step-6: Grow Field Oxide•Field oxide is thermally grown by wet oxidation at temperatures around 1000 C to the thickness 8000-10,000A. •Oxide will grows where there is no masking nitride, but at the nitride’s edges, some oxidation occurred.•This caused the nitride’s edges to lift. Because of the shape, this structure is called bird’s beak.

Silicon substrate

Nitride layer

Boron

Oxide layer

ORIGINAL MASK

BIRD’S BEAK

FINAL ACTIVEAREA

8000 A

5000 A


27 • The bird’s beak is a lateral extension of the field oxide into the active area of the devices.

• For a typical 8000A LOCOS, bird’s beak ~ 5000A. Limiting factor for the usage of LOCOS.

Step-7: Strip Masking Nitride Layer• Oxynitride etch (200-300 A top layer of

nitride) – deglaze process• Wet hot phosphoric process to remove

nitride (good selectivity to oxide)• Tricky process, deglaze process must be

carefully characterized.

Silicon substrate


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Step-8: Regrow and strip sacrificial oxide• Kooi et al discovered that a thin layer of silicon nitride

can form on the silicon surface (pad oxide – silicon interface).

• This nitride spot is called white ribbon or Kooi Effect and must be removed to prevent defect from occurring when growing gate oxide.

• This can be done by regrown a pad oxide and subsequently removed.

Factors Affecting Bird’s Beak Length and Shape

1) Pad oxide thicknessLateral oxidation can be reduced by using a thinner pad oxide, leading to a shorter bird’s beak.

2) Pad layer composition – CVD oxynitride3) Silicon crystal orientation – shorter bird’s

beak in <111> compared to <100>.4) Field oxide process temperature – Shorter

with higher oxidation temperature.5) Thickness and mechanical properties of nitride layer – the thicker the nitride, the shorter the bird’s beak


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Advanced Semi-Recessed LOCOS Process

• Based on the fact that a thinner pad oxide will produce a shorter bird’s beak.• Usual pad oxide is replaced with a poly-buffered layer; poly 500 A : oxide 100 A• Thicker nitride is used to suppress the bird’s beak more, 1000 – 2500 A

A) Poly Buffered LOCOS

B) Sealed Interface LOCOS

• Reduce the bird’s beak by depositing nitride layer directly onto the silicon.• Lateral diffusion of oxidants is suppressed better, resulting a shorter bird’s beak.


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Basic Fully-recessed LOCOS Process

Step-1: Pad Oxide Layer

• Wafer is cleaned using RCA cleaning technique• 200-500 A SiO2 (called pad or buffer oxide) is thermally grown• The function of this oxide is to cushion the transition of stress between

the silicon substrate and the subsequently deposited nitride.

Silicon substrate


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Step-2: Silicon Nitride Layer

• 1000 - 2000 A thick layer of CVD silicon nitride is deposited.• The function of this nitride is as mask to the oxidation process.• Silicon nitride is very effective as oxidation mask because oxygen and water

vapor diffuse very slowly through it, preventing oxidizing species from reaching

the silicon surface under the nitride.• Silicon nitride however exhibiting a very high tensile stress (1010 dynes/cm2), hence used with minimal thickness.

Silicon substrate


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Step-3: Photolithography-Active Area Definition

• To define the active area (where the transistors to be put)

Silicon substrate Silicon substrate


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Step-4: Nitride Etch, Oxide Etch, Silicon Etch

• To cover the active regions, expose areas to form LOCOS

Silicon substrate


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Step-5: Channel stop implant

• To create a channel stop doping layer under Field Oxide. • In NMOS circuit, a p implant (boron, 60-100 keV) is used, while in PMOS, arsenic is used.• PR is removed after the implant

Silicon substrate


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Step-6: Grow Field Oxide

• Field oxide is thermally grown by wet oxidation at temperatures around 1000 C to the

thickness 8000-10,000 A.

• Oxide will grows where there is no masking nitride, but at the nitride’s edges, some

oxidation occurred.

• This caused the nitride’s edges to lift. Because of the shape, this structure is called

bird’s beak.

BIRD’S BEAK

BIRD’S HEAD


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SEM picture of Fully-Recessed LOCOS


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Step-7: Strip Masking Nitride Layer

• Oxynitride etch (200-300A top layer of nitride) – deglaze process• Wet hot phosphoric process to remove nitride (good selectivity to oxide)• Tricky process, deglaze process must be carefully characterized.

Step-8: Regrow and strip sacrificial oxide

• Kooi et al discovered that a thin layer of silicon nitride can form on the silicon surface

(pad oxide – silicon interface).• This nitride spot is called white ribbon or Kooi Effect and must be removed to prevent

defect from occuring when growing gate oxide.• This can be done by regrown a pad oxide and subsequently removed.


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Advanced Fully-Recessed LOCOS Process

A) Side Wall Masked Isolation (SWAMI)• Bird’s beak free structure, very planar process

Silicon substrate

1. Pad Oxidation2. CVD Nitride Deposition


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3. Oxide / Nitride Etch4. Silicon Etch

Sloping sidewall, help to reducethe stress during oxidation


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5. Second layer of pad oxide and nitride

6. CVD Oxide


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7. Etch Oxide, Etch Nitride

8. Field Oxidation

ActiveLOCOS

9. Nitride / Oxide strip


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B) Self Aligned Planar Oxidation Technology (SPOT)

• Another modified fully-recessed LOCOS to eliminate the bird’s beak and head.

• Conventional semi-recessed LOCOS is grown using high pressure oxidation.

• The LOCOS then removed using BOE

SiO2


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• Second pad oxide is grown, followed by deposition of a second CVD nitride

• Nitride and oxide then anisotropically etched.

LOCOS

• Second LOCOS is then grown using High Pressure Oxidation


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C) Fully Recessed Oxide (FUROX)

D) OSELO


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4 major applications• Locos replacement for isolation within the well

(STI)• Isolation in bipolar (Moderate Trench)• Latch prevention in CMOS (Moderate Trench)• Trench capacitor in DRAM (Deep Trench)

3 categories• Shallow trench <1 um• Moderate 1-3 um• Deep > 3 um deep

Trench Isolation Technology

AdvantagesIncrease the packing density tremendously

DisadvantagesComplex to fabricate, very expensive machines,

poor uniformity, low throughput, EMT 367 : Microelectronic Fabrication Sem 2 2017/18

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Trench etched

CVD oxide deposited

Oxide polished to surfaceby CMP.


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Shallow Trench Isolation (STI)


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Silicon On Insulator (SOI) with STI Isolation Technology

• Completely isolate the transistor on silicon surface from the bulk silicon substrate.

• Tremendously increase the packing density of IC chip

• Mainstream isolation technology for high performance ICs for feature size below

0.13 um process technology

• Normally coupled with Copper Interconnect Technology and Low-k InterlevelDielectric.


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THANK YOU


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Documents

EMT 367 Microelectronic fabrication - portal.unimap.edu.myportal.unimap.edu.my/portal/page/portal30/Lecture Notes/KEJURUTERAAN... · EMT 367 : Microelectronic Fabrication Sem 2 2017/18