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CHAPTER 1

INTRODUCTION:

1.1 OVER VIEW OF THE PROJET

The one main problem continuously follows the whole world

that’s power demand. The developed and developing nations concern it

and searching the way of reduce the power demand, because most of the

 power plant based on thermal and atomics, has one of the major problem

that lot of fuel requirement.

 

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1.2 BLOCK DIAGRAM OF THE PROJECT

FIG 1.2 BLOCK DIAGRAM OF PROJECT

CHAPTER 2

2

Power Supply

Battery voltage

monitor Microcontroller MOSFET Driver

MOSFET

Step UpTransformer

zo electric

stals

Regulation and

 battery circuit

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POWER MODULES

2.1 POWER SUPPLY

Since all electronic circuits work only with low D.C. voltage we need a power 

supply unit to provide the appropriate voltage supply. This unit consists of 

transformer, rectifier, filter and regulator. A.C. voltage typically 230V rms is

connected to a transformer which steps that AC voltage down to the level to the

desired AC voltage. A diode rectifier then provides a full-wave rectified voltage

that is initially filtered byA a simple capacitor filter to produce a DC voltage. This

resulting DC voltage usually has some ripple or AC voltage variations. regulator 

circuit can use this DC input to provide DC voltage that not only has much less

ripple voltage but also remains the same DC value even the DC voltage varies

some what, or the load connected to the output DC voltage changes. The power 

supply unit is a source of constant DC supply voltage. The required DC supply is

obtained from the available AC supply after rectification, filtration and regulation.

BLOCK DIAGRAM

 FIG 2.1 POWER SUPPLY BLOCK DIAGRAM

3

Transformer Rectifier Filter Regulator  230V

AC

12VAC

12VDC

12VDC

5VDC

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2.2 POWER SUPPLY CIRCUIT DIAGRAM

FIG: 2.2 POWER SUPPLY CIRCUIT DIAGRAM

2.2.1 PESCRIPTION OF POWER SUPPLY UNIT

The main components used in the power supply unit shown in fig 5.5 into dc

 power through the diodes. Here the bridge diode is used to are Transformer,

Rectifier, Filter, and Regulator. The 230V ac supply is converted into 12V ac

supply through the transformer. The output of the transformer has the same

frequency as in the input ac power. This ac power is converted convert the ac

supply to the dc power supply. This converted dc power supply has the ripple

content and for the normal operation of the circuit, the ripple content of the dc power supply should be as low as possible. Because the ripple content of the power 

supply will reduce the life of circuit.

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So to reduce the ripple content of the dc power supply, the filter is used. The

filter is nothing but the large value capacitance. The output waveform of the filter 

capacitance will almost be the straight line.

This filtered output will not be the regulated voltage. For the normal

operation of the circuit it should have the regulated output. Specifically for the

microcontroller IC regulated constant 5V output voltage should be given. For this

 purpose 78xx regulator should be used in the circuit. In that number of IC, the 8

represents the positive voltage and if it is 9, it will represent the negative voltage.

The xx represents the voltage. If it is 7805, it represent 5V regulator, and if it is

7812, it represent 12V regulator. Thus the regulated constant output can be

obtained. The brief description of the blocks above is as follows.

RECTIFIER 

A rectifier is a device such as a semiconductor capable of converting

sinusoidal input waveform units into a unidirectional waveform, with a non-zero

average component

FILTERS

Capacitors are used as filters in the power supply unit. Shunting the load

with the capacitor, effects filtering. The action of the system depends upon the fact

the capacitor stores energy during the conduction period and delivers this energy to

the load during the inverse or non-conducting period. In this way, time duringwhich the current passes through the load is prolonged and ripple is considerably

reduced.

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2.3 FIXED VOLTAGE REGULATOR  

An IC7805 fixed voltage regulator is used in this circuit. The function of this

regulator is to provide a +5V constant DC supply, even if there are fluctuations to

the regulator input. This regulator helps to maintain a constant voltage throughout

the circuit operation.

FIG: 2.3 FIXED VOLTAGE REGULATOR 

2.4 TRANSFORMER 

Transformer is a device used either for stepping-up or stepping-down of the

AC supply voltage with a corresponding decreases or increases in the current.

Here, a center-tapped transformer is used for stepping-down the voltage so as to

get a voltage that can be regulated to get a constant 12V. In this project, to satisfy

these requirements, we make use of 1.0A, 12V-0-12V transformer.

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2.4.1 POTENTIAL TRANSFORMER 

Voltage transformers (VT) or potential transformers (PT) are another type of 

instrument transformer, used for metering and protection in high-voltage circuits.

They are designed to present negligible load to the supply being measured and to

have a precise voltage ratio to accurately step down high voltages so that metering

and protective relay equipment can be operated at a lower potential. Typically the

secondary of a voltage transformer is rated for 69 V or 120 V at rated primary

voltage, to match the input ratings of protection relays.

The transformer winding high-voltage connection points are typically

labeled as H1, H2 (sometimes H0 if it is internally grounded) and X1, X2 and

sometimes an X3 tap may be present. Sometimes a second isolated winding (Y1, Y2,

Y3) may also be available on the same voltage transformer. The high side (primary)

may be connected phase to ground or phase to phase. The low side (secondary) is

usually phase to ground.

The terminal identifications (H1, X1, Y1, etc.) are often referred to as

 polarity. This applies to current transformers as well. At any instant terminals with

the same suffix numeral have the same polarity and phase. Correct identification of 

terminals and wiring is essential for proper operation of metering and protection

relays.

While VTs were formerly used for all voltages greater than 240 V primary,

modern meters eliminate the need VTs for most secondary service voltages. VTs

are typically used in circuits where the system voltage level is above 600 V.

Modern meters eliminate the need of VT's since the voltage remains constant and it

is measured in the incoming supply.

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2.4.2 CURRENT TRANSFORMER 

FIG: 2.4.2 CURRENT TRANSFORMER 

A current transformer (CT) is a type of instrument transformer designed to

 provide a current in its secondary winding proportional to the alternating current

flowing in its primary. They are commonly used in metering and protective

relaying in the electrical voltages where they facilitate the safe measurement of 

large currents, often in the presence of high voltages. The current transformer 

safely isolates measurement and control circuitry from the high voltages typically

 present on the circuit being measured.

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CHAPTER NO 3:

PIC MICROCONTROLLER 

3.1 MICROCONTROLLER – AN OVERVIEW

PIC is a family of Harvard architecture microcontrollers made by Microchip

Technology, derived from the PIC1640 originally developed by General

Instrument's Microelectronics Division. The name PIC initially referred to

"Peripheral Interface Controller".

PICs are popular with developers and hobbyists alike due to their low cost,

wide availability, large user base, extensive collection of application notes,

availability of low cost or free development tools, and serial programming (and re-

 programming with flash memory) capability.

Separate code and data spaces (Harvard architecture)

A small number of fixed length instructions

Most instructions are single cycle execution (4 clock cycles), with single

delay cycles upon branches and skips

A single accumulator (W), the use of which (as source operand) is implied

(i.e. is not encoded in the opcode)

All RAM locations function as registers as both source and/or destination of 

math and other functions.

A hardware stack for storing return addresses

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A fairly small amount of addressable data space (typically 256 bytes),

extended through banking

Data space mapped CPU, port, and peripheral registers

Unlike most other CPUs, there is no distinction between memory space and

register space because the RAM serves the job of both memory and registers, and

the RAM is usually just referred to as the register file or simply as the registers.

3.2 ARCHITECTURE OF PIC MICRO CONTROLLER 

DATA SPACE (RAM)

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FIG 3.1 ARCHITECTURE OF PIC MICRO CONTROLLER 

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PICs have a set of registers that function as general purpose RAM. Special

 purpose control registers for on-chip hardware resources are also mapped into the

data space. The addressability of memory varies depending on device series, and

all PIC devices have some banking mechanism to extend the addressing to

additional memory. Later series of devices feature move instructions which can

cover the whole addressable space, independent of the selected bank. In earlier 

devices (i.e., the baseline and mid-range cores), any register move had to be

achieved via the accumulator.

To implement indirect addressing, a "file select register" (FSR) and "indirect

register" (INDF) are used: A register number is written to the FSR, after which

reads from or writes to INDF will actually be to or from the register pointed to by

FSR. Later devices extended this concept with post- and pre- increment/decrement

for greater efficiency in accessing sequentially stored data. This also allows FSR to

 be treated almost like a stack pointer.

CODE SPACE

All PICs feature Harvard architecture, so the code space and the data space

are separate. PIC code space is generally implemented as EPROM, ROM, or flash

ROM.

In general, external code memory is not directly addressable due to the lack of an external memory interface. The exceptions are PIC17 and select high pin

count PIC18 devices

WORD SIZE

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The word size of PICs can be a source of confusion. All PICs handle (and

address) data in 8-bit chunks, so they should be called 8-bit microcontrollers.

However, the unit of addressability of the code space is not generally the

same as the data space. For example, PICs in the baseline and mid-range families

have program memory addressable in the same word size as the instruction width,

ie. 12 or 14 bits respectively. In contrast, in the PIC18 series, the program memory

is addressed in 8-bit increments (bytes), which differs from the instruction width of 

16 bits.

In order to be clear, the program memory capacity is usually stated in

number of (single word) instructions, rather than in bytes.

STACKS

PICs have a hardware call stack, which is used to save return addresses. The

hardware stack is not software accessible on earlier devices, but this changed with

the 18 series devices.

Hardware support for a general purpose parameter stack was lacking in early

series, but this greatly improved in the 18 series, making the 18 series architecture

friendlier to high level language compilers.

INSTRUCTION SET

A PIC's instructions vary from about 35 instructions for the low-end PICs to

over 80 instructions for the high-end PICs. The instruction set includes instructionsto perform a variety of operations on registers directly, the accumulator and a

literal constant or the accumulator and a register, as well as for conditional

execution, and program branching.

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Some operations, such as bit setting and testing, can be performed on any

numbered register, but bi-operand arithmetic operations always involve W; writing

the result back to either W or the other operand register. To load a constant, it is

necessary to load it into W before it can be moved into another register. On the

older cores, all register moves needed to pass through W, but this changed on the

"high end" cores.

PIC cores have skip instructions which are used for conditional execution

and branching. The skip instructions are: 'skip if bit set', and, 'skip if bit not set'.

Because cores before PIC18 had only unconditional branch instructions,

conditional jumps are implemented by a conditional skip (with the opposite

condition) followed by an unconditional branch. Skips are also of utility for 

conditional execution of any immediate single following instruction.

The PIC architecture has no (or very meager) hardware support for 

automatically saving processor state when servicing interrupts.

PIC INSTRUCTIONS FALL INTO 5 CLASSES

Operation on W with 8-bit immediate ("literal") operand. E.g. movlw (move

literal to W), andlw (AND literal with W). One instruction peculiar to the PIC is

retlw, load immediate into W and return, which is used with computed branches to

 produce lookup tables.

Operation with W and indexed register. The result can be written to either 

the W register (e.g. addwf reg,w). or the selected register (e.g. addwf reg,f).

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Bit operations. These take a register number and a bit number, and perform

one of 4 actions: set or clear a bit, and test and skip on set/clear. The latter are used

to perform conditional branches. The usual ALU status flags are available in a

numbered register so operations such as "branch on carry clear" are

 possible.Control transfers. Other than the skip instructions previously mentioned,

there are only two: goto and call. A few miscellaneous zero-operand instructions,

such as return from subroutine, and sleep to enter low-power mode.

3.3 PERFORMANCE

Many of these architectural decisions are directed at the maximization of 

top-end speed, or more precisely of speed-to-cost ratio. The PIC architecture was

among the first scalar CPU designs, and is still among the simplest and cheapest.

The Harvard architecture - in which instructions and data come from conveniently

separate sources - simplifies timing and microcircuit design greatly, and this pays

 benefits in areas like clock speed, price, and power consumption.

The PIC is particularly suited to implementation of fast lookup tables in the

 program space. Such lookups are O(1) and can complete via a single instruction

taking two instruction cycles. Basically any function can be modelled in this way.

Such optimization is facilitated by the relatively large program space of the PIC

(e.g. 4096 x 14-bit words on the 16F690) and by the design of the instruction set,

which allows for embedded constants.

The simplicity of the PIC, and its scalar nature, also serve to greatly simplify

the construction of real-time code. It is typically possible to multiply the line count

of a PIC assembler listing by the instruction cycle time to determine execution

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time. (This is true because skip-based instructions take 2 cycles whether the skip

occurs or doesn't.) On other CPUs (even the Atmel, with its MUL instruction),

such quick methods are just not possible. In low-level development, precise timing

is often critical to the success of the application, and the real-time features of the

PIC can save crucial engineering time.

A similarly useful and unique property of PICs is that their interrupt latency

is constant (it's also low: 3 instruction cycles). The delay is constant even though

instructions can take one or two instruction cycles: a dead cycle is optionally

inserted into the interrupt response sequence to make this true. External interrupts

have to be synchronized with the four clock instruction cycle, therwise there can be

a one instruction cycle jitter. Internal interrupts are already synchronized.

The three-cycle latency is increased in practice because the PIC does not

store its registers when entering the interrupt routine. Typically, 4 instructions are

needed to store the W-register, the status register and switch to a specific bank 

 before starting the actual interrupt processing.

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3.4 LIMITATIONS

THE PIC ARCHITECTURES HAVE SEVERAL LIMITATIONS

Only a single accumulator 

A small instruction set

Operations and registers are not orthogonal; some instructions can address

RAM and/or immediate constants, while others can only use the

accumulator 

Memory must be directly referenced in arithmetic and logic operations,

although indirect addressing is available via 2 additional registers

Register-bank switching is required to access the entire RAM of many

devices, making position-independent code complex and inefficient

Conditional skip instructions are used instead of conditional jump

instructions used by most other architectures

The following limitations have been addressed in the PIC18, but still apply

to earlier cores:

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COMPILER DEVELOPMENT

These properties have made it difficult to develop compilers that target PIC

microcontrollers. While several commercial compilers are available, in 2008,

Microchip finally released their C compilers, C18, and C30 for their line of 18f 24f 

and 30/33f processors. By contrast, Atmel's AVR  microcontrollers—which are

competitive with PIC in terms of hardware capabilities and price, but feature a

RISC instruction set—have long been supported by the GNU C Compiler .

Also, because of these properties, PIC assembly language code can be

difficult to comprehend. Judicious use of simple macros can make PIC assembly

language much more palatable, but at the cost of a reduction in performance. For 

example, the original Parallax PIC assembler "pasm" has macros which hide W

and make the PIC look like a two-address machine. It has macro instructions like

"mov b,a" (move the data from address a to address b) and "add b,a" (add data

from address a to data in address b). It also hides the skip instructions by providing

three operand branch macro instructions such as "cjne a,b,dest" (compare a with b

and jump to dest if they are not equal).

3.5 FAMILY CORE ARCHITECTURAL DIFFERENCES

3.5.1 BASELINE CORE DEVICES

These devices feature a 12-bit wide code memory, a 32-byte register file,

and a tiny two level deep call stack. They are represented by the PIC10 series, as

well as by some PIC12 and PIC16 devices. Baseline devices are available in 6-pin

to 40-pin packages.

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Generally the first 7 to 9 bytes of the register file are special-purpose

registers, and the remaining bytes are general purpose RAM. If banked RAM is

implemented, the bank number is selected by the high 3 bits of the FSR. this

affects register numbers 16–31; registers 0–15 are global and not affected by the

 bank select bits

The ROM address space is 512 words (12 bits each), which may be extended

to 2048 words by banking. CALL and GOTO instructions specify the low 9 bits of 

the new code location; additional high-order bits are taken from the staus register.

 Note that a CALL instruction only includes 8 bits of address, and may only specify

addresses in the first half of each 512-word page.

The instruction set is as follows. Register numbers are referred to as "f",

while constants are referred to as "k". Bit numbers (0–7) are selected by "b". The

"d" bit selects the destination: 0 indicates W, while 1 indicates that the result is

written back to source register.

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3.5 12- BIT PIC INSTRUCTION SET

12-BIT PIC INSTRUCTION SET

OPCODE

(BINARY)

MNEMONIC DESCRIPTION

0000 0000 0000 NOP No operation

0000 0000 0010 OPTION Load OPTION register with contents of W

0000 0000 0011 SLEEP Go into standby mode

0000 0000 0100 CLRWDT Reset watchdog timer  

0000 0000 01ff TRIS f Move W to port control register (f=1..3)

0000 001 fffff MOVWF f Move W to f  

0000 010 xxxxx CLRW Clear W to 0 (a.k.a CLR x,W)

0000 011 fffff CLRF f Clear f to 0 (a.k.a. CLR f,F)

0000 10d fffff SUBWF f,d Subtract W from f (d = f − W)

0000 11d fffff DECF f,d Decrement f (d = f − 1)

0001 00d fffff IORWF f,d Inclusive OR W with F (d = f OR W)

0001 01d fffff ANDWF f,d AND W with F (d = f AND W)

0001 10d fffff XORWF f,d Exclusive OR W with F (d = f XOR W)

0001 11d fffff ADDWF f,d Add W with F (d = f + W)

0010 00d fffff MOVF f,d Move F (d = f)

0010 01d fffff COMF f,d Complement f (d = NOT f)

0010 10d fffff INCF f,d Increment f (d = f + 1)

0010 11d fffff DECFSZ f,d Decrement f (d = f − 1) and skip if zero

0011 00d fffff RRF f,d Rotate right F (rotate right through carry)

0011 01d fffff RLF f,d Rotate left F (rotate left through carry)

0011 10d fffff SWAPF f,d Swap 4-bit halves of f (d = f<<4 | f>>4)

0011 11d fffff INCFSZ f,d Increment f (d = f + 1) and skip if zero

0100 bbb fffff BCF f,b Bit clear f (Clear bit b of f)

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0101 bbb fffff BSF f,b Bit set f (Set bit b of f)

0110 bbb fffff BTFSC f,b Bit test f, skip if clear (Test bit b of f)

0111 bbb fffff BTFSS f,b Bit test f, skip if set (Test bit b of f)

1000 kkkkkkkk RETLW k Set W to k and return

1001 kkkkkkkk CALL k Save return address, load PC with k  

101 kkkkkkkkk GOTO k Jump to address k (9 bits!)

1100 kkkkkkkk MOVLW k Move literal to W (W = k)

1101 kkkkkkkk IORLW k Inclusive or literal with W (W = k OR W)

1110 kkkkkkkk ANDLW k AND literal with W (W = k AND W)

1111 kkkkkkkk XORLW k Exclusive or literal with W (W = k XOR W)

 

3.5 TABULATION OF 12- BIT PIC INSTRUCTION SET

3.6 MID-RANGE CORE DEVICES

These devices feature a 14-bit wide code memory, and an improved 8 level

deep call stack. The instruction set differs very little from the baseline devices, but

the increased opcode width allows 128 registers and 2048 words of code to bedirectly addressed. The mid-range core is available in the majority of devices

labeled PIC12 and PIC16.

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The first 32 bytes of the register space are allocated to special-purpose

registers; the remaining 96 bytes are used for general-purpose RAM. If banked

RAM is used, the high 16 registers (0x70–0x7F) are global, as are a few of the

most important special-purpose registers, including the STATUS register which

holds the RAM bank select bits. (The other global registers are FSR and INDF, the

low 8 bits of the program counter PCL, the PC high preload register PCLATH, and

the master interrupt control register INTCON.)

The PCLATH register supplies high-order instruction address bits when the

8 bits supplied by a write to the PCL register, or the 11 bits supplied by a GOTO or 

CALL instruction, is not sufficient to address the available ROM space.

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3.7 14 BIT INSTRUCTION SET

14 BIT PIC INSTRUCTION SET

OPCODE

(BINARY)MNEMONICDESCRIPTION

00 0000 0000 0000 NOP No operation

00 0000 0000 1000 RETURN Return from subroutine, W unchanged

00 0000 0000 1001 RETFIE Return from interrupt

00 0000 0110 0010 OPTION Write W to OPTION register 

00 0000 0110 0011 SLEEP Go into standby mode

00 0000 0110 0100 CLRWDT Reset watchdog timer 

00 0000 0110 01ff TRIS f 

00 0000 1 fffffff MOVWF f Move W to f  

00 0001 0 xxxxxxx CLRW Clear W to 0 (W = 0)

00 0001 1 fffffff CLRF f Clear f to 0 (f = 0)

00 0010 d fffffff SUBWF f,d Subtract W from f (d = f − W)

00 0011 d fffffff DECF f,d Decrement f (d = f − 1)

00 0100 d fffffff IORWF f,d Inclusive OR W with F (d = f OR W)

00 0101 d fffffff ANDWF f,d AND W with F (d = f AND W)

00 0110 d fffffff XORWF f,d Exclusive OR W with F (d = f XOR W)

00 0111 d fffffff ADDWF f,d Add W with F (d = f + W)

00 1000 d fffffff MOVF f,d Move F (d = f)

00 1001 d fffffff COMF f,d Complement f (d = NOT f)

00 1010 d fffffff INCF f,d Increment f (d = f + 1)

00 1011 d fffffff DECFSZ f,d Decrement f (d = f − 1) and skip if zero

00 1100 d fffffff RRF f,d Rotate right F (rotate right through carry)

00 1101 d fffffff RLF f,d Rotate left F (rotate left through carry)

00 1110 d fffffff SWAPF f,d Swap 4-bit halves of f (d = f<<4 | f>>4)

00 1111 d fffffff INCFSZ f,d Increment f (d = f + 1) and skip if zero

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01 00 bbb fffffff BCF f,b Bit clear f (Clear bit b of f)

01 01 bbb fffffff BSF f,b Bit set f (Set bit b of f)

01 10 bbb fffffff BTFSC f,b Bit test f, skip if clear (Test bit b of f)

01 11 bbb fffffff BTFSS f,b Bit test f, skip if set (Test bit b of f)10 0 kkkkkkkkkkk CALL k Save return address, load PC with k 

10 1 kkkkkkkkkkk GOTO k Jump to address k (11 bits)

11 00xx kkkkkkkk MOVLW k Move literal to W (W = k)

11 01xx kkkkkkkk RETLW k Set W to k and return

11 1000 kkkkkkkk IORLW k Inclusive or literal with W (W = k OR W)

11 1001 kkkkkkkk ANDLW k AND literal with W (W = k AND W)

11 1010 kkkkkkkk XORLW k Exclusive or literal with W (W = k XOR W)

11 110x kkkkkkkk SUBLW k Subtract W from literal (W = k − W)

11 111x kkkkkkkk ADDLW k Add literal to W (W = k + W)

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3.8 TABULATION OF 14 BIT INSTRUCTION SET

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3.8 PIC17 HIGH END CORE DEVICES

The 17 series never became popular and has been superseded by the PIC18

architecture. It is not recommended for new designs, and availability may be

limited.

Improvements over earlier cores are 16-bit wide opcodes (allowing many

new instructions), and a 16 level deep call stack. PIC17 devices were produced in

 packages from 40 to 68 pins.

3.8.1 IMPORTANT NEW FEATURES:

A memory mapped accumulator 

Read access to code memory (Table Reads)

Direct register to register moves (prior cores needed to move registers

through the accumulator)

An external program memory interface to expand the code space

An 8bit x 8bit hardware multiplier 

A second indirect register pair 

Auto-increment/decrement addressing controlled by control bits in a status

register (ALUSTA)

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3.9 PIC18 HIGH END CORE DEVICES

Microchip introduced the PIC18 architecture in 2002. Unlike the 17 series, it

has proven to be very popular, with a large number of device variants presently in

manufacture. In contrast to earlier devices, which were more often than not

 programmed in assembly, C has become the predominant development language

3.9.1 IMPORTANT NEW FEATURES

Much deeper call stack (31 levels deep)

The call stack may be read and written

Conditional branch instructions

Indexed addressing mode (Plusw)

Extending the fsr registers to 12 bits, allowing them to linearly address the

entire data address space

The addition of another FSR register (bringing the number up to 3)

The auto increment/decrement feature was improved by removing the

control bits and adding four new indirect registers per FSR. Depending on

which indirect file register is being accessed it is possible to post decrement,

 post increment, or preincrement FSR; or form the effective address by

adding W to FSR.

In more advanced PIC18 devices, an "extended mode" is available which

makes the addressing even more favorable to compiled code:

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a new offset addressing mode; some addresses which were relative to the

access bank are now interpreted relative to the FSR2 register 

the addition of several new instructions, notable for manipulating the FSR 

registers.

These changes were primarily aimed at improving the efficiency of a data

stack implementation. If FSR2 is used either as the stack pointer or frame

 pointer, stack items may be easily indexed—allowing more efficient re-

entrant code. Microchip C18 chooses to use FSR2 as a frame pointer.

3.10 PIC24 AND DSPIC 16-BIT MICROCONTROLLERS

In 2001, Microchip introduced the dsPIC series of chips, which entered mass

 production in late 2004. They are Microchip's first inherently 16-bit

microcontrollers. PIC24 devices are designed as general purpose microcontrollers.

dsPIC devices include digital signal processing capabilities in addition.

They feature a set of 16 working registers

They fully support a stack in ram, and do not have a hardware stack 

Bank switching is not required to access ram or special function registers

Data stored in program memory can be accessed directly using a feature

called program space visibility

Interrupt sources may be assigned to distinct handlers using an interruptvector table

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3.10.1 IMPORTANT NEW FEATURES 

 barrel shifting 

Bit reversal

(16×16)-bit multiplication and other dsp operations.

Hardware support for loop indexing

direct memory access 

Dspics can be programmed in c using a variant of gcc.

Pic32 32-bit microcontrollers

In November 2007 Microchip introduced the new PIC32MX family of 32-

 bit microcontrollers. The initial device line-up is based on the industry

standard MIPS32 M4K Core. The device can be programmed using the

Microchip MPLAB C Compiler for PIC32 MCUs, a variant of the GCC

compiler. The first 18 models currently in production (PIC32MX3xx and

PIC32MX4xx) are pin to pin compatible and share the same peripherals set

with the PIC24FxxGA0xx family of (16-bit) devices allowing the use of 

common libraries, software and hardware tools.

3.11 NEW FEATURES OF PIC 32 MICROCHIP

The highest execution speed 80 MIPS (90+ Dhrystone MIPS @80MHz)

The largest FLASH memory: 512kbyte

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One instruction per clock cycle execution

The first cached processor 

Allows execution from RAM

Full Speed Host/Dual Role and OTG USB capabilities

Full JTAG and 2 wire programming and debugging

Real-time trace

Device Variants and Hardware Features

3.12 SPECIAL FEATURES OF PIC MICRO CONTROLLER 

Sleep mode (power savings).

Watchdog timer .

Various crystal or RC oscillator configurations, or an external clock.

Variants

Within a series, there are still many device variants depending on what

hardware resources the chip features.

General purpose I/O pins.

Internal clock oscillators.

8/16/32 Bit Timers.

Internal EEPROM Memory.

Synchronous/Asynchronous Serial Interface USART.

MSSP Peripheral for I²C and SPI Communications.

Capture/Compare and PWM modules.

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Analog-to-digital converters (up to ~1.0 MHz).

USB, Ethernet, CAN interfacing support.

External memory interface.

And many more.

3.13 TRENDS

The first generation of PICs with EPROM storage are almost completely

replaced by chips with Flash memory. Likewise, the original 12-bit instruction set

of the PIC1650 and its direct descendants has been superseded by 14-bit and 16-bit

instruction sets. Microchip still sells OTP (one-time-programmable) and windowed

(UV-erasable) versions of some of its EPROM based PICs for legacy support or 

volume orders. It should be noted that the Microchip website lists PICs that are not

electrically erasable as OTP despite the fact that UV erasable windowed versions

of these chips can be ordered

.

3.14 DEVELOPMENT TOOLS

Microchip provides a freeware IDE package called MPLAB, which includes

an assembler, linker, software simulator , and debugger. They also sell C compilers

for the PIC18 and dsPIC which integrate cleanly with MPLAB. Free student

versions of the C compilers are also available with all features. But for the free

versions, optimizations will be disabled after 60 days.

Several third parties make C, BASIC  and Pascal language compilers for 

PICs, many of which integrate to MPLAB and/or feature their own IDE.

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A blockset for Matlab/Simulink allow one to generate C and binary files

from a simulink model. Most common peripherals have their blocksets and you do

not need to write the configuration code.

OPEN SOURCE

The following development tools are available for the PIC family under the

GPL or other free software or open sources licenses.

FreeRTOS is a mini real time kernel ported to PIC18, PIC24, dsPIC and

PIC32 architectures.

GPUTILS is free and available from the GPUTILS website.

GPSIM is an Open Source simulator for the PIC microcontrollers featuring

hardware modules that simulate specific devices that might be connected to

them, like LCDs.

SDCC supports 8-bit PIC micro controllers (PIC16, PIC18). Currently,

throughout the SDCC website, the words, "Work is in progress", are

frequently used to describe the status of SDCC's support for PICs.

KTechlab, a OpenSource microcontroller  IDE written in c++ and qt.

Ktechlab supports the programming of microcontrollers using C, Assembly,

Microbe (a BASIC-like language) and using flowcode a graphical

 programming language similar to Flowcode

Ktechlab is a free IDE for programming PIC Microcontroller. It allows one

to write the program in C, Assembly, Microbe (a BASIC-like language) and

using FlowChart Method.

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PiKdev runs on Linux and is a simple graphic IDE for the development of 

PIC-based applications. It currently supports assembly language. Non Open

Source C language is also supported for PIC 18 devices. PiKdev is

developed in C++ under Linux and is based on the KDE environment.

Piklab is a forked version of PiKdev and is managed as SourceForge Project.

Piklab adds to Pikdev by providing support for programmers and debuggers.

Currently, Piklab supports the JDM, PIC Elmer, K8048, HOODMICRO,

ICD1, ICD2, PICkit1, PICKkit2, and PicStart+ as programming devices and

has debugging support for ICD2 in addition to using the simulator, GPSim.

JAL stands for Just Another Language. It is a Pascal-like language that is

easily mastered. The compiler supports a few Microchip (16c84, 16f84,

12c508, 12c509, 16F877) and SX microcontrollers. The resulting assembly

language can then be viewed, modified and further processed as if you were

 programming directly in assembler.

PMP (Pic Micro Pascal) is a free Pascal language compiler and IDE. It is

intended to work with Microchip MPLAB that it uses device definition files,

assembler and linker. It supports PIC10 to PIC18 devices.

The GNU Compiler Collection and the GNU Binutils have been ported to

the PIC24, dsPIC30F and dsPIC33F in the form of Microchip's MPLAB C30 

compiler and MPLAB ASM30 Assembler.

MIOS is a real-time operating system written in PIC assembly, optimized for 

MIDI processing and other musical control applications. There is a C

wrapper for higher level development. Currently it runs on the MIDIbox 

Hardware Platform.

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FlashForth is a native Forth operating system for the PIC18F and the

dsPIC30F series. It makes the PIC a standalone computer with an

interpreter, compiler, assembler and multitasker.

CHAPTER NO 4:

MOSFET

Two power MOSFETs in the surface-mount package D2PAK . Operating as

switches, each of these components can sustain a blocking voltage of 120 volts in

the OFF state, and can conduct a continuous current of 30 amperes in the ON state,

dissipating up to about 100 watts and controlling a load of over 2000 watts. A

matchstick is pictured for scale.

A cross section through an nMOSFET when the gate voltage VGS is below the

threshold for making a conductive channel; there is little or no conduction between

the terminals source and drain; the switch is off. When the gate is more positive, it

attracts electrons, inducing an n-type conductive channel in the substrate below the

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oxide, which allows electrons to flow between the n-doped terminals; the switch is

on.

 

Simulation result for formation of inversion channel (electron density) and

attainment of threshold voltage (IV) in a nanowire MOSFET. Note that the

threshold voltage for this device lies around 0.45V.

The metal–oxide–semiconductor field-effect transistor (MOSFET, MOS-

FET, or MOS FET) is a transistor  used for amplifying or switching electronic

signals. The basic principle of this kind of  transistor was first proposed by Julius 

Edgar Lilienfeld in 1925. In MOSFETs, a voltage on the oxide-insulated gate

electrode can induce a conducting channel between the two other contacts called

source and drain. The channel can be of  n-type or   p-type (see article on

semiconductor devices), and is accordingly called an nMOSFET or a pMOSFET

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(also commonly nMOS, pMOS). It is by far the most common transistor  in both

digital and analog circuits, though the bipolar junction transistor was at one time

much more common.

The 'metal' in the name is now often a misnomer  because the previously

metal gate material is now often a layer of  polysilicon (polycrystalline silicon).

Aluminium had been the gate material until the mid 1970s, when polysilicon

 became dominant, due to its capability to form self-aligned gates. Metallic gates

are regaining popularity, since it is difficult to increase the speed of operation of 

transistors without metal gates.

IGFET is a related term meaning insulated-gate field-effect transistor, and is used

almost synonymously with MOSFET, being more accurate since many

"MOSFETs" use a gate that is not metal and a gate insulator that is not oxide.

Another synonym is MISFET for metal–insulator–semiconductor FET.

Composition

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Photomicrograph of two metal-gate MOSFETs in a test pattern. Probe pads for two

gates and three source/drain nodes are labeled.

Usually the semiconductor of choice is silicon, but some chip manufacturers, most

notably IBM and Intel, recently started using a chemical compound of silicon and

germanium (SiGe) in MOSFET channels. Unfortunately, many semiconductors

with better electrical properties than silicon, such as gallium arsenide, do not form

good semiconductor-to-insulator interfaces, thus are not suitable for MOSFETs.

Research continues on creating insulators with acceptable electrical characteristics

on other semiconductor material.

In order to overcome power consumption increase due to gate current leakage,

high-κ dielectric replaces silicon dioxide for the gate insulator, while metal gates

return by replacing polysilicon (see Intel announcement[1]).

The gate is separated from the channel by a thin insulating layer, traditionally of 

silicon dioxide and later of  silicon oxynitride. Some companies have started to

introduce a high-κ dielectric + metal gate combination in the 45 nanometer node.

When a voltage is applied between the gate and body terminals, the electric field

generated penetrates through the oxide and creates an "inversion layer" or 

"channel" at the semiconductor-insulator interface. The inversion channel is of the

same type, P-type or N-type, as the source and drain, thus it provides a channel

through which current can pass. Varying the voltage between the gate and body

modulates the conductivity of this layer and thereby controls the current flow

 between drain and source.

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Circuit symbols

P-channel

 N-channel

JFET

MOSFET

enh

MOSFET enh (no bulk)

MOSFET

dep

A variety of symbols are used for the MOSFET. The basic design is generally a

line for the channel with the source and drain leaving it at right angles and then

 bending back at right angles into the same direction as the channel. Sometimes

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three line segments are used for  enhancement mode and a solid line for depletion

mode. Another line is drawn parallel to the channel for the gate.

The bulk connection, if shown, is shown connected to the back of the

channel with an arrow indicating PMOS or NMOS. Arrows always point from P to

 N, so an NMOS (N-channel in P-well or P-substrate) has the arrow pointing in

(from the bulk to the channel). If the bulk is connected to the source (as is

generally the case with discrete devices) it is sometimes angled to meet up with the

source leaving the transistor. If the bulk is not shown (as is often the case in IC

design as they are generally common bulk) an inversion symbol is sometimes used

to indicate PMOS, alternatively an arrow on the source may be used in the same

way as for bipolar transistors (out for nMOS, in for pMOS).

Comparison of enhancement-mode and depletion-mode MOSFET symbols,

along with JFET symbols (drawn with source and drain ordered such that higher 

voltages appear higher on the page than lower voltages):

For the symbols in which the bulk, or body, terminal is shown, it is here

shown internally connected to the source. This is a typical configuration, but by no

means the only important configuration. In general, the MOSFET is a four-

terminal device, and in integrated circuits many of the MOSFETs share a body

connection, not necessarily connected to the source terminals of all the transistors.

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MOSFET operation

Example application of an N-Channel MOSFET. When the switch is pushed the

LED lights up.[2]

Metal–oxide–semiconductor structure on P-type silicon

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Metal–oxide–semiconductor structure

A traditional metal–oxide–semiconductor (MOS) structure is obtained by

growing a layer of  silicon dioxide (SiO2) on top of a silicon substrate and

depositing a layer of metal or  polycrystalline silicon (the latter is commonly used).

As the silicon dioxide is a dielectric material, its structure is equivalent to a planar 

capacitor , with one of the electrodes replaced by a semiconductor.

When a voltage is applied across a MOS structure, it modifies the distribution of 

charges in the semiconductor. If we consider a P-type semiconductor (with  N  A the

density of  acceptors,  p the density of holes;  p = N  A in neutral bulk), a positive

voltage, V GB, from gate to body (see figure) creates a depletion layer by forcing the

 positively charged holes away from the gate-insulator/semiconductor interface,

leaving exposed a carrier-free region of immobile, negatively charged acceptor 

ions (see doping (semiconductor)). If V GB is high enough, a high concentration of 

negative charge carriers forms in an inversion layer located in a thin layer next to

the interface between the semiconductor and the insulator. Unlike the MOSFET,

where the inversion layer electrons are supplied rapidly from the source/drain

electrodes, in the MOS capacitor they are produced much more slowly by thermal

generation through carrier generation and recombination centers in the depletion

region. Conventionally, the gate voltage at which the volume density of electrons

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in the inversion layer is the same as the volume density of holes in the body is

called the threshold voltage.

This structure with p-type body is the basis of the N-type MOSFET, which

requires the addition of an N-type source and drain regions.

MOSFET structure and channel formation

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Cross section of an NMOS without channel formed: OFF state

Cross section of an NMOS with channel formed: ON state

A metal–oxide–semiconductor field-effect transistor (MOSFET) is based

on the modulation of charge concentration by a MOS capacitance between a body

electrode and a gate electrode located above the body and insulated from all other 

device regions by a gate dielectric layer which in the case of a MOSFET is an

oxide, such as silicon dioxide. If dielectrics other than an oxide such as silicon

dioxide (often referred to as oxide) are employed the device may be referred to as a

metal–insulator–semiconductor FET (MISFET). Compared to the MOS capacitor,

the MOSFET includes two additional terminals (source and drain), each

connected to individual highly doped regions that are separated by the body region.

These regions can be either p or n type, but they must both be of the same type,

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and of opposite type to the body region. The source and drain (unlike the body) are

highly doped as signified by a '+' sign after the type of doping.

If the MOSFET is an n-channel or nMOS FET, then the source and drain

are 'n+' regions and the body is a 'p' region. As described above, with sufficient

gate voltage, holes from the body are driven away from the gate, forming an

inversion layer or n-channel at the interface between the p region and the oxide.

This conducting channel extends between the source and the drain, and current is

conducted through it when a voltage is applied between source and drain.

Increasing the voltage on the gate leads to a higher electron density in the inversion

layer and therefore increases the current flow between the source and drain.

For gate voltages below the threshold value, the channel is lightly

 populated, and only a very small subthreshold leakage current can flow between

the source and the drain.

If the MOSFET is a p-channel or pMOS FET, then the source and drain

are 'p+' regions and the body is a 'n' region. When a negative gate-source voltage

(positive source-gate) is applied, it creates a  p-channel  at the surface of the n

region, analogous to the n-channel case, but with opposite polarities of charges and

voltages. When a voltage less negative than the threshold value (a negative voltage

for p-channel) is applied between gate and source, the channel disappears and only

a very small subthreshold current can flow between the source and the drain.

The source is so named because it is the source of the charge carriers

(electrons for n-channel, holes for p-channel) that flow through the channel;

similarly, the drain is where the charge carriers leave the channel.

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The device may comprise a Silicon On Insulator (SOI) device in which a

Buried OXide (BOX) is formed below a thin semiconductor layer. If the channel

region between the gate dielectric and a Buried Oxide (BOX) region is very thin,

the very thin channel region is referred to as an Ultra Thin Channel (UTC) region

with the source and drain regions formed on either side thereof in and/or above the

thin semiconductor layer. Alternatively, the device may comprise a

SEMiconductor On Insulator (SEMOI) device in which semiconductors other than

silicon are employed. Many alternative semiconductor materials may be employed.

When the source and drain regions are formed above the channel in whole

or in part, they are referred to as Raised Source/Drain (RSD) regions.

Modes of operation

The operation of a MOSFET can be separated into three different modes,

depending on the voltages at the terminals. In the following discussion, a

simplified algebraic model is used that is accurate only for old technology. Modern

MOSFET characteristics require computer models that have rather more complex

 behavior.

For an enhancement-mode, n-channel MOSFET, the three operational modes

are:

Cutoff, subthreshold, or weak-inversion mode

When V GS  < V th: 

where V th is the threshold voltage of the device.

According to the basic threshold model, the transistor is turned off, and there is no

conduction between drain and source. In reality, the Boltzmann distribution of 

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electron energies allows some of the more energetic electrons at the source to enter 

the channel and flow to the drain, resulting in a subthreshold current that is an

exponential function of gate–source voltage. While the current between drain and

source should ideally be zero when the transistor is being used as a turned-off 

switch, there is a weak-inversion current, sometimes called subthreshold leakage.

In weak inversion the current varies exponentially with gate-to-source bias

V GS as given approximately by

,

where I  D0 = current at V GS  = V th, the thermal voltage V T  = kT / q and the slope factor 

n is given by

n = 1 + C  D / C OX ,

with C  D = capacitance of the depletion layer and C OX  = capacitance of the

oxide layer. In a long-channel device, there is no drain voltage dependence of the

current once V  DS  > > V T , but as channel length is reduced drain-induced barrier  

lowering introduces drain voltage dependence that depends in a complex way upon

the device geometry (for example, the channel doping, the junction doping and so

on). Frequently, threshold voltage Vth for this mode is defined as the gate voltage at

which a selected value of current ID0 occurs, for example, ID0 = 1 μA, which may

not be the same Vth-value used in the equations for the following modes.Some micropower analog circuits are designed to take advantage of 

subthreshold conduction.[5][6][7] By working in the weak-inversion region, the

MOSFETs in these circuits deliver the highest possible transconductance-to-

current ratio, namely: g m / I  D = 1 / (nV T ), almost that of a bipolar transistor.[8] 

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The subthreshold  I–V curve depends exponentially upon threshold voltage,

introducing a strong dependence on any manufacturing variation that affects

threshold voltage; for example: variations in oxide thickness, junction depth, or 

 body doping that change the degree of drain-induced barrier lowering. The

resulting sensitivity to fabricational variations complicates optimization for 

leakage and performance.[9][10] 

MOSFET drain current vs. drain-to-source voltage for several values of  V GS  − V th;

the boundary between linear (Ohmic) and saturation (active) modes is indicated

 by the upward curving parabola.

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Cross section of a MOSFET operating in the linear (Ohmic) region; strong

inversion region present even near drain

Cross section of a MOSFET operating in the saturation (active) region; channel

exhibits pinch-off near drain

Triode mode or linear region (also known as the ohmic mode[11][12])

When V GS > V th and V  DS  < ( V GS  – V th ) 

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The transistor is turned on, and a channel has been created which allows current to

flow between the drain and the source. The MOSFET operates like a resistor,

controlled by the gate voltage relative to both the source and drain voltages. The

current from drain to source is modeled as:

where μn is the charge-carrier effective mobility, W is the gate width, L is the gate

length and C ox is the gate oxide capacitance per unit area. The transition from the

exponential subthreshold region to the triode region is not as sharp as the equations

suggest.

Saturation or active mode

When V GS > V th and V  DS  > ( V GS  – V th ) 

The switch is turned on, and a channel has been created, which allows current to

flow between the drain and source. Since the drain voltage is higher than the gate

voltage, the electrons spread out, and conduction is not through a narrow channel

 but through a broader, two- or three-dimensional current distribution extending

away from the interface and deeper in the substrate. The onset of this region is also

known as pinch-off to indicate the lack of channel region near the drain. The drain

current is now weakly dependent upon drain voltage and controlled primarily by

the gate–source voltage, and modeled approximately as:

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The additional factor involving λ, the channel-length modulation parameter,

models current dependence on drain voltage due to the Early effect, or  channel 

length modulation. According to this equation, a key design parameter, the

MOSFET transconductance is:

,

where the combination V ov = V GS  – V th is called the overdrivevoltage,[15] and where

V  DSsat  = V GS  - V th (which Sedra neglects) accounts for a small discontinuity in  I  D

which would otherwise appear at the transition between the triode and saturation

regions.

Another key design parameter is the MOSFET output resistance r out given by:

.

r out  is the inverse of  g  DS  where . VDS is the expression in saturation

region.

If λ is taken as zero, an infinite output resistance of the device results that leads to

unrealistic circuit predictions, particularly in analog circuits.

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As the channel length becomes very short, these equations become quite

inaccurate. New physical effects arise. For example, carrier transport in the active

mode may become limited by velocity saturation. When velocity saturation

dominates, the saturation drain current is more nearly linear than quadratic in V GS .

At even shorter lengths, carriers transport with near zero scattering, known as

quasi- ballistic transport. In addition, the output current is affected by drain-induced

 barrier lowering of the threshold

CHAPTER 5:

BATTERY VOLTAGE MONITORING

INTRODUCTION:

This circuit is used to monitor the battery voltage, using a bi-color LED

to indicate the state of the battery. When the LED is "GREEN" the battery voltage

is above 11.9 volts. When the LED is "YELLOW", the battery voltage is between

11.9 and 11.5 volts. When the LED is "RED" the battery voltage is below 11.5

volts. You can of course, modify the trigger points by using the trimmer resistors

and/or changing the value of the dropping resistors in the divider.

A dual op amp is used as a voltage comparator. The green LED is on

so long as the voltage across the circuit is above 11.5 volts. The red LED comes on

when the voltage across the circuit drops to below 11.9 volts. Therefore, in the

11.9 to 11.5 volt range, both LED's are on, producing a some what yellow color.

When the voltage drops below 11.5 volts, the green LED turns off and now only

the red LED is on, indicating a low voltage condition.

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It is recommended that multi-turn trimmer be used for V1 and V2. Muti-turn

trimmer will make it much easier to set the trigger points than using a less

expensive single turn trimmer. The trimmers could be eliminated entirely, if one

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had access to an assortment of 1% resistors and carefully calculated the values

needed. One would also want to use a more precise voltage reference than the

common 78L05 regulator provides.

CHAPTER NO 7:

PIEZO ELECTRIC CRYSTAL

Crystals that generate a voltage when a stress is applied to them.The inverse

effect is also true: a voltage causes deformation.This is due to complicated crystal

structure that is unsymmetrical about the center.

In these crystals, the positive and negative charges are separated, but

symmetrical.When a stress is applied, the symmetry is disrupted and there is an

uneven charge distribution.this uneven distribution generates a voltage across the

system.

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CHAPTER - 6

ELECTRONIC COMPONENTS USED

6.1 RESISTOR 

FIG 6.1: SYMBOL OF RESISTOR 

A resistor is a two-terminal  electronic component having a resistance (R)

that produces a voltage (V) across its terminals that is proportional to the electric 

current (I) flowing through it in accordance with Ohm's law: V = IR 

The primary characteristics of a resistor are the resistance, the tolerance, the

maximum working voltage and the  power  rating. Other characteristics include

temperature coefficient, noise, and inductance.

Critical resistance is determined by the design, materials and dimensions of 

the resistor. 

6.2 CAPACITOR 

FIG 6.2 SYMBOL OF CAPACITOR 

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The capacitors are formerly known as condenser. It is a  passive  electronic 

component consisting of a pair of conductors separated by a dielectric (insulator).

When there is a potential difference (voltage) across the conductors, a static

electric field develops in the dielectric that stores energy and produces a

mechanical force between the conductors.

Capacitors are widely used in electronic circuits for blocking direct current 

while allowing alternating current to pass, in filter networks, for smoothing the

output of  power supplies.

6.3 DIODE

FIG 6.3: SYMBOL OF DIODE

In electronics, a diode is a two-terminal electronic component that conducts

electric current in only one direction.

This is a semiconductor material of a vacuum tube with two electrodes: a

 plate and a cathode.

The most common function of a diode is to allow an electric current to pass

in one direction (called the diode's forward direction) while blocking current in the

opposite direction (the reverse direction).

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6.4 TRANSISTOR 

FIG 6.4 SYMBOL OF TRANSISTOR 

A transistor is a semiconductor  device used to amplify and switch electronic 

signals, with at least three terminals for connection to an external circuit.

The transistor is the fundamental building block of modern electronic 

devices, and is ubiquitous in modern electronic systems. Following its release

,transistor revolutionized the field of electronics, and paved the way for smaller 

and cheaper radios, calculators, and computers, among other things. 

6.5 LED (LIGHT EMITTING DIODE)

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FIG.6.5: SYMBOL OF DIODE

A light-emitting diode (LED) is a semiconductor  light source. LEDs are

used as indicator lamps in many devices, and are increasingly used for  lighting.

When a light-emitting diode is forward biased (switched on), electrons are able to

recombine with electron holes within the device, releasing energy in the form of 

 photons. This effect is called electroluminescence and the color  of the light

(corresponding to the energy of the photon) is determined by the energy gap of the

semiconductor.

An LED is often small in area (less than 1 mm2), and integrated optical

components may be used to shape its radiation pattern. LEDs present many

advantages over incandescent light sources including lower energy consumption,

longer  lifetime, improved robustness, smaller size, faster switching, and greater 

durability and reliability.

LEDs powerful enough for room lighting are relatively expensive and

require more precise current and heat management than compact fluorescent lamp 

sources of comparable output. Light-emitting diodes are used in applications as

diverse as replacements for  aviation lighting, automotive lighting (particularly

 brake lamps, turn signals and indicators) as well as in traffic signals.

The compact size, the possibility of narrow bandwidth, switching speed, and

extreme reliability of LEDs has allowed new text and video displays and sensors to

 be developed, while their high switching rates are also useful in advanced

communications technology. Infrared LEDs are also used in the remote control 

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units of many commercial products including televisions, DVD players, and other 

domestic appliances.

APPLICATION

Vibration Dampeners

Energy farm

Quartz Watches

Guitar Pickups

Lighters

Sonar 

Phonographs

Printers

BIBLOGRAPHY:

H. R. Silva, J. A. Afonso, P. C. Morim, P. M. Oliveira, J. H. Correia and

L. A. Rocha , “Wireless Hydrotherapy Smart-Suit Network for Posture

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Monitoring,” Proc IEEE. International Symposium on Industrial

Electronics, ISIE, 4-7 June 2007, pp. 2713-2717.

[2] S. Roundy, P.K. Wright, and J. Rabaey, “Energy Scavenging for Wireless

Sensor Networks with Special Focus on Vibrations,” Kluwer Academic

Press, 2003.

[3] S. Roundy, E. S. Leland, J. Baker, E. Carleton, E. Reilly, E. Lai, B. Otis,

J. M. Rabaey, P. K. Wright, “Improving Power Output for VibrationBased Energy

Scavengers,” Pervasive Computing 2005 pp 28-36.

CONCLUSION:

The piezo electric metal is semiconductor device, have very high

 positive co efficient characteristics, covalent band is very near to conduction band

so most of electrons will easily jump to conduction band. This concept much

useful to our project.

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COST ANALYSIS

S. No Particulars Cost

1 Circuit Designing Rs.1700.00

2 Other Components Rs. 2900.00

3 Project Report Expenses Rs. 1200.00

4 Traveling Expenses Rs. 300.005 Miscellaneous Rs. 400.00

TOTAL Rs. 6500.00

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