Embed Size (px)
Citation preview
ENG6530Reconfigurable Computing
Systems
General Information Handout
Fall 2017, September 7th
2 RCS - Fall 2017
2
Shawki Areibi
Research Interests
• VLSI Physical Design Automation (CAD/EDA)• Combinatorial Optimization (Heuristics/Meta-heuristics)• Reconfigurable Computing Systems/Embedded Systems
PhD, Waterloo 1995
Office, Email, Phone
• Office: 2335, EXT 53819• Email: [email protected]• Web: http://www.uoguelph.ca/~sareibi• Office Hour: Thursday 2:00 – 3:00
3 RCS - Fall 2017
3
Outline
• Staff (TA, Lab Tech)• Lecture Schedule• Course Text and References• Resources and Communication• Assignments, Paper Review, Project• Evaluation• Course contents, Tentative Schedule
4
• Phil Watson (No official Lab Instructor appointed yet!)
• Email: [email protected]
• Thornbrough Building
• Room 1140, ext 53870
Lab Instructor/Coordinator
ENG2410 Fall 2017
5
Lab Assistant
RCS - Fall 2017
5
• Shravani Prasad
• Thornbrough Building
• Room 2319, ext 53873
• Email: [email protected]
6 RCS - Fall 2017
6
Lecture Schedule
o Lectures 11:00 – 12:30 (Tue/Thur)
� In RICH 2531
� Note: Some lectures might take place on same days (Tue/Thur) but at 17:30-19:30
7 RCS - Fall 2017
7
Text Book and References
Text Books & References
1. “Reconfigurable Computing: The Theory and Practice of FPGA-Based Computing”, Edited by S. Hauck, 2008.
2. “Introduction to Reconfigurable Computing: Architectures, Algorithms and Applications”, by C.Bobda
3. “Reconfigurable Computing: Accelerating Computation with FPGAs”, by Maya Gokhale
4. “Computer Organization and Design”, by Patterson and Hennessy
5. “VHDL for Engineers”, by K. Short, 2009.
6. “The Designer’s Guide to VHDL”, by Peter Ashenden
8 RCS - Fall 2017
8
Resources & Communication
o http://www.uoguelph.ca/~sareibi
o Communications
1. E-mail
2. ENG6530/ENG3050 Web Pages
� Username:
� Password:
9 RCS - Fall 2017
9
Prerequisites
o Digital Design (ENG2410)
o Computer Organization (ENG3380)
o Basic knowledge of programming languages (C, C++)
o Basic Knowledge of Hardware Description Languages (VHDL)
o Experience in VLSI Design maybe helpful but not required.
10 RCS - Fall 2017
10
Course Objectives
Achieves the following goals:1. Gives an overview of the traditional Von Neumann
Computer Architecture, its specifications, design and implementations and main drawbacks. Techniques to improve the performance.
2. Teaches you the internal structure of Programmable Logicin general and Field Programmable Gate Arrays in particular.
3. Teaches you how digital circuits are designed today using advanced CAD tools and HDLs and high level languages.
4. Teaches you the basic concepts of Reconfigurable Computing systems (Hardware/Software co-design)
5. Teaches you when/how to apply Reconfigurable Computing Concepts to design efficient, reliable, robust systems (DSP).
6. Understand the concept of Run Time Reconfiguration.
11 RCS - Fall 2017
11
Evaluation
Topic Weight Details
Assignments 25% Assignments
Paper Review 10% See Web Page
Project 25% See Web Page
Final Exam 40% Closed Book Exam
12 RCS - Fall 2017
12
Paper Review
o Each student (group) is assigned several articles from journal papers/conferences.
o Prepare a brief (20 minute) oral presentation of the article or topic (objectives, methods, results, contributions e.t.c.)
o A Two page summary giving the citation and the material in the oral presentation must be written and a copy is distributed to each class member.
13 RCS - Fall 2017
13
Paper Review: Topics
1. Coarse Grained Reconfigurable Arrays
2. Evolvable Hardware
3. Floating Point vs. Fixed Point representations
4. CAD for RCS (High Level Synthesis)
5. Operating Systems for Reconfigurable Computing
6. Electronic System Level: A comparison
7. ASICs vs. FPGAs vs. ASIPs
8. Run Time Reconfiguration: Challenges
9. Others …
14 RCS - Fall 2017
14
Research Project
o “Graduate Students” will select a topic related to Reconfigurable Computing Systems.
o You should conduct an in-depth study covering the problem to be solved and its current status.
o Your finding should be documented in a report� Introduction to the problem� Motivation� Background� Literature Review� Methodology� Results� Conclusion
15 RCS - Fall 2017
15
Tentative Schedule
o Topic #1, Introduction to RCS
o Topic #2, Programmable Logic Devices
o Topic #3, CAD for RCS (FPGAs)
o Topic #4, VHDL
o Topic #5, High Level Languages (Handel-C)
o Topic #6, Reconfigurable Processors (ASIPs)
o Topic #7, Hardware/Software Co-design
o Topic #8, Run Time Reconfigurations
o Topic #9, Digital Signal Processing, Tools
o Topic #10, Design Exploration Techniques
o Topic #11, RCS Applications
16 RCS - Fall 2017
16
What is Reconfigurable Computing?
o Mapping algorithms traditionally running on general purpose processors onto reconfigurable platforms to achieve better performance.
o Computation using hardware that can adapt at the logic level to solve specific problems
o Why is this interesting/important?• Some applications are poorly suited to General microprocessors.
• VLSI “explosion” provides increasing resources.
• Hardware/Software Co-design is main trend in Embedded Systems.
• Accelerate scientific/industrial applications to achieve speedup (Real Time performance is necessary!)
17 RCS - Fall 2017
17
Topic #1: RCS, Introduction
o Identify bottlenecks currently found in traditional Von Neumann Architectures.
o Learn new techniques to improve performance.o How/Why RCS can fill the gap between ASICs and
General Purpose Processors.
18 RCS - Fall 2017
18
Topic #1, Cont ..: Technology Comparison
Technology Performance Cost Power Flexibility Memory BW I/O BW
GPP
PDSP
ASIC
FPGA
LOW
Med-High
HIGH
Medium
LOW
Medium
HIGH
LOWt
HIGH
Medium
LOW
Low-Medium
HIGH
Medium
LOW
HIGH
LOW
Medium
HIGH
HIGH
LOW
LOW
HIGH
HIGH
19 RCS - Fall 2017
19
ProgrammableOr Array
ProgrammableAND array
ProgrammableOr Array
ProgrammableAND array
Topic #2: Programmable Logic
20 RCS - Fall 2017
20
Topic #2 Cont … : FPGAs
o Around the beginning of the 1980s, it became apparent that there was a gap in the digital IC continuum.
o At one end, there were programmable devices liks SPLDs and CPLDs, which were highly configurable but could not support large designs.
o At the other end of the spectrum were ASICs which can support complex functions but were expensive, time consuming, ….
21 RCS - Fall 2017
21
Topic #3: CAD for Programmable Logic
Design Entry
Logic Optimization
Synthesis
Mapping to k-LUT
Packing LUTs to CLBs
Placement
Routing Configure an FPGA
Simulation
22 RCS - Fall 2017
22
Topic #3: FPGA Design Flow
Synthesis• Translate Design into Device Specific Primitives• Optimization to Meet Required Area & Performance Constraints
Design Specification
Place & Route• Map Primitives to Specific Locations inside
Target Technology with Reference to Area &• Performance Constraints• Specify Routing Resources to Be Used
Design Entry/RTL CodingBehavioral or Structural Description of Design
LEMEM I/O
RTL Simulation• Functional Simulation• Verify Logic Model & Data Flow (No Timing Delays)
23 RCS - Fall 2017
23
B
AFInternal
Functionality
circuit
ExternalInterface
InputsOutputs
Topic #4: VHDL
24 RCS - Fall 2017
24
VHDL for Specification
VHDL for Simulation
VHDL for Synthesis
VHDL for Synthesis
of Arithmetic Circuits
Topic #4: Synthesizable VHDL
25 RCS - Fall 2017
25
Topic #5: Managing ComplexityESL
26 RCS - Fall 2017
26
Topic #5: High Level Languages
o Take an algorithm written in C.
o Generate an efficient hardware design, run it on an FPGA.
o Fast design cycle, easy to maintain code.
o C programmers should be able to create fast hardware!
27 RCS - Fall 2017
27
Topic #6: ASIPs
An ASIP is a stored-memory CPU whose architecture is tailored for a particular set of applications.
� The instruction-sets tailored to specific applications or application domains
28 RCS - Fall 2017
28
process (a, b, c)in port a, b;out port c;
{read(a);…write(c);
}
Specification
Line (){
a = ……detach
}
Processor
Capture
Model FPGA
Partition
Synthesize
Interface
Topic #7: Hardware/Software Co-design
29 RCS - Fall 2017
29
Topic #8: RTR
FPGAs are classified as dynamically reconfigurable if their embedded configuration storage circuitry and corresponding functions can be updated without disturbing the operation of the remaining logic.
30 RCS - Fall 2017
30
The concept of Run Time Reconfiguration on FPGAs is similar to the concept of Virtual Memory on Computer Systems.
Topic #8, Cont ..: Virtual Hardware
31 RCS - Fall 2017
31
Topic#9: DSP
32 RCS - Fall 2017
32
o Algorithmic complexity increases as application demands increase.
o In order to process these new algorithms, higher performance signal processing engines are required
Topic #9: DSP, Performance Gap
33 RCS - Fall 2017
33
Topic #10: Design Exploration
o Given an application (software implementation): what is the most appropriate hardware components and communication links that should be used?
o The main challenge in DSE arises from the sheer size of the design space that must be explored.
� Typically, a large system has millions, if not billions, of possibilities, and so enumerating every point in the design space is prohibitive.
34 RCS - Fall 2017
34
Topic #11: Applications
o What applications require Hardware Acceleration?
o Image processing, medical applications, real time …� Hardware Accelerators for CAD
� Hardware Accelerators for ANNs
� Hardware Accelerators for Communication Systems
RCS - Fall 2017 35
Satellite Imaging
• Satellite imaging used for mapping, environmental s tudies and defense applications
• High-data rate and low-power demands of space requi re cutting-edge technology such as RC to provide requi red processing capabilities
• Including RC devices in the processing chain will eventually enhance performance
Pulse
Compression
Doppler
Processing
Space-Time
Adaptive
Processing
(STAP)
Constant
False Alarm
Rate
(CFAR)
Receive
Cube
Send
Results
Corner TurnPartitioned along
range dimension
Partitioned along
pulse dimension
GMTI processing chain
c/o LANLc/o LANL
c/o US Air Force
RCS - Fall 2017 36
fMRI and Real-time Human Body Imaging• Technique for determining which parts of the brain are activated
by different types of physical sensation or activit y – “brain mapping”
• High- and low-resolution scans compared using numero us FFTs– Typically post-processed– Much error correction needed due to subject movemen t– 3D data representation requires a good deal of conv entional processing
• Studying how RC devices can achieve real-time proce ssing
Figures c/o University of Oxford, UK
37 RCS - Fall 2017
37
