Engineering Models and Circuit Realization of

Quantum State Machines

5. Complete Automated

System for Design of QSM

5.1. Complete Automated System for Design of QSM

1. Use state minimization/state assignment techniques available in the Berkeley tools to obtain various encoded ( and/or minimized ) flavors of the machine

2. Use DCARL/MMD to find the reversible logic solutions for all flavors of the encoded machine

3. Analyze the results and come up with the best state minimization / encoding strategy that works for reversible logic implementation of the FSM

4. Use the Benchmark circuits for the input FSM’s

Problem Definition• State assignment problem

– Involves assigning binary coded values to the states of an FSM

– The target is to minimize the area of the combinational circuit required to realize the FSM

– The complexity of the combinational component of the FSM depends heavily on the state assignment and selection of memory elements

• Creating completely specified functions– Done by assigning values to the “don’t care” outputs to

produce reversible logic

Tools and Tools and FlowFlow

Tools and Flow • Available Berkeley tools – MVSIS, SIS, VIS• SIS – System for Sequential circuit synthesis• MVSIS – for multiple valued logic synthesis, does not

implement sequential logic yet• VIS – Verification tool for sequential logic, calls SIS to do the

optimization for any given state machine• SIS available 1.2 for Windows and 1.3 for Linux• Can be downloaded from

http://embedded.eecs.berkeley.edu/pubs/downloads/sis/index.htm

Tools and Flow1. DCARL – Don’t Care algorithm for reversible logic, developed at PSU in

2007 and presented at RM 2007

2. Assign values to the “don't cares” outputs, and map the outputs according to the assigned input values, creating thus a completely specified reversible Boolean function specification

3. Apply the MMD algorithm to this specification to synthesize the network

4. Compare the cost in terms of the number of Toffoli gates and keep track of the “don't cares” values with the minimal cost

5. Backtrack to find K solutions or until no more backtracking is possible

SIS Usage• Inputs can be in KISS, BLIF format

• KISS – uses State Transition Graph format, can be synchronous as well as asynchronous

• BLIF – Netlist of Combinational gates and latches

• BLIF – internally represented as care network, don’t care network, can be verified by stg_cover command which simulates both symbolically

• Performs State minimization, State assignment, Retiming

SIS commands and description• State minimization – states are equivalent if they produce

same outputs for same set of inputs– Uses STAMINA, developed by University of Colorado, Boulder with

heuristics implemented for incompletely specified machines– Uses KISS input and output

• State assignment – STG to binary codes for each symbolic state

• Retiming – moves registers across logic gates to minimize cycle time, number of registers

NovaNova

State assignment toolsSIS - NOVA

• Target two-level PLA based implementations

• Optimizes the number of product terms called cubes

• The assignment needs to be in such a way that the area of the combinational circuit required to realize the FSM is minimized

• Solves two types of problems:– Constrained cubical embedding problem

• Focused on input constraints– Covered constrained cubical embedding problem

• Focused on both input and output constraints

NOVAAlgorithms used for

state encoding• Algorithms that solve constrained cubical embedding

problem:

1. iexact_code• Is an exact algorithm• Finds an encoding satisfying all input constraints• Target is minimizing the encoding length

2. ihybrid_code• heuristic encoding algorithms (approximate)• Target is to maximize input constraint satisfaction• User supplied encoding length (or default used)• Based on a polynomial version of iexact_code• Yields solutions of high quality and guarantees the satisfaction of all

input constraints for an encoding space large enough

NOVAAlgorithms used for

state encoding3. igreedy_code

• Heuristic encoding algorithms (approximate)• Target is to maximize input constraint satisfaction• User supplied encoding length (or default used)• Specially tailored for short code-lengths

• Algorithm that solves covered constrained cubical embedding problem:1. iohybrid_code

• heuristic encoding algorithms (approximate)• Target is to maximizes simultaneous input and output constraint

satisfaction• Based on an adaptation of ihybrid_code to deal with both input and

output constraints

JediJedi

State assignment tools:SIS - Jedi

• Target multi-level logic implementations• Uses simulated annealing based encoding scheme• There are four main heuristics for generating

weights between pairs of states: – Input dominant– Output dominant– Coupled – Variations

JediAlgorithms used for

state encoding

1. The input dominant algorithm:1. works on the source states of the transitions of the FSMs (the states from which the transitions are

triggered)2. pairs of present states which assert similar outputs and produce similar sets of next states are

given high edge weights3. This has an effect of maximizing the size of common cubes in the boolean functions corresponding

to the output and the next state lines

2. The output dominant algorithm1. works on the output states of the transitions of the FSMs2. pairs of next states which are produced by similar inputs and similar sets of present states are

given high edge weights3. This has an effect of maximizing the number of common cubes in the boolean functions

corresponding to the next state lines

3. The coupled approach– Uses a hybrid of the input and output dominant heuristics

4. Variations– Examples: one-hot, random, straight mapping

SIS example flow

Input state machine

.i 1

.o 1

.p 10

.s 50 A B 01 A C 10 B C 11 B B 00 C C 11 C D 10 D E 11 D A 10 E B 01 E C 1

Minimized State Machine

.i 1

.o 1

.p 8

.s 4

.r S00 S0 S1 01 S0 S2 10 S1 S2 11 S1 S1 00 S2 S2 11 S2 S3 10 S3 S0 11 S3 S0 1

Encoded State Machine – part of BLIF output

0 S0 S1 01 S0 S2 10 S1 S2 11 S1 S1 00 S2 S2 11 S2 S3 10 S3 S0 11 S3 S0 1

.code S0 11

.code S1 10

.code S2 00

.code S3 01

DCARLDCARL

DCARL Usage/Description• Inputs are test files that contains input vectors

• Input bits can be 0, 1 or x

• Outputs are text files, one for each solution, output file contains output vectors that are output bits

• Output bits can only be 0 or 1 (completely specified)

• No repeated output vectors (reversible)

• Some bits may be added to generate reversible functions

• Outputs of DCARL applied to MMD to choose best solution

DCARL example flow 1

Incompletely Specified

Input

00110111x00x01xxx0xxx 111

Completely Completely

SpecifiedSpecified

Output 1Output 1001001101101110110000000010010100100

011 011 111111

Completely Completely

SpecifiedSpecified

Output 2Output 2001001101101110110000000011011010010

100 100 111111

DCARL example flow 2/1

Incompletely Specified

Input

00100111x00x01xxx0xxx 111

Output 1Output 1

000100011001100101100110000000000010001001000100

0011 0011 01110111010101011000100010101010101110111100110011011101

1110 1110 11111111

Output 2Output 2

1001100100010001011001100000000000100010010001000011 0011 011101110101010110001000101010101011101111001100110111011110 1110 11111111

•Add Garbage bitsAdd Garbage bitsGenerate reversible logic bitsGenerate reversible logic bits

DCARL example flow 2/2

Output 4Output 4

0001000110011001111011100000000000100010010001000011 0011 011101110101010101100110100010001010101010111011110011001101110111111111

Output 5Output 5

0001000110011001111111110000000000100010010001000011 0011 01110111010101010110011010001000101010101011101111001100110111011110 1110

•Add Garbage bitsAdd Garbage bitsGenerate reversible logic bitsGenerate reversible logic bits

Output 3Output 3

0001000110011001011101110000000000100010010001000011 0011 11111111010101010110011010011001101010101011101111001100110111011110 1110

Output 6Output 6

00010001100110010110011010001000001000100000000000110011011101110100 0100 01010101101010101011101111001100110111011110 1110 11111111

SIS output to DCARL input conversion

Encoded State Machine

0 S0 S1 01 S0 S2 10 S1 S2 11 S1 S1 00 S2 S2 11 S2 S3 10 S3 S0 11 S3 S0 1

.code S0 11

.code S1 10

.code S2 00

.code S3 01

DCARL formatOnly outputs in the input file

Inputs included here for clarityFormat below

Encoded State, Input / Output

000 - 001001 - 011010 - 111011 - 111100 - 001101 - 100110 - 100111 - 001

6. Results

6.1. Results - Work flow• Some FSM’s from MCNC benchmark circuits chosen

• SIS – State machine minimization run on each circuits

• State assignment - NOVA and JEDI with options run on all the circuits

• DCARL input file for each encoded state machine obtained

• DCARL run on the input and cost obtained

Results – Minimal cost and State assign options

FSM Inputs Outputs States

DCARL input

JEDI NOVA

  Inputs Outputs States option cost option cost

bbtas 2 2 6 5 r 350 ig 362

dk16 2 3 27 7 r 5299  

donfile 2 1 24 3 c 13 all (ie failed) 15

lion 2 1 4 4 c 51 ia, ie, ig, ih 44

lion9 2 1 9 4 d, r, i 126 ia, ig, ih 125

s27 4 1 6 7 r 2149 r 2135

shiftreg 1 1 8 4 s 6 r 4

train11 2 1 11 4 o, y 128 ig 117

train4 2 1 4 4 c, i 48 ie, ig, ih 43

s8 4 1 5 5 c, r 10 ia, ig,, ih, ioh 18

modulo12 1 1 12 5 s 93 iov 104

bbara 4 2 10 7 y 5034 ih 5148

Results – JEDI and DCARL

JEDI options and DCARL cost

1

10

100

1000

10000

c d i o r s y

JEDI state assign options

DC

AR

L c

ost

(lo

g s

cale

)

bbtas

dk16

donfile

lion

lion9

s27

shiftreg

train11

train4

s8

modulo12

bbara

NOVA options and DCARL costNOVA options and DCARL cost

1

10

100

1000

10000

100000

ia ie ig ih ioh iov r

NOVA

NOVA state assign options

DC

AR

L c

ost

( lo

g s

cale

)

bbtas

donfile

lion

lion9

s27

shiftreg

train11

train4

s8

modulo12

bbara

6.2. Conclusions on Software6.2. Conclusions on Software1. Different algorithms for state assignment and Boolean function

realization of excitation functions provide minimal cost for different state machines

2. Some options like “ie” works better with smaller circuits, but bigger circuits it either add extra bits or even fail

3. In almost 70% of the cases the random or coupled approaches gave the best results for Jedi

4. In general Jedi is better in handling bigger circuits compared to Nova

5. Both Nova and Jedi are algorithms developed in past for SOP realization of excitation functions. One needs new state assignments algorithms for One needs new state assignments algorithms for ESOP-type of logic, as it is realized in quantum circuits.ESOP-type of logic, as it is realized in quantum circuits.

7. General Conclusions on QSM Synthesis7. General Conclusions on QSM Synthesis

1. Practical models for QSMs and their classical controllers have been developed. Our approaches all involve state minimization and state assignment of machines. Other methods of realization that are used in classical machines, such as decomposition or one-hot encoding, should be also investigated.

2. A synthesis flow which allows us to design QSMs from abstract specifications has been developed. The CAD tool can be improved by improving backtracking method to convert incomplete to complete functions and by better quantum circuit minimizer that will replace MMD.

3. Synchronous as well as asynchronous techniques for high level synthesis of QSMs have been demonstrated by us. More details can be found in MS thesis of Manjith Kumar.

4. State assignment tools from U.C. Berkeley were used but new algorithms specific to reversible logic should be developed