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Enhancement/Depletion-mode HEMT Technology for III-Nitride Mixed-Signal and RF Applications
by
Ruonan WANG
A Thesis Submitted to The Hong Kong University of Science and Technology
in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy
in the Department of the Electronic and Computer Engineering
January 2008, Hong Kong
ii
Authorization
I hereby declare that I am the sole author of the theses.
I authorize the Hong Kong University of Science and Technology to lend this thesis to other institutions or individuals for the purpose of scholarly research.
I further authorized the Hong Kong University of Science and Technology to reproduce the thesis by photocopying or by other means, in total or in part, at the request of other institutions or individuals for the purpose of scholarly research.
__________________________________________ Ruonan WANG
iii
Enhancement/Depletion-mode HEMT Technology for III-Nitride Mixed-Signal and RF Applications
by
Ruonan WANG
This is to certify that I have examined above PhD thesis and have found that it is complete and satisfactory in all aspects,
and that any and all revisions required by the thesis examination committee have been made.
________________________________________ Prof. Kevin J. CHEN
Thesis Supervisor
________________________________________ Prof. Kwing Lam CHAN
Thesis Examination Committee Member (Chairman)
________________________________________ Prof. Kei May LAU
Thesis Examination Committee Member
________________________________________ Prof. Johnny K. O. SIN
Thesis Examination Committee Member
________________________________________ Prof. Jiannong WANG
Thesis Examination Committee Member
________________________________________ Prof. Khaled BEN LETAIEF
Head of the Department of Electronic and Computer Engineering
The Department of Electronic and Computer Engineering January 2008
iv
ACKNOWLEDGEMENTS
I would first like to take this opportunity to express my appreciation to my
supervisor, Prof. Kevin J. CHEN, for his intensive guidance and generous help in my
thesis work. Without his support, I could not have this opportunity to come to Hong
Kong and involve in the challenging and exciting field of GaN HEMTs. In the past
three and a half years, I learned so much from him on how to become a good
researcher. I think I can benefit from the experience with him all through my life,
especially his persistent pursuit in deeply understanding and solving problems, and
his great enthusiasm on the research and teaching work. Prof. Chen also provided me
a lot of opportunities to attend international conferences, and therefore, got a chance
to have conversations with the top corporations and research groups in the world. In
addition, I would like to thank Prof. Kei May LAU, for her supporting and providing
substrates in my research work. The other committee members of my thesis
examination are also appreciated: Prof. Kwing Lam CHAN, Prof. Jiannong WANG,
Prof. Johnny K. O. SIN, and Prof. Jianbin XU.
Most of the GaN HEMT samples used in this work were grown by Mr. Wilson C.
W. TANG, my long-term research cooperator. Many thanks go to Mr. Kwok Wai
CHAN for his kindness and patience in guiding me how to use the microwave device
measurements.
All of the GaN-based HEMTs, which make up of the foundation of my research
work, were fabricated in the nanoelectronic fabrication facility (NFF) at HKUST. It’s
Mr. Shuo JIA who helped me get familiar with the clean room and the details of
v
micro-fabrication techniques. He was a very good listener and friend, and we got a
lot of funs on the same interests. I also want to express my gratitude to Dr. Yong
CAI, and Dr. Jie LIU, who gave me many valuable suggestions to my work. Their
solid experiment results on GaN HEMTs constructed the foundation of my thesis
work, and their experience saved me a lot of time in wafer processing. Dr. Zhiqun
CHENG made me grasp the basic design principles of RF device and circuit
topology in a short time. Dr. Zhenchuan YANG also deserves to be mentioned here
for his helpful discussions in the group meetings and resourceful knowledge on
micro-fabrications. It has been a pleasant time to work with these kind people and
share the knowledge of GaN-based devices and circuits with them.
I would like to thank some other members in the wireless communication
laboratory, Dr. Congshun WANG, Dr. Wei HUANG, Dr. Wanjun CHENG, Dr.
Hualiang ZHANG, Dr. Maojun WANG, Mr. Kingyuen WONG, Mr. Yichao WU, Mr.
Di SONG, Mr. Li YUAN, Mr. Xiaohua WANG, Ms. Song TAN and Ms. Congwen
YI, who worked with me for a long time and shared the happy time with me.
A last, I must thank my father Duo WANG, my mother Shuyun QIAO and my
wife Hong YIN for their unconditional love, efforts and encouragements all the time.
They are the most important part of my life.
vi
TABLE OF CONTENTS
Title Page…… .......................................................................................................................... i
Authorization Page................................................................................................................... ii
Signature Page ........................................................................................................................ iii
Acknowlegements................................................................................................................... iv
Table of Contents.................................................................................................................... vi
List of Figures ….................................................................................................................... ix
List of Tables ........................................................................................................................ xiv
Abstract……............................................................................................................................ 1
Chapter 1 Introduction ............................................................................................................. 4
1.1 Fundamentals of High Electron Mobility Transistors ........................................ 4
1.2 Developments of AlGaN/GaN HEMTs ........................................................... 14
1.3 Enhancement/Depletion-mode AlGaN/GaN HEMTs and Mixed-Signal
Applications ..................................................................................................... 19
1.3.1 Synthesis of Enhancement-mode AlGaN/GaN HEMTs ....................... 19
1.3.2 Mixed-signal applications of E/D-mode AlGaN/GaN HEMTs ............ 24
1.4 Objective of This Work.................................................................................... 27
Chapter 2 Temperature Dependence and Thermal Stability of Planar-Integrated
Enhancement/Depletion-mode AlGaN/GaN HEMTs and Digital Circuits...... 29
2.1 Motivation of Planar Integration of E/D-mode AlGaN/GaN HEMTs for GaN-
based High Temperature Digital Circuits......................................................... 29
vii
2.2 Device Structure and Fabrication..................................................................... 31
2.3 Discrete E/D-mode AlGaN/GaN HEMTs by Planar Process........................... 36
2.3.1 Temperature Dependence...................................................................... 36
2.3.2 Thermal stability ................................................................................... 44
2.4 Planar-Integrated DCFL Digital Circuits ......................................................... 46
2.4.1 DCFL Inverters ..................................................................................... 46
2.4.2 DCFL Ring Oscillators.......................................................................... 50
2.5 Summary .......................................................................................................... 54
Chapter 3 Integration of Enhancement and Depletion-mode AlGaN/GaN MIS-HFETs by
Fluoride-based Plasma Treatment .................................................................... 56
3.1 Motivation of Fabrication of E-mode AlGaN/GaN MIS-HFETs..................... 56
3.2 Device Structure and Fabrications ................................................................... 58
3.3 Device and Circuit Characterization ................................................................ 61
3.3.1 E-mode AlGaN/GaN MIS-HFET Characteristics ................................. 61
3.3.2 DCFL Integrated Circuit Applications .................................................. 66
3.4 Conclusions ...................................................................................................... 70
Chapter 4 Gain Improvement of Enhancement-mode AlGaN/GaN HEMTs Using Dual-
Gate Architectures............................................................................................ 71
4.1 Motivation for the Enhancement-mode AlGaN/GaN DG HEMTs.................. 71
4.2 E-mode Dual-Gate AlGaN/GaN HEMTs Fabrication ..................................... 72
4.3 Device DC and RF Characteristic Comparison................................................ 74
4.4 Conclusions ...................................................................................................... 79
viii
Chapter 5 Conclusion............................................................................................................. 81
5.1 Conclusion........................................................................................................ 81
5.2 Suggestions for Future Work ........................................................................... 84
References….......................................................................................................................... 86
Appendix A Planar Process Flow for E/D-Mode AlGaN/GaN HEMT Integration............ 102
Appendix B Device DC and RF Characterization .............................................................. 109
Appendix C Process Flow for E/D-Mode AlGaN/GaN MIS-HFETs................................. 118
Appendix D Publication List .............................................................................................. 126
ix
LIST OF FIGURES
Fig. 1.1.1 Schematic structure of an AlGaAs/GaAs HEMT and the corresponding energy band profile. ....................................................................................................... 5
Fig. 1.1.2 Energy-band diagram of the metal/n-AlGaAs/GaAs system and the
electrostatic field distribution in the AlGaAs layer at the threshold voltage and VG,max. ................................................................................................................. 6
Fig. 1.1.3 Gate-bias-modulated conduction band diagram and 2DEG concentration of an
AlGaAs/GaAs HEMT. ....................................................................................... 7 Fig. 1.1.4 Typical DC I-V characteristics of an AlGaAs/GaAs HEMT: (a) output curve;
(b) transfer curve. ........................................................................................................ 8 Fig. 1.1.5 Equivalent circuit model for a HEMT, and the intrinsic circuit model is
enclosed by the dashed line........................................................................................ 9 Fig. 1.1.6 The physical origin of the elements in the equivalent circuit model of
AlGaAs/GaAs HEMT............................................................................................... 10 Fig. 1.1.7 Schematic representation of a HEMT operating in Class A................................ 13 Fig. 1.2.1 Schematic structure of an AlGaN/GaN HEMT and the corresponding energy-
band profile. ............................................................................................................... 15 Fig. 1.2.2 Crystal structure of (a) Ga-faced and (b) N-faced wurtzite GaN........................ 16 Fig. 1.2.3 Band profiles of the AlGaN/GaN heterostructures with different AlGaN
thickness, which demonstrate the surface states’ contribution to the 2DEG formation. ................................................................................................................... 17
Fig. 1.3.1 Schematic diagram of an E-mode HEMT with the recessed gate. ..................... 20 Fig. 1.3.2 Conduction band schematic diagrams of (a) conventional D-mode AlGaN/GaN
HEMT and (b) E-mode HEMT with CF4 plasma treatment............................... 22 Fig. 1.3.3 DCFL circuit schematics of (a) E/D-mode HEMT inverter, (b) NOR gate and
(c) NAND gate logic circuits. .................................................................................. 26 Fig. 2.2.1 Schematic cross-section of the AlGaN/GaN HEMT device. .............................. 31
x
Fig. 2.2.2 Layout of the Hall Bridge for Hall measurements................................................ 32 Fig. 2.2.3 Schematics showing the process flow of E/D-mode HEMTs: (a) ohmic contact;
(b) active region definition by plasma treatment; (c) D-mode gate formation; (d) E-mode gate definition and plasma treatment; (e) SiN passivation. .................. 33
Fig. 2.2.4 Layout for the AlGaN/GaN HEMTs fabrication .................................................. 34 Fig. 2.2.5 Microscopy photos of the fabricated HEMT devices: (a) overall view; and (b)
zoom-in view of the active region........................................................................... 35 Fig. 2.3.1 DC output characteristics of (a) D-mode HEMT and (b) E-mode HEMT by the
planar process............................................................................................................. 36 Fig. 2.3.2 Transfer characteristics comparison between the planar process and the
standard ICP mesa etching process: (a) drain current and (b) transconductance comparison. The source-drain voltage (VDS) is fixed at 10 V............................. 37
Fig. 2.3.3 D-mode HEMTs transfer characteristics comparison at different temperatures:
(a) drain current and (b) transconductance. ........................................................... 38 Fig. 2.3.4 E-mode HEMTs transfer characteristics comparison at different temperatures:
(a) drain current in log scale, (b) drain current in linear scale and (c) device transconductance. ...................................................................................................... 39
Fig. 2.3.5 Temperature dependence of threshold voltage (Vth) and off-state drain leakage
current (Ileak) for E/D-mode HEMTs by the planar process................................. 40 Fig. 2.3.6 Sub-threshold slope characteristic comparison between RT and 350°C ........... 42 Fig. 2.3.7 Sub-threshold slope characteristics from RT to 350°C........................................ 43 Fig. 2.3.8 Schematics of gate controlling capability in sub-threshold region for (a) D-
mode and (b) E-mode HEMTs. ............................................................................... 43 Fig. 2.3.9 E/D-mode HEMTs DC characteristic comparison before and after high-
temperature measurements....................................................................................... 44 Fig. 2.3.10 The variations of the peak drain current density (Imax), off-state drain current
(Ileak) and maximum transconductance (gm) during thermal stress up to 153 hours at 350ºC for E/D-mode HEMTs fabricated by the planar process........... 45
Fig. 2.3.11 Small signal RF characteristics comparison before and after thermal stress for
both E-mode and D-mode HEMTs by the planar process. .................................. 46
xi
Fig. 2.4.1 Schematic design of E/D-mode AlGaN/GaN DCFL inverter. ............................ 47 Fig. 2.4.2 Static voltage transfer curves of an E/D-mode HEMT DCFL inverter at (a)
room temperature (RT) and (b) 350ºC. .................................................................. 47 Fig. 2.4.3 Temperature dependence of (a) the voltage transfer curves and (b) current
consumption for the E/D-mode DCFL inverter by the planar process. ............. 49 Fig. 2.4.4 (a) Schematic design and (b) SEM photograph of a 17-stage E/D-mode
AlGaN/GaN DCFL ring oscillator by the planar process.................................... 50 Fig. 2.4.5 Configuration of ring oscillator measurement system, including a DC source, a
current meter, a spectrum analyzer and an oscilloscope. ..................................... 51 Fig. 2.4.6 The 17-stage E/D-mode AlGaN/GaN HEMT DCFL ring oscillator frequency
spectrum at (a) room temperature (RT) and (b) 350ºC. ....................................... 52 Fig. 2.4.7 The dependences of the ring oscillator (a) output frequency and (b) current
consumption on different environment temperatures........................................... 53 Fig. 2.4.8 The dependences of the ring oscillator power-delay product per stage on
environment temperatures. ....................................................................................... 53 Fig. 3.2.1 Capacitance-voltage curves of the substrate used for the E/D-mode MIS-HFET
fabrication................................................................................................................... 58 Fig. 3.2.2 Schematics showing the process flow of E/D-mode AlGaN/GaN MIS-HFETs
integration: (a) active region definition and ohmic contacts; (b) the 1st Si3N4 layer (thick) deposition and E-mode gate definition; (c) D-mode device window opened; (d) the 2nd Si3N4 layer (thin) deposition; (e) interconnects and pads openings; (f) metallization for gate contacts and interconnects................. 59
Fig. 3.3.1 E-mode AlGaN/GaN MIS-HFET (a) DC output and (b) transfer curves.......... 62 Fig. 3.3.2 E-mode AlGaN/GaN MIS-HFET gate leakage current performance. ............... 63 Fig. 3.3.3 Pulse measurements of E-mode AlGaN/GaN MIS-HFET. ................................. 63 Fig. 3.3.4 Small signal RF measurements of E-mode AlGaN/GaN MIS-HFETs .............. 64 Fig. 3.3.5 Power sweep measurements by a load-pull system at 2 GHz on E-mode
AlGaN/GaN MIS-HFETs......................................................................................... 65
xii
Fig. 3.3.6 DC output characteristics of an E-mode MIS-HFET with longer fluoride plasma treatment time. .............................................................................................. 66
Fig. 3.3.7 D-mode AlGaN/GaN MIS-HFET (a) DC output and (b) transfer curves. ........ 67 Fig. 3.3.8 E/D-mode AlGaN/GaN MIS-HFET DCFL inverter voltage transfer and current
consumption curve. ................................................................................................... 68 Fig. 3.3.9 Ring oscillator frequency and time domain characteristics at RT [(a) and (b)]
and 415°C [(c) and (d)]............................................................................................. 69 Fig. 3.3.10 Temperature dependence of ring oscillator frequency and current consumption.
...................................................................................................................................... 70 Fig. 4.1.1 Schematic structure of dual-gate AlGaN/GaN HEMTs....................................... 72 Fig. 4.2.1 Schematics showing the process flow of E-mode DG HEMTs: (a) mesa and
ohmic contacts; (b) D-mode gate electrodes; (c) E-mode gate definition and plasma treatment; (d) E-mode gate metal deposition and lift-off....................... 73
Fig. 4.3.1 DC characteristics of E-mode DG HEMTs: (a) output curves and (b) transfer
characteristics............................................................................................................. 75 Fig. 4.3.2 Transfer curves of E-mode and D-mode SG HEMTs. ......................................... 76 Fig. 4.3.3 Frequency dependence of short-circuit current gain (h21) and maximum
stable/maximum available gain (MSG/MAG) for E-mode DG and SG devices....................................................................................................................................... 76
Fig. 4.3.4 Equivalent small-signal circuit model for AlGaN/GaN HEMTs........................ 77 Fig. 4.3.5 Output impedance (RDS) and feedback capacitance (CGD) comparison between
E-mode SG and DG HEMTs, which are extracted from S-parameters. ............ 78 Fig. 4.3.6 Gain-frequency characteristic comparison between E-mode DG and SG
HEMTs........................................................................................................................ 78 Fig. B.1 (a) Configuration of the static DC measurement with a semiconductor
parameter analyzer; (b) the shape of the device for the static DC measurement..................................................................................................................................... 109
Fig. B.2 (a) Configuration of the dynamic I-V measurement with a dynamic I-V
analyzer; (b) the shape of the device for the dynamic I-V measurement; (c) the shape of the GSG probe for RF measurements. .................................................. 110
xiii
Fig. B.3 (a) Configuration of the CV measurement with a LCR meter and a
semiconductor parameter analyzer; (b) the shape of Schottky diode for the CV measurement. ........................................................................................................... 111
Fig. B.4 Configuration of the S-parameters measurement with a vector network analyzer
(VNA) and a DC bias source controlled by PC. ................................................. 114 Fig. B.5 SOLT calibration standards for on-wafer RF small-signal measurement. ...... 115 Fig. B.6 The shape of the “open” pad for device de-embeding. ...................................... 116 Fig. B.7 Configuration of the large-signal power measurement, including a load-pull
system, a signal generator, a DC bias source, and a power meter controlled by a PC. ............................................................................................................................. 117
xiv
LIST OF TABLES
Table 1-1 Advantages of the HEMT structure. .................................................................. 8 Table 1-2 Historical Development of GaN-based HEMTs. ............................................. 18 Table 1-3 E-mode AlGaN/GaN HEMT performance comparison................................... 23 Table 1-4 Properties of competing materials in power electronics. ................................. 24 Table 1-5 Competitive advantages of GaN devices ............................................................... 25 Table 2-1 DCFL inverter characteristics with different environment temperatures at the
supply voltage of 3.3 V............................................................................................. 50
1
Enhancement/Depletion-mode HEMT Technology for III-Nitride
Mixed-Signal and RF Applications
by Ruonan WANG
Department of Electronic and Computer Engineering
The Hong Kong University of Science and Technology
ABSTRACT
Owing to the unique capabilities of achieving high breakdown voltage, high
current density, high cut-off frequencies, and high operating temperatures,
AlGaN/GaN high electron mobility transistors (HEMTs) are emerging as promising
candidates for radio-frequency (RF)/microwave power amplifiers and high-
temperature electronics. Compared to the conventional depletion-mode (D-mode)
AlGaN/GaN HEMTs, enhancement-mode (E-mode) devices present two major
advantages: 1) the reduced circuit complexity by eliminating the negative voltage
supply; 2) the implementation of direct-coupled FET logic (DCFL) for digital
circuits by integrating E/D-mode AlGaN/GaN HEMTs together. In this work, we
will use a novel fluoride-based plasma treatment technique to fabricate high-
performance E-mode AlGaN/GaN HEMTs, and then apply this treatment technique
2
to new device structure and integration technology for GaN-based mixed-signal
circuit applications.
This work can be divided into three parts, namely planar-integration of E/D-
mode AlGaN/GaN HEMTs, Si3N4/AlGaN/GaN metal-insulator-semiconductor
heterostructure field-effect transistors (MIS-HFETs), and E-mode dual-gate (DG)
AlGaN/GaN HEMTs. At first, to achieve high density and high uniformity GaN-
based digital circuits, a planar fabrication technology has been developed to integrate
E/D-mode AlGaN/GaN HEMTs on the same chip. A DCFL inverter and a 17-stage
ring oscillator are demonstrated using this technology, in which the whole process is
conducted on a planar surface. After 153-hour thermal stress measurements at 350°C,
the fabricated devices maintain the same DC and RF characteristics, suggesting
excellent thermal reliability of this planar process. Both discrete E/D-mode HEMTs
and integrated DCFL circuits exhibit proper functions within the temperature range
from room temperature (RT) to 350°C, demonstrating a promising potential for GaN-
based high-temperature digital ICs. Secondly, to enhance the gate voltage swing and
suppress the gate leakage current at high temperatures, E-mode Si3N4/AlGaN/GaN
MIS-HFETs are adopted based on CF4 plasma treatment and a two-step Si3N4
deposition technique. In the new MIS structure, the forward gate bias can be applied
up to 7 V, the highest value reported in AlGaN/GaN HEMTs up to now. In addition,
E-mode AlGaN/GaN MIS-HFETs show no current collapse under pulse operation as
a result of the Si3N4 passivation effects in the access region. The DCFL ring
oscillator, which consists of E/D-mode AlGaN/GaN MIS-HFETs, reveals a stable
3
operation from RT to 415°C, indicating the excellent high-temperature working
capabilities. At last, an E-mode DG AlGaN/GaN HEMT, composed of an E-mode
and a D-mode gate electrode, is designed and fabricated. Compared to the E-mode
single-gate AlGaN/GaN HEMTs, a 9-dB gain improvement has been achieved at 2.1
GHz in the DG devices. This achievement can be attributed to the higher output
impedance and smaller feedback capacitance in DG architecture.
4
CHAPTER 1
INTRODUCTION
1.1 Fundamentals of High Electron Mobility Transistors
The high electron mobility transistor (HEMT), which is also named as
heterostructure field-effect transistor (HFET), modulation doped field-effect
transistor (MODFET), two-dimensional electron gas field-effect transistor
(TEGFET), or selectively doped heterostructure transistor (SDHT), was invented
about 20 years ago. The first HEMT device was reported in 1980 [1], after the
successful growth of modulation doped AlGaAs/GaAs heterostructure [2]. By
employing two semiconductor materials with different band-gaps, an electron
potential well is formed at the hetero-interface between AlGaAs and GaAs. The
electrons are confined in this potential well to form a two-dimensional electron gas
(2DEG). Due to the two-dimensional feature of the electrons in this conduction
channel, the carrier mobility can be enhanced remarkably.
The first generation of HEMT structure was constructed in lattice-matched
GaAs-based AlGaAs/GaAs system, which has been widely studied [3] and used in
radio-frequency (RF), microwave and millimeter wave applications. Additional
material systems, including pseudo-morphic HEMT (i.e. with InGaAs channel in
GaAs-based material system) and InP-based InAlAs/InGaAs have also been studied
to achieve higher operating frequencies and lower noise.
5
The fundamental characteristic of the HEMT structure is the conduction band
offset between the materials which construct the barrier and channel layers, that is,
the barrier layer has a higher conduction band while the channel layer has a lower
one. A potential well is then formed which can contain a large number of electrons to
form a 2DEG channel at the hetero-interface due to this conduction band offset. The
schematic structure and the energy-band profile of an AlGaAs/GaAs HEMT are
shown in Fig. 1.1.1 [4].
Semi-insulating Substate(GaAs)
Undoped GaAs
Undoped AlGaAs
n-doped AlGaAs
S G D
EV EC
EF
E
2DEG
Fig. 1.1.1 Schematic structure of an AlGaAs/GaAs HEMT and the corresponding
energy band profile.
In this case, the electrons in the 2DEG channel are provided by the modulation
doped barrier layer. The electrons are separated from the ionized donors by the
potential barrier at the hetero-interface and confined in a two-dimensional
conduction channel, which can reduce the scattering between the carriers and the
ionized donors. This feature ensures a high electron density and mobility, which
make HEMTs promising for high frequency and high power applications.
6
d d
di
EC
EF
qVG
E
at VG,max
at VTH
)(0
/
max
min
0max
dddEVE
qnE
iG
s
Δ++=Δ== ε
Fig. 1.1.2 Energy-band diagram of the metal/n-AlGaAs/GaAs system and the electrostatic field distribution in the AlGaAs layer at the threshold voltage and VG,max.
In a HEMT, by placing a Schottky barrier (metal/semiconductor) gate above the
doped AlGaAs barrier layer, the 2DEG sheet charge concentration can be controlled
by applying an appropriate bias voltage. Figure 1.1.2 shows the energy-band diagram
of the metal/AlGaAs/GaAs system and the electrostatic field distribution in the
AlGaAs barrier layer at threshold voltage and maximum gate bias [5]. Where nS0 is
the maximum 2DEG sheet carrier concentration, d is the thickness of the n-doped
AlGaAs barrier, di is the thickness of the undoped AlGaAs spacer, Δd is the mean
distance of the 2DEG from the AlGaAs/GaAs hetero-interface. When the gate bias
exceeds the maximum value, VG,max, a zero-field or conduction region is created near
the center of the AlGaAs layer. With increasing the forward gate bias, this region
7
forms a parasitic metal semiconductor field effect transistor (MESFET) and
effectively shields the 2DEG channel of the HEMT [6].
Metal AlGaAs GaAs
VG = 0
VG > 0
VG < 0
EF
EF
EF
EF
EF
EF
EC
EC
EC
EF
EF
EF
qVG
qVG
Fig. 1.1.3 Gate-bias-modulated conduction band diagram and 2DEG concentration of an AlGaAs/GaAs HEMT.
Figure 1.1.3 demonstrates the mechanism of the gate-controlled 2DEG channel in
an AlGaAs/GaAs HEMT [4]. With a zero gate bias, there is a 2DEG accumulated at
the hetero-interface, that is, the channel is on. By increasing the gate bias, the
conduction band is modulated and more electrons are accumulated in the 2DEG
channel, which provides higher sheet carrier density and larger current density in the
8
channel. When the gate bias is lowered below the threshold voltage (Vth), the channel
is depleted and there are no electrons in the channel, that is, the channel is pinched
off and no current can go through under the gate.
With a Schottky contact as the gate electrode and two ohmic contacts as the
source and drain electrodes, a heterostructure field effect transistor can be formed on
an AlGaAs/GaAs wafer. The DC output and transfer current-voltage (I-V)
characteristics of a typical AlGaAs/GaAs HEMT device are shown in Fig. 1.1.4 [4].
Linear Saturated
gmVGS
VDS
IDS
IDS
VGS
gm
VTH
Fig. 1.1.4 Typical DC I-V characteristics of an AlGaAs/GaAs HEMT: (a) output curve; (b) transfer curve.
Table 1-1 Advantages of the HEMT structure.
• High electron mobility • Small source resistance • High fT due to high electron velocity in large electrical fields • High transconductance due to small gate-to-channel separation • High output resistance
(a) (b)
9
Compared with conventional Si-based electronic devices, HEMTs have the
following advantages listed in Table 1-1.
After the introduction of the field-effect transistor in the early 1960s, equivalent
circuit models were analyzed by many investigators. These models were modified
after the emergence of GaAs MESFET. After the realization of the HEMTs with
submicron gate length, these models were further modified and the most popular one
is shown in Fig. 1.1.5 [7].
+Vg
-
im = gmVgexp(-j )
g0 Cds
rd
Ld
Cdp
rs
Ls
Cgs2+Cgp
Cgs1
rg
Cg
ri
Lg
G D
S
Cgd
im
ωτ
Fig. 1.1.5 Equivalent circuit model for a HEMT, and the intrinsic circuit model is enclosed by the dashed line.
The equivalent circuit for the intrinsic HEMT is shown within the dashed
rectangular boundary, which includes the gate capacitance (Cg), the charging
resistance (ri), the output conductance (g0), and the drain-to-gate transconductance
(gm). The element Ci (not shown here), which arises due to the passive coupling
10
between the drain and the channel, is not included. These intrinsic parameters,
together with the extrinsic ones, can be used to analyze and predict the AC operation
behavior of the HEMT. They can be extracted from the small-signal S-parameter
measurements. The origins of these elements are shown in Fig. 1.1.6 [8].
rS CgCgs1
rd
Cgs2Cgd
rg
Cds
2DEG
S DG
Fig. 1.1.6 The physical origin of the elements in the equivalent circuit model of AlGaAs/GaAs HEMT.
Combined with the parameter extraction techniques, the equivalent circuit can be
used to characterize the performance of the devices. In the real applications, it is also
desirable to predict the ultimate potential of the devices’ performance or make a
decision which device should be chosen. Then, the first-order calculation of several
performance figures of merit (FOMs) of the active devices will be very useful for
making preliminary judgments. In most cases, the FOMs of interest include the
current gain cutoff frequency (or cutoff frequency, fT), power gain cutoff frequency
(or maximum frequency of oscillation, fmax), output power density (Pout), power
11
added efficiency (PAE), linear gain (GT), minimum noise figure (NFmin), etc. These
FOMs are only first-order indicators of the ultimate performance limit of the devices.
However, these data can be used as a basis of primary comparison between active
devices.
As the frequency increases, the short-circuit current gain (|h21|) of a HEMT
device will decreases. The current gain cutoff frequency of a HEMT device is the
frequency where |h21| falls to unity. In the first order approximation, from the
equivalent circuit shown in Fig. 1.1.5, fT can be driven as:
g
mT C
gfπ2
=
The fT is an approximate criterion which can be used to compare the operation
speed limitation of the devices. In general, the device with a higher fT value usually
can operate at higher frequencies than the one with a lower fT value. In the HEMT
devices, fT can also be represented in term of the saturation drift velocity of the
electrons in the 2DEG channel:
g
satT L
vfπ2
= ,
where vsat is the saturation electron drift velocity and Lg is the gate (channel) length.
Obviously, higher electron velocity and smaller gate (channel) length will result in
higher current gain cutoff frequency.
(1.1)
(1.2)
12
The power gain cutoff frequency, fmax, is the highest frequency at which power
gain can be obtained from the device. That is, the power gain of the device is unity at
fmax. As current gain cutoff frequency, fmax is an indicator of the ultimate operating
frequency of the device. High fmax value is desirable in high frequency applications.
In microwave applications, where the power gain is mostly concerned, fmax attracts
more interest from the designers than fT does. Usually, for simplification, in the
definition of the power gain cutoff frequency, the power gain is the unilateral power
gain (U), so fmax is defined as the frequency at which U reaches unity. For HEMT
devices, the unilateral gain can be represented in terms of the two-port y-parameters
of the device:
)]Re(*)Re()Re(*)[Re(4||
21122211
21221
yyyyyyU+−
=
The expression of fmax can be extracted from the device equivalent circuit shown
in Fig. 1.1.5. In the first-order approximation, fmax can be written as [9]:
gi
dsT
RRRff+
=2max ,
where Ri is the channel charging resistance, Rg is the gate parasitic resistance, Rds is
the output resistance, and fT is the current gain cutoff frequency. This equation
(1.3)
(1.4)
13
provides some useful relationship between fT and fmax when the device works at high
frequency.
I DS
(mA
/mm
)Imax
Imin
KNEE VOLTAGE
RL-Ropt
OFF-STATE BREAKDOWN
CLASS-A BIAS POINT
Vk VBRVDS (V)
Fig. 1.1.7 Schematic representation of a HEMT operating in Class A.
As mentioned previously, HEMT is a promising candidate for high frequency
and high power applications due to its high carrier mobility and high current
handling capability. The small-signal FOMs, fT and fmax, provide guidelines for the
frequency performance of HEMTs, while to evaluate microwave large signal (or
power) performance of them, some other FOMs should be considered. Two
important large-signal FOMs are the output power density (Pout) and the power added
efficiency (PAE). For class A operation, the theoretical maximum output power can
be found out by:
))((21
minmaxmax, KBRout VVIIP −−= ,
(1.5)
14
where Imax is the maximum channel current, Imin is the minimum drain current due to
the gate-drain and source-drain leakage, VBR is the off-state breakdown voltage of the
device, and VK is the knee voltage. This approximate equation of the maximum
output power is graphically presented in Fig. 1.1.7 [10], where the device is assumed
to work along the ideal load line (a straight line) with a constant knee voltage and an
adequate large-signal gain.
The other important microwave large-signal FOM is the power added efficiency,
PAE. For class A operation, the PAE of the device can be written in terms of the
power gain as:
⎟⎟⎠
⎞⎜⎜⎝
⎛−=
−=
−=
aDC
aout
DC
inout
GPGP
PPPPAE 11
21)/11( ,
where Ga is the power gain of the device. It can be found the maximum value of
PAE for class A operation approaches 50% with infinite Ga. For class B operation,
the PAE is higher, which has a maximum value of π/4 (~78.5%).
1.2 Developments of AlGaN/GaN HEMTs
In early 1990s, with the successful growth of high-quality III-nitride epitaxial
films by advanced metal-organic chemical vapor deposition (MOCVD) technique,
the AlGaN/GaN heterostructure was demonstrated for the first time in 1991 [11].
Owing to their unique characteristics, such as large bandgap, high electric field
(1.6)
15
strength, and good electron transport properties, GaN-based HEMTs are emerging as
promising candidates for high voltage, high power and high frequency applications
[12]. Intensive investigations have been carried out on GaN-based HEMTs and
significant progress has been made in the last decade [13]-[28].
Semi-insulating Substrate
Undoped GaN
Undoped AlGaN
n-doped AlGaN
Fig. 1.2.1 Schematic structure of an AlGaN/GaN HEMT and the corresponding energy-band profile.
Similar to the GaAs-based HEMTs, GaN-based HEMTs employ two kinds of
materials with different bandgaps as the barrier and channel layer. The most popular
one is AlGaN/GaN HEMTs. Due to the conduction band offset between AlGaN and
GaN, an electron potential quantum well is formed at the hetero-interface between
AlGaN and GaN. The electrons are confined in this potential well to form a 2DEG.
The electrons transport in a two-dimensional way, which can largely improve the
electron mobility. The schematic cross-section and the energy-band profile of the
AlGaN/GaN HEMT are shown in Fig. 1.2.1.
16
As reported in [29], nitride-based semiconductors have a unique property
compared to GaAs system, a very strong polarization field within the crystal. This
polarization field has profound impacts on the electronic properties of GaN-based
heterostructures.
Ga-face N-face
Substrate Substrate
[000
1]
[000
1]
Fig. 1.2.2 Crystal structure of (a) Ga-faced and (b) N-faced wurtzite GaN
The polarization field in the nitride-based heterostructures comes from two parts,
the spontaneous polarization and the piezoelectric polarization. Due to the non-
central symmetry, nitrides exhibit a macroscopic spontaneous polarization field
along the hexagonal c-axis in the wurtzite lattice. In addition, nitrides have a strain-
induced piezoelectric polarization, which is much higher than that in the traditional
III-V semiconductors [30]. The direction of the polarization field in nitrides depends
on the polarity of the crystal [31], that is, whether it’s Ga-faced [Fig. 1.2.2 (a)] or N-
faced [Fig. 1.2.2 (b)]. Almost all MOCVD-grown nitrides are Ga-faced, while the
nitrides grown in MBE system are usually N-faced. With the assistance of the
17
polarization field, a polarization charge density of 1013 cm-2 can be achieved in a
strained-Al0.3Ga0.7N/relaxed-GaN system [32].
Fig. 1.2.3 Band profiles of the AlGaN/GaN heterostructures with different AlGaN thickness, which demonstrate the surface states’ contribution to the 2DEG formation.
In the AlGaN/GaN heterostructure, the origin of 2DEG is quite different from that
in AlGaAs/GaAs system. Due to the strong polarization field in the AlGaN/GaN
heterostructure, a sheet carrier density of ~1013 cm-2 can be obtained at the
AlGaN/GaN interface without any modulation doping [33]. As doping concentration
is zero in this case, the 2DEG does not come from the conventional modulation
doping in the AlGaN layer. Up to now, the most popular model, proposed by
Ibbetson et al. [34], suggests that the donor-like surface states could serve as the
source of the electrons in the 2DEG channel. With the electrostatic field induced by
the polarization field in the AlGaN/GaN heterostructure, the band profile and the
electron distribution are modified and a large number of electrons transfer from the
donor-like surface states to the AlGaN/GaN hetero-interface that is lower in energy,
18
forming a 2DEG. The mechanism of the surface state’s contribution to 2DEG can be
illustrated by Fig. 1.2.3 for an undoped AlGaN barrier sample. If the donor-like
surface state is sufficiently deep and lies below Fermi level, EF, there is no 2DEG in
the channel [Fig. 1.2.3 (a)]; when the barrier thickness increases and the surface state
energy level reaches EF, the electrons are then able to transfer from the occupied
states to empty conduction band states at the interface, creating 2DEG in the channel
and leaving positive surface charges behind, as shown in Fig. 1.2.3 (b).
Table 1-2 Historical Development of GaN-based HEMTs.
Year Event Authors Ref. 1969 GaN by hydride vapor phase epitaxy Maruska and Tietjen [36] 1971 GaN by MOCVD Manasevit et al. [37] 1992 AlGaN/GaN two-dimensional electron gas Khan et al. [38] 1993 AlGaN/GaN HEMT Khan et al. [35] 1994 Microwave AlGaN/GaN HFET Khan et al. [39] 1996 Microwave power AlGaN/GaN MODFET Wu et al. [40] 1999 Reveal current compression in GaN MODFET Kohn et al. [41] 1999 6.9 W/mm @ 10 GHz GaN HEMT on SiC Sheppard et al. [42] 2000 Surface passivated AlGaN/GaN HEMTs Green et al. [43] 2004 30 W/mm @ 8 GHz GaN HEMT with field plate Wu et al. [16] 2005 High performance enhancement-mode HEMT Cai et al. [44]
Due to the advantages of the GaN-based heterostructures, tremendous progress
has been made in the development of AlGaN/GaN HEMT since it was firstly
demonstrated by Khan et al. in 1993 [35]. Table 1-2 lists the most representative
developments of GaN-based HEMTs.
19
1.3 Enhancement/Depletion-mode AlGaN/GaN HEMTs and Mixed-Signal
Applications
1.3.1 Synthesis of Enhancement-mode AlGaN/GaN HEMTs
In the AlGaN/GaN heterostructure, high-density 2DEG induced by spontaneous
and piezoelectric polarization effects presents the conventional AlGaN/GaN HEMTs
as depletion-mode (D-mode) transistors with a threshold voltage (Vth) typically
around -4 V. Usually, the Vth of the AlGaN/GaN HEMTs depends on the design of
the epitaxial structure, namely, the Al composition, Si doping concentration, and the
thickness of the AlGaN barrier. Methods that can further modify the threshold
voltage during the device fabrication stage will provide additional flexibilities in
device fabrication and circuit applications. When the threshold voltage is adjusted to
be positive, enhancement-mode (E-mode) operation is realized. Compared to the D-
mode HEMTs, E-mode devices allow elimination of negative-polarity voltage supply,
and therefore, reduce the circuit complexity and system cost significantly.
A common fabrication technique of modifying the HEMTs’ threshold voltage,
the so-called “gate-recess” technique, is to reduce the thickness of the barrier layer
under the gate metal. In the generally used AlGaN/GaN heterostructure for HEMTs,
where Al composition is in the range of 15 - 35% and the AlGaN barrier thickness is
around 20 nm, the reduction in the AlGaN thickness by the gate recess results in a
decreasing polarization-induced 2DEG density. And with the help of the gate metal
work function, the threshold voltage can be shifted positively. With a deep enough
20
gate-recess etching, the Vth can reach a positive value and E-mode HEMTs are
formed, with the schematic diagram shown in Fig. 1.3.1 [45].
S D
GaN
AlGaNSiNx
Recessed-Gate
Fig. 1.3.1 Schematic diagram of an E-mode HEMT with the recessed gate.
For a conventional III-V compound semiconductor, such as GaAs and InP, there
are sufficient highly-selective chemical wet-etching recipes [46] that can be applied
to recess etching. The wet etching has the major advantage of low damages.
However, a compatible wet-etching method for AlGaN/GaN heterostructure is still
lacking up to now. As an alternative approach, a chloride-based dry inductively
coupled plasma reactive ion etching (ICP-RIE) has been employed to fulfill this task
by several groups [45], [47]-[51]. This approach can effectively modify the Vth of
AlGaN/GaN HEMTs to positive direction. However, the ICP-RIE etching will
introduce damages and defects to the AlGaN layer, which will affect the device
performance. The post-etching rapid thermal annealing (RTA) at 700ºC was found to
be able to repair the damages [48], [51]. But the RTA at such high temperatures will
not be compatible with the gate metal (i.e. Ni/Au) and has to be carried out prior to
the gate metal deposition. As a result, the photolithography of the gate electrode and
21
recess etching has to be conducted separately, which brings undesirable complexity
to the device fabrication. In addition, the uniformity in the recess-etching depth and,
consequently the uniformity in the threshold voltage and gate capacitance, are
another challenging issue for this method.
Recently, our group demonstrated a technique of fabricating high-performance
self-aligned E-mode AlGaN/GaN HEMTs using the fluoride-based plasma treatment
[44], [52]-[53]. No change in the AlGaN thickness is required in this technology. The
control of the threshold voltage is realized through a modulation of energy band by
fluorine ions implanted in the AlGaN/GaN heterostructure during the plasma
treatment. As the fluorine ions have a strong electronegativity and are negatively
charged, the potential in the AlGaN barrier and the 2DEG channel can be effectively
raised. As a result, the Vth can be shifted to a positive value, and E-mode HEMTs can
be fabricated. A post-gate annealing at a gate-electrode-compatible temperature of
400ºC proves to be effective in recovering the plasma-induced damages.
The fluorine ions, which are incorporated into the AlGaN layer by CF4 plasma
treatment, are confirmed by secondary ion mass spectrum (SIMS) measurements [52].
It can be concluded from the SIMS results that the implanted fluorine ions have a
good thermal stability in the AlGaN layer up to 700ºC. According to our recent
DLTS (deep-level transient spectroscopy) observations, the fluorine ions
incorporated in the AlGaN barrier introduce a deep level state near the mid-bandgap.
Therefore, the fluorine ions are believed to provide negatively charged acceptor-like
states in the AlGaN layer. These fixed negative charges will cause an upward
22
bending of the conduction band in the AlGaN layer, as shown in Fig. 1.3.2.
Compared to the untreated AlGaN/GaN HEMT structure [Fig. 1.3.2 (a)], the plasma-
treated structure has its conduction band minimum above Fermi level, indicating a
completely depleted channel and E-mode operation. In addition, the immobile
negatively charged fluorine ions raise the conduction band, leading to an additional
barrier height ΦF, as shown in Fig. 1.3.2 (b). This enhanced barrier can significantly
suppress the gate Schottky diode current of the AlGaN/GaN HEMTs in both reverse
and forward bias conditions.
Fig. 1.3.2 Conduction band schematic diagrams of (a) conventional D-mode AlGaN/GaN HEMT and (b) E-mode HEMT with CF4 plasma treatment.
There have been several other reports on the fabrication of E-mode AlGaN/GaN
HEMTs besides gate recess etching and fluoride plasma treatment techniques. Using
a thin AlGaN barrier (10 nm), Khan et al. [54] realized an E-mode HEMT with a
peak transconductance of 23 mS/mm. Hu et al. [55] demonstrated an E-mode HEMT
with selectively re-grown pn junction gates and showed a peak transconductance of
10 mS/mm. Moon et al. [47] and Kumar et al. [48] used reactive ion etching for gate
23
recess to fabricate E-mode AlGaN/GaN HEMTs, with large on-resistance [47] and
nonzero (~20 mA/mm) drain current at zero gate bias [48]. Started with a D-mode
HEMT, Endoh et al. [56] was able to convert it to E-mode HEMT using Pt-based
gate electrode annealed at high temperature. Such an approach requires a D-mode
HEMT with the threshold voltage already close to zero. Y. Uemoto et al. [26] also
realized the E-mode operation by growing p-AlGaN layer under the gate to lift up the
potential in the channel. The E-mode HEMT exhibits a peak transconductance of
about 70 mS/mm. But the hole injection will affect the device turn-off characteristics
in this p-AlGaN layer technology. The E-mode device characteristics are compared
in Table 1-3 among different fabrication technologies. It seems that the E-mode
HEMTs fabricated by CF4 plasma treatment exhibit excellent DC and RF
performance, compared to other methods.
Table 1-3 E-mode AlGaN/GaN HEMT performance comparison
Ref Technology Gate
length Imax
(mA/mm) Peak gm
(mS/mm) Vth (V)
fT & fmax (GHz)
[54] Thin AlGaN 1 μm --- 23 0.05 ---
[55] PN junction gate 10 μm 40 10 --- ---
[47] Gate recess etch 0.2 μm 100 85 0 24 / 45
[48] Gate recess etch 1 μm 470 248 0.075 8 / 26
[56] Pt-based gate 0.12 μm 450 230 0 58 /109
[26] P-layer gate 2 μm 200 70 1 4.2 / 10.7
[44] Plasma treatment 1 μm 313 151 0.9 10 / 34.3
24
1.3.2 Mixed-signal applications of E/D-mode AlGaN/GaN HEMTs
Table 1-4 Properties of competing materials in power electronics.
Semiconductor (commonly used compounds)
Characteristic Unit Silicon
Gallium arsenide (AlGaAs/ InGaAs)
Indium phosphide
(InAlAs/ InGaAs)
Silicon carbide
Gallium nitride
(AlGaN/ GaN)
Bandgap eV 1.1 1.42 1.35 3.26 3.49
Electron mobility at 300 K
cm2/Vs 1500 8500 5400 700 1000- 2000
Saturated (peak) electron velocity
x107 cm/s
1.0 (1.0)
1.3 (2.1)
1.0 (2.3)
2.0 (2.0)
1.3 (2.1)
Critical breakdown field
MV/cm 0.3 0.4 0.5 3.0 3.0
Thermal conductivity
W/cm·K 1.5 0.5 0.7 4.5 >1.5
Relative dielectric constant
εr 11.8 12.8 12.5 10.0 9.0
In the RF and microwave power amplifier markets, a variety of PA technologies
are competing each other, such as Si lateral-diffused metal-oxide-semiconductors
and bipolar junction transistors, GaAs metal-semiconductor field-effect transistors
(MESFETs), GaAs heterojunction bipolar transistors, SiC MESFETs, and GaN
HEMTs. Compared to other competing materials, the material properties of GaN are
presented in Table 1-4 [57]. Wide bandgap, large breakdown electric field and high
electron saturated velocity make it as an excellent candidate for RF and microwave
power amplifiers. The competitive advantages of GaN-based amplifiers for a
25
commercial product are described in Table 1-5 [13]. The first column states the
required performance benchmarks for any power device technology and the second
column lists the enabling features of GaN-based devices that fulfill this need. The
last column summarizes the resulting performance advantages at the system level and
to the customer. The highlighted features offer the most significant product benefits.
Table 1-5 Competitive advantages of GaN devices
Need Enabling Feature Performance Advantage
High Power Density Wide Bandgap, High Field Compact, Ease of Matching
High Voltage Operation High Breakdown Field Eliminate/Reduce Step Down
High Linearity HEMT Topology Optimum Band Allocation
High Frequency High Electron Velocity Bandwidth, m-Wave/mm-wave
High Efficiency High Operating Voltage
Power Saving, Reduced Cooling
Low Noise High Gain, High Velocity High Dynamic Range receivers
High Temperature Operation Wide Bandgap Rugged, Reliable, Reduced
Cooling
Thermal Management SiC Substrate High Power Devices with Reduced Cooling Needs
Technology Leverage Direct Bandgap: Enable for Lighting
Driving Force for Technology: Low Cost
Besides RF and microwave power amplifiers, AlGaN/GaN HEMTs also exhibit
the promising potential to construct digital integrated circuits (ICs), especially for the
operations at high temperature that is impossible for silicon or GaAs-based
technologies. The high-temperature digital ICs can provide the enabling technology
in intelligent control and sensing circuits for automotive engines, aviation systems,
26
chemical reactors and well-logging for oil exploration systems [58]. Due to lack of p-
channel AlGaN/GaN HEMTs, a circuit configuration like CMOS can not be
implemented yet. Using n-channel HEMTs, direct-coupled FET logic (DCFL), as
shown in Fig. 1.3.3, which features integrated E/D-mode HEMTs, offers the simplest
circuit configuration [59]. For a long time, the development of GaN-based digital ICs
has been hindered by the lack of compatible integration process for both D-mode and
E-mode AlGaN/GaN HEMTs. As a tradeoff, Hussain et al. [60] used an all-D-mode-
HEMT technology and buffered FET logic (BFL) configuration to realize an inverter
and a 31-statge ring oscillator that includes 217 transistors and two negative voltage
supplies.
Fig. 1.3.3 DCFL circuit schematics of (a) E/D-mode HEMT inverter, (b) NOR gate and (c) NAND gate logic circuits.
With the development low-damage Cl2-based ICP-RIE technology, Micovic et al.
[61] applied the technology of two-step gate recess etching and used plasma-
enhanced chemical vapor deposition (PECVD) grown SiN as the gate metal
27
deposition mask to fabricate E-mode HEMTs, which were integrated with the D-
mode AlGaN/GaN HEMTs together. By using this technology, they demonstrated a
31-stage DCFL ring oscillator. Recently, our group developed a technique featuring
fluoride-based plasma treatment and post-gate annealing to realize self-aligned E-
mode AlGaN/GaN HEMTs. Based on CF4 plasma treatment, a monolithic integration
of E/D-mode AlGaN/GaN HEMTs for digital ICs has been demonstrated [53], [62].
Compared to the technology of two-step gate recess etching, the fluoride-based
plasma treatment technique saves one mask for fabricating GaN-based digital ICs.
1.4 Objective of This Work
This work mainly focuses on applying fluoride-based plasma treatment technique
to realize the integration of enhancement/depletion-mode HEMTs for GaN-based
mixed-signal circuit applications. New isolation technology and new device structure
are developed to improve the circuit and device performance. In addition, the high-
temperature characteristics of AlGaN/GaN HEMTs and circuits have been
investigated in detail for GaN-based high-temperature digital IC applications.
Chapter 2 reports a planar fabrication technology for integrating
enhancement/depletion-mode AlGaN HEMTs. The technology relies heavily on CF4
plasma treatment, which is used in two separate steps to achieve two objectives: 1)
active device isolation; and 2) threshold voltage control for the enhancement-mode
HEMT formation. Compared to the standard mesa etching technique, the plasma
28
treatment can achieve the same isolation results, and show no device DC and RF
performance degradation after a 153-hour thermal stress measurement. The device
and circuit high-temperature characterizations are also carried out from room
temperature to 350ºC.
Chapter 3 demonstrates an enhancement-mode Si3N4/AlGaN/GaN metal-
insulator-semiconductor HFETs by combing the CF4 plasma treatment technique and
a two-step Si3N4 deposition process. The threshold voltage has been shifted from -4
V (for depletion-mode substrate) to 2 V using this technique. The forward gate bias
of the E-mode MIS-HFETs is as large as 7 V, at which a maximum current density of
420 mA/mm is obtained. At the same time, the depletion-mode AlGaN/GaN MIS-
HFETs are fabricated on the same chip. A direct-coupled FET logic inverter and 17-
stage ring oscillator have been demonstrated by integrating enhancement/depletion-
mode AlGaN/GaN MIS-HFETs.
Chapter 4 contains the work of AlGaN/GaN dual-gate HEMTs, composed of an
enhancement-mode gate and a depletion-mode gate. Compared to the enhancement-
mode single-gate devices, the dual-gate AlGaN/GaN HEMTs have comparable DC
characteristics, but achieve a 9-dB gain improvement at 2.1 GHz in small signal RF
measurements. The gain improvement can be attributed to the larger output
impedance and smaller feed back capacitance in dual-gate structure.
Finally, the work is summarized in Chapter 5, and future plan for the thesis work
is also provided.
29
CHAPTER 2
Temperature Dependence and Thermal Stability of Planar-Integrated
Enhancement/Depletion-mode AlGaN/GaN HEMTs and Digital Circuits
2.1 Motivation of Planar Integration of E/D-mode AlGaN/GaN HEMTs for
GaN-based High Temperature Digital Circuits
With the wide bandgap, excellent thermal and chemical stability, AlGaN/GaN
high-electron mobility transistors (HEMTs) are inherently attractive for applications
in high temperature electronics [53], [61], [63]-[66]. The direct-coupled FET logic
(DCFL) circuit, which features integrated enhancement/depletion-mode (E/D-mode)
HEMTs, offers a simple configuration for digital integrated circuits. Recently, the
DCFL digital ICs, based on E/D-mode AlGaN/GaN HEMTs, have been
demonstrated using a recess gate [61] and a fluoride-based plasma treatment
technique [53], [62], both of which used an inductively coupled plasma (ICP) mesa
etching to achieve the active device isolation. However, the three-dimensional mesas
may impose significant limitations on the minimum size realized by
photolithography and are not desirable for digital IC applications that require high-
density and high-uniformity circuit integrations. Thus, a planar process is critical to
the success of GaN-based digital IC technology, as seen from the successful
development of commercial GaAs MESFET ICs [67]-[68].
For the planar GaN-based device isolation, most of the works have been focused
on implanting high energy H+, He+, N+, Mg+ or O+ ions that introduce significant
30
damages to crystal lattice and cut off the current path [69]-[73]. A multiple energy
Zn+ implantation [74], N+ implantation [75], and P+/He+ co-implantation [76] have
been implemented in the fabrication of AlGaN/GaN HEMTs. Recently, our group
developed a technique featuring fluoride-based plasma treatment and post-gate
annealing to realize E-mode AlGaN/GaN HEMTs [44], [52], [77]-[78]. The basic
idea is to introduce fluorine ions into the AlGaN barrier under the gate region.
Because of the strong electronegativity of the fluorine ions, they can provide the
fixed negative charges in the AlGaN layer, effectively depleting the two-dimensional
electron gas (2DEG) in the channel [52]. The electron-depletion capability of the
fluorine ions indicates the possibility of using fluorine plasma treatment for device
isolation. However, the isolation mechanism lies in the surface potential modulation
rather than the physical damages as in the case of ion implantation.
In this work, we employ the fluorine plasma treatment technique to achieve the
active device isolation in a planar integration of E/D-mode AlGaN/GaN HEMTs.
Without any dry etching for mesa formation and gate recess, the plasma treatment
can achieve the same isolation between active devices as the three-dimensional mesa
approach and both D-mode and E-mode HEMTs are fabricated on the same chip.
Since the GaN-based digital ICs are attractive for high-temperature applications
and thermal stability is always an important issue in any device isolation techniques,
we will report the detailed investigation of the temperature dependence and thermal
stability of the planar-integrated E/D-mode AlGaN/GaN HEMTs and digital
integrated circuits. High-temperature characterizations of E/D-mode HEMTs, DCFL
31
inverter and ring oscillator are conducted from room temperature (RT) up to 350ºC.
At 350 ºC, the ring oscillator still functions properly. In addition, the thermal stress
measurements (at 350ºC) are carried out to evaluate the thermal reliability of the
planar process. After 153-hour thermal stress, the E/D-mode HEMTs show very
small degradation in DC and RF performances, suggesting the excellent thermal
stability in the plasma-induced inter-device isolation.
2.2 Device Structure and Fabrication
Fig. 2.2.1 Schematic cross-section of the AlGaN/GaN HEMT device.
The AlGaN/GaN HEMT structures, with the schematic cross section shown in
Fig. 2.2.1, are grown on c-plane sapphire substrates in an Aixtron AIX 2000 HT
metal-organic chemical vapor deposition (MOCVD) system. The HEMT structure
consists of a ~ 50-nm thick low temperature GaN nucleation layer, a 2.5-μm thick
32
unintentionally doped GaN buffer layer, and an AlGaN barrier layer with a nominal
30% Al composition. The barrier layer is composed of a 3-nm undoped spacer, a 21-
nm carrier supplier layer doped with Si at 2x1018 cm-3, and a 2-nm undoped cap layer.
Hall measurements were conducted on the sample at room temperature through a
Hall Bridge pattern fabricated on the sample, with the layout shown in Fig. 2.2.2.
The room temperature hall measurements of the structure yield an electron sheet
density of 1.3 x 1013 cm-2 and an electron mobility of 950 cm2/Vs.
Fig. 2.2.2 Layout of the Hall Bridge for Hall measurements.
The process flow is illustrated in Fig. 2.2.3. At first, the source/drain ohmic
contacts of E/D-mode HEMTs are formed simultaneously by a deposition of e-beam
evaporated Ti/Al/Ni/Au (20 nm/150 nm/50 nm/80 nm) and rapid thermal annealing
(RTA) at 850ºC for 30 s, as shown in Fig. 2.2.3 (a). Secondly, the active regions for
both E/D-mode devices are patterned by photolithography, which is followed by the
CF4 plasma treatment in a reactive ion etching (RIE) system [Fig. 2.2.3 (b)]. The
plasma power is 300 W, and the treatment time is 100 s. The gas flow is controlled to
33
Fig. 2.2.3 Schematics showing the process flow of E/D-mode HEMTs: (a) ohmic contact; (b) active region definition by plasma treatment; (c) D-mode gate formation;
(d) E-mode gate definition and plasma treatment; (e) SiN passivation.
34
be 150 sccm, and the DC bias is set to be 0 V. This step is used to form the device
isolation. As pointed in Fig. 2.2.3 (b), the isolation regions are the locations where a
large amount of F- ions are incorporated in the AlGaN layers, and then deplete the
2DEG in the channel. Next, the D-mode HEMTs’ gate electrodes are patterned by
the e-beam evaporation of Ni/Au (50 nm/300 nm) and liftoff [Fig. 2.2.3 (c)].
Subsequently, the E-mode HEMTs’ gate electrodes and interconnections are defined.
Prior to the e-beam evaporation of Ni/Au, the gate regions are treated by CF4 plasma
at 170 W for 150 s, as shown in Fig. 2.2.3 (d). This step performs the function of
converting the treated gate region from D-mode to E-mode [44], [52]. A 200-nm-
thick SiN passivation layer is deposited by the PECVD, and the probing pads are
opened [Fig. 2.2.3 (e)]. At last, the sample is annealed at 400ºC for 10 min to repair
the plasma-induced damage in the AlGaN barrier and the channel of the E-mode
HEMTs. The layout for device fabrication is shown in Fig. 2.2.4, and more process
details can be found in Appendix A.
Source
Source
DrainGate
Fig. 2.2.4 Layout for the AlGaN/GaN HEMTs fabrication
35
As a comparison, the D-mode devices are also fabricated on another piece of
sample from the same substrate by standard process, in which Cl2/He ICP etching is
used to define a mesa as the device active region. For the DCFL inverter and ring
oscillator shown in this paper, the E-mode HEMT driver is designed with a gate
length, gate-source spacing, gate-drain spacing, and gate width of 1.5, 1.5, 1.5, and
50 μm, respectively; the D-mode load is designed with a gate length, gate-source
spacing, gate-drain spacing, and gate width of 4, 3, 3, and 8 μm, yielding a ratio
β=(WGE/LGE)/(WGD/LGD) of 16.7. The discrete E-mode and D-mode HEMTs with 1.5
x 100 μm2 gate dimensions are also fabricated by planar process for DC and RF
characterizations.
Figure 2.2.5 shows the microscopy photos of the overall and zoom-in views of
the HEMT devices we fabricated.
Fig. 2.2.5 Microscopy photos of the fabricated HEMT devices: (a) overall view; and
(b) zoom-in view of the active region.
(a) (b)
36
2.3 Discrete E/D-mode AlGaN/GaN HEMTs by Planar Process
2.3.1 Temperature Dependence
For the E/D-mode HEMTs fabricated by the planar process, the DC output
characteristics are plotted in Fig. 2.3.1. The peak current density for D-mode and E-
mode HEMTs are about 730 and 190 mA/mm, respectively. Both E-mode and D-
mode devices can be pinched off completely when gate bias is below threshold
voltage. The current drop in D-mode HEMT under high gate bias is due to the high
current level and self heating effects during device operation. This current
degradation can be solved using SiC substrate with better thermal conductivity,
instead of sapphire. The device DC measurement details can be found in Appendix B.
Fig. 2.3.1 DC output characteristics of (a) D-mode HEMT and (b) E-mode HEMT by the planar process
Figure 2.3.2 shows the DC transfer characteristic comparison between planar
process and standard mesa etching technology. It can be seen that the D-mode
HEMT drain leakage current for planar process is about 0.3 mA/mm, which has
0 2 4 6 8 100
200
400
600
800 (a)VGS = -6V ~ 1V; step = 1V
I D (m
A/m
m)
VDS (V)0 2 4 6 8 10
0
50
100
150
200 (b)VGS = 0V ~ 3.5V step = 0.5V
I D (m
A/m
m)
VDS (V)
37
reached the same level as the devices fabricated by standard mesa etching. In
addition, both of them exhibit comparable drain current and transconductance (gm)
performance, as seen from Fig. 2.3.2. We also measure the leakage current between
two pads (400 x 100 μm2) with the spacing of 150 μm. At the DC bias of 10 V, the
leakage current by planar process is about 38 μA, at the same level of the standard
mesa etching sample (~30 μA). From all results above, we can conclude that,
compared with ICP mesa etching, the fluoride-based plasma treatment can achieve
the same level of device isolation, enabling a complete planar integration process.
The E-mode HEMTs exhibit smaller transconductance compared to the D-mode
devices, due to the incomplete recovery of the plasma induced damage which causes
a slight mobility reduction [44], [52].
Fig. 2.3.2 Transfer characteristics comparison between the planar process and the standard ICP mesa etching process: (a) drain current and (b) transconductance
comparison. The source-drain voltage (VDS) is fixed at 10 V.
To evaluate the temperature dependence of the planar-integrated E/D-mode
HEMTs, on wafer high-temperature characterizations of the devices are performed
-10 -8 -6 -4 -2 0 2 410-1
100
101
102
103 (a)
I D (m
A/m
m)
VGS (V)
Planar D-HEMT Planar E-HEMT Std. D-HEMT
VDS = 10 V
-10 -8 -6 -4 -2 0 2 4-20
020406080
100120140 (b)
Gm
(mS/
mm
)
VGS
38
from RT (25ºC) to 350ºC in the air ambient. Figure 2.3.3 shows the I-V transfer
characteristics of the D-mode HEMTs by planar process within the temperature
range of 25ºC ~ 350ºC. It can be seen that both the drain current and
transconductance drop as the temperature rises. When gate is biased at 1 V, the
maximum drain current density (Imax) decreases by 48% at 350ºC compared to RT,
and the peak gm drops by 47% at 350ºC. The current and gm reductions at high
temperatures can be attributed to the mobility degradation of 2DEG [79]. The off-
state leakage current increases when temperature rises [Fig. 2.3.3 (a)], but still in an
acceptable level even at 350°C. It was well known that the intrinsic carrier excitation
in semiconductor will be more serious at high temperatures due to higher thermal
activation energy, and the device will become leakier, leading to larger off-state
leakage current at high temperatures.
Fig. 2.3.3 D-mode HEMTs transfer characteristics comparison at different temperatures: (a) drain current and (b) transconductance.
-10 -8 -6 -4 -2 0 210-1
100
101
102
103
104
(a)
I D (m
A/m
m)
VGS (V)
RT 100oC 150oC 250oC 350oC
VDS = 10 V
-10 -8 -6 -4 -2 0 2
0
40
80
120
160(b) RT
100oC 150oC 250oC 350oC
VDS = 10 V
Gm
(mS/
mm
)
VGS (V)
39
Fig. 2.3.4 E-mode HEMTs transfer characteristics comparison at different temperatures: (a) drain current in log scale, (b) drain current in linear scale and (c)
device transconductance.
The E-mode HEMT’s transfer characteristics at different temperatures are given
in Fig. 2.3.4. The threshold voltage (Vth) is defined as the gate bias intercept of the
linear extrapolation of the drain current from the point of peak gm in transfer curves.
Both the threshold voltage and pinch-off source-drain leakage current (Ileak) are
plotted against the temperature for E/D-mode HEMTs in Fig. 2.3.5. When the
temperature rises from RT to 350ºC, Ileak increases from 0.29 to 1.16 mA/mm for D-
mode HEMTs, while it increases from 0.20 to 0.53 mA/mm for E-mode HEMTs. A
significant difference is observed in the threshold voltage shift between D-mode and
E-mode HEMTs at high temperatures. The threshold voltage of D-mode HEMTs
-2 -1 0 1 2 3
0
20
40
60
80
100
120
140
Vth(350oC)
Vth(RT)
(b)
I D (m
A/m
m)
VGS (V)
RT 350oC
VDS = 10 V
-6 -4 -2 0 2 410-1
100
101
102
(a)
I D (m
A/m
m)
VGS (V)
RT 100oC 150oC 250oC 350oC
VDS = 10 V
-6 -4 -2 0 2 4
0
20
40
60
80
100
120 (c) RT 100oC 150oC 250oC 350oC
VDS = 10 V
Gm
(mS/
mm
)
VGS (V)
40
changes little at high temperatures, as seen from Fig. 2.3.3 and Fig. 2.3.5. But the E-
mode HEMT’s Vth shifts to the negative direction when the temperature increases. As
shown in Fig. 2.3.4 (b), the E-mode HEMT’s Vth varies from 1.14 V at RT to 0.77 V
at 350ºC, exhibiting a temperature coefficient of -1.14 mV/K. But within the whole
temperature range (RT ~ 350 ºC), the E-mode device keeps its threshold voltage as a
positive value all the time.
0 50 100 150 200 250 300 350 400-0.5
0.0
0.5
1.0
1.5
2.0
-5
-4
-3
-2
-1
0
1
2
,,
I leak
(mA
/mm
)
Temperature (oC)
E-mode HEMT D-mode HEMT
Vth (V
)
Fig. 2.3.5 Temperature dependence of threshold voltage (Vth) and off-state drain leakage current (Ileak) for E/D-mode HEMTs by the planar process.
The different trends in the Vth-temperature dependence between the E-mode and
D-mode HEMTs could be due to the presence of fluorine ions in the AlGaN layer of
the E-mode HEMTs. As we mentioned before, the fixed fluorine ions have played a
key role in shifting Vth during the formation of E-mode HEMTs. According to our
recent DLTS (deep-level transient spectroscopy) measurement [80] and
photoconductivity measurement, the fluorine ions incorporated in the AlGaN layer
41
introduce acceptor-like deep-level states that are near the mid-bandgap. As the
temperature increases, some of the electrons confined in the fluorine ions can be
thermally excited, leading to a reduction in the number of the negatively-charged
fluorine ions in the AlGaN layer. Therefore, the E-mode HEMT’s Vth tends to shift to
the negative direction as the temperature rises. Even with this negative shift in Vth,
the E-mode HEMTs maintained a positive threshold voltage throughout the entire
high temperature testing, e.g., Vth is 0.77 V even at 350ºC [Fig. 2.3.4 (b)]. It should
be noted that the fluorine treatment technique is robust enough to allow us to adjust
and optimize the threshold voltage at the specified temperature by changing the
fluorine plasma treatment dose.
Figure 2.3.4 (a) and (c) reveal that the E-mode drain current decreases 26% at the
same bias and gm drops 47% at 350ºC compared to RT. The current reduction of E-
mode HEMTs is much smaller than D-mode HEMTs (48%) due to the different shift
occurred in the E-mode HEMT’s Vth. At high temperatures, the E-mode HEMTs
exhibit a more negative Vth compared to RT, which will help to increase the current
density; in D-mode operation, Vth changes little at high temperatures, leading to a
larger current drop than E-mode HEMTs. Nevertheless, both E-mode and D-mode
AlGaN/GaN HEMTs show stable operation at 350ºC, indicating good thermal
stability of the planar process based on CF4 plasma treatment.
The high-temperature characteristics of sub-threshold slope are also investigated
for both E-mode and D-mode HEMTs, as shown in Fig. 2.3.6. From the transfer
42
curve in log scale, the HEMT sub-threshold slope (S) can be defined by the following
equation [81],
( )[ ]D
GS
IddVSlog
= .
From Fig. 2.3.6, we can see the drain current slopes below threshold voltage become
smaller at 350°C than RT for both E-mode and D-mode HEMTs, indicating a larger
S value. The sub-threshold slopes at different temperatures have been summarized in
Fig. 2.3.7. The S varies from 248 mV/dec at RT to 664 mV/dec at 350°C for D-mode
HEMT, while it increases from 464 to 757 mV/dec for E-mode device. As we
discussed before, the electron mobility decreases with temperature increased. When
gate bias is close to device threshold voltage, the electrons begin to accumulate under
the gate and form 2DEG. But the accumulation rate will be affected due to the
mobility degradation at high temperatures, leading to a larger sub-threshold slope.
-10 -8 -6 -4 -2 0 2 410-1
100
101
102
103
D-mode RT D-mode 350oC
I D (m
A/m
m)
VGS (V)
E-mode RT E-mode 350oC
Fig. 2.3.6 Sub-threshold slope characteristic comparison between RT and 350°C
(2.1)
43
0 100 200 300 400
200
400
600
800
S (m
V/d
ec)
Temperature (oC)
E-mode S D-mode S
Fig. 2.3.7 Sub-threshold slope characteristics from RT to 350°C.
Fig. 2.3.8 Schematics of gate controlling capability in sub-threshold region for (a) D-mode and (b) E-mode HEMTs.
Figure 2.3.7 also shows us that the sub-threshold slope in E-mode HEMT is
larger than D-mode HEMT within the temperature range of 25°C ~ 350°C. But the
difference between E-mode and D-mode HEMT keeps decreasing as temperature
increases. The sub-threshold slope reveals the gate controlling capability to the
channel, which can be illustrated in Fig. 2.3.8. For D-mode HEMT, when gate bias is
close to threshold voltage, the electrons accumulate in the channel. At that time, the
static electric field starts from gate metal, goes through the AlGaN layer, and ends at
44
2DEG in the channel, as shown in Fig. 2.3.8 (a). For E-mode HEMT, a large number
of fluorine ions are located in the AlGaN layer, as we mentioned before. The electric
field will be stopped at these negative ions in AlGaN layer, so that part of electric
field will be shielded in E-mode HEMT [Fig. 2.3.8 (b)]. Therefore, compared to D-
mode HEMTs, the gate controlling capability will be depressed by fluorine ions in E-
mode devices, resulting in a larger sub-threshold slope. At high temperatures, part of
fluorine ions will lose electrons due to higher electron thermal energy, and threshold
voltage becomes more negative. So the fluorine ion shielding effects can be released
to some extent in E-mode HEMTs, and the behavior of E-mode HEMTs will be
closer to D-mode devices. Then the difference in S between E-mode and D-mode
HEMTs is decreased at high temperatures, as given in Fig. 2.3.7.
2.3.2 Thermal stability
Fig. 2.3.9 E/D-mode HEMTs DC characteristic comparison before and after high-temperature measurements.
-10 -8 -6 -4 -2 0 2 410-1
100
101
102
103
104
(a)VDS = 10 V
I D (m
A/m
m)
VGS (V)
, E/D-HEMT ID before HT, E/D-HEMT ID after HT
-10 -8 -6 -4 -2 0 2 40
20406080
100120140160180
(b)
, E/D-HEMT Gm before HT, E/D-HEMT Gm after HT
VDS = 10 V
Gm
(mS/
mm
)
VGS (V)
45
When high-temperature measurements are finished, we re-measure the E/D-mode
HEMTs I-V characteristics. As shown in Fig. 2.3.9, the device performance shows
little difference before and after high-temperature measurements.
0 20 40 60 80 100 120 140 16010-1
100
101
102
103
50
100
150
200
250
, D/E-HEMT ILeak
I D (m
A/m
m)
Time (hours)
, D/E-HEMT Imax
, D/E-HEMT Peak gm
Max
imum
gm (m
S/m
m)
Fig. 2.3.10 The variations of the peak drain current density (Imax), off-state drain current (Ileak) and maximum transconductance (gm) during thermal stress up to 153
hours at 350ºC for E/D-mode HEMTs fabricated by the planar process.
The device thermal stress measurements are also carried out to evaluate the
thermal stability of the planar process further. The sample is thermally stressed at
350ºC for hours. DC and RF measurements are performed at various stress time.
Figure 2.3.10 shows the variations of the maximum current density Imax, off-state
leakage current Ileak, and the peak transconductance gm with different stress time up
to 153 hours. It can be seen that, for both E-mode and D-mode HEMTs by planar
process, no obvious performance degradations occur during the 153-hour thermal
stress testing. That indicates that the thermal stability for the planar process is pretty
good at 350°C at least.
46
-5 -4 -3 -2 -1 0 1 2 3
0
10
20
30
40
50
60
Ft &
Fm
ax (G
Hz)
VGS (V)
, D-HEMT Ft & Fmax Before HT, D-HMET Ft & Fmax After HT, E-HEMT Ft & Fmax Before HT, E-HEMT Ft & Fmax After HT
Fig. 2.3.11 Small signal RF characteristics comparison before and after thermal stress for both E-mode and D-mode HEMTs by the planar process.
On wafer small signal RF characterizations are also performed before and after
153-hour thermal stress from 0.1 to 39.1 GHz on E/D-mode HEMTs fabricated by
planar process. The RF measurement details can be found in Appendix B. As shown
in Fig. 2.3.11, the E/D-mode HEMT RF characteristics remain the same after a long
time thermal stress. The maximum current gain cutoff frequency (fT) and maximum
power gain cutoff frequency (fmax) are about 11.5 and 35.3 GHz respectively for D-
mode HEMT; the maximum fT and fmax are 8.3 and 28.9 GHz for E-mode ones.
2.4 Planar-Integrated DCFL Digital Circuits
2.4.1 DCFL Inverters
The circuit schematic of an E/D-mode DCFL inverter is given in Fig. 2.4.1,
where the D-mode HEMT is used as an active load and the E-mode HEMT is used as
a driver to drive this active load.
47
Fig. 2.4.1 Schematic design of E/D-mode AlGaN/GaN DCFL inverter.
Fig. 2.4.2 Static voltage transfer curves of an E/D-mode HEMT DCFL inverter at (a) room temperature (RT) and (b) 350ºC.
Figure 2.4.2 shows the inverter static voltage transfer characteristics (the solid
square curves) and the inverter current consumption (the solid circle curves) at RT
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.50.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
10-3
10-2
10-1
100
101
Vou
t (V
)
Vin (V)
(a)
I DD (m
A)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.50.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
10-2
10-1
100
101
(b)
Vou
t (V
)
Vin (V)
I DD (m
A)
48
and 350ºC, with the supply voltage of 3.3 V. The hollow square curves are the same
transfer characteristics with the axis interchanged and represent the input-output
states of the next inverter stage, as the inverter will be used in an inverter chain to
form a ring oscillator. The high and low output logic levels (VOH and VOL) are given
by the two intersections of the curves in stable equilibrium points, and the difference
between the two levels is defined as the output logic voltage swing. The inverter
threshold voltage (VTH) is defined as the input voltage, where the input is equal to the
output. The static noise margins are measured using the method of the largest width
[82] for both logic-low noise margin (NML) and logic-high noise margin (NMH). At
RT, the DCFL inverter exhibits VOH and VOL of 3.30 and 0.52 V respectively,
yielding an output swing of 2.78 V. The inverter NML and NMH are 0.80 and 1.04 V,
as seen from Fig. 2.4.2 (a). When input voltage is below 0.5 V, the E-mode driver
can be turned off completely with the leakage current of ~3 μA, indicating the good
isolation achieved by plasma treatment. The inverter leakage current (ILEAK) is
consistent with the device measurement results, as shown in Fig.2.3.2 (a). Figure
2.4.2 (b) reveals that the inverter still can function properly at 350ºC, with NML and
NMH of 0.39 and 1.03 V respectively.
The inverter voltage transfer curves and current consumption at different
temperatures are plotted in Fig. 2.4.3, at a supply voltage of 3.3 V. Table 2-1 lists the
measured values of static noise margins (NML and NMH), as well as VOH, VOL, output
voltage swing, VTH, and ILEAK. Figure 2.4.3 (a) shows that the voltage transfer curves
keep shifting to the negative direction as the temperature increases, leading to a
49
smaller VTH. As shown in Section 2.3.1, when the temperature rises, the E-mode
HEMT’s threshold voltage becomes more negative, while the D-mode one changes
little. So the D-mode HEMT current will drop faster than the E-mode device, leading
to the E/D-mode device current ratio increased at high temperatures. Compared to
the D-mode HEMTs, the E-mode devices become stronger and stronger at high
temperatures. Therefore, the inverter static voltage transfer curve will shift to the
negative direction. At high temperatures, the rise of output voltage in transfer curves
is due to the gate Schottky diodes’ turn-on at the large input voltage (> 2.5 V).
Figure 2.4.3 (b) shows that the inverter off-state leakage current increases when the
temperature is increased, as seen from the device measurement results. When the
sample is cooled down to RT, the inverter exhibits almost the same performance with
the one before high-temperature test. The trend is consistent with the results that are
observed in the discrete E/D-mode devices, as shown in Fig. 2.3.9.
Fig. 2.4.3 Temperature dependence of (a) the voltage transfer curves and (b) current consumption for the E/D-mode DCFL inverter by the planar process.
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.510-3
10-2
10-1
100
101
(b)
RT 100oC 150oC 200oC 250oC 300oC 350oC
I DD (m
A)
Vin (V)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.50.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5(a)
Vou
t (V
)
Vin (V)
RT 100oC 150oC 200oC 250oC 300oC 350oC
50
Table 2-1 DCFL inverter characteristics with different environment temperatures at the supply voltage of 3.3 V.
Temperature
(ºC) VOH
(V) VOL
(V) Swing
(V) VTH (V)
NML (V)
NMH (V)
ILEAK
(μA)
RT 3.30 0.52 2.78 1.82 0.80 1.04 2.97
100 3.28 0.63 2.65 1.58 0.80 1.32 3.98
150 3.25 0.65 2.60 1.53 0.76 1.36 4.86
200 3.20 0.60 2.60 1.45 0.69 1.33 6.34
250 3.08 0.54 2.54 1.28 0.56 1.26 9.06
300 2.87 0.54 2.33 1.18 0.45 1.10 17.22
350 2.68 0.53 2.15 1.13 0.39 1.03 28.66
2.4.2 DCFL Ring Oscillators
(a)
(b)
Fig. 2.4.4 (a) schematic design and (b) SEM photograph of a 17-stage E/D-mode AlGaN/GaN DCFL ring oscillator by the planar process.
51
Based on the E/D-mode AlGaN/GaN HEMT DCFL inverters, ring oscillators are
formed with 17-stage inverter chain and an output buffer stage, with the schematic
design shown in Fig. 2.4.4 (a). The micrograph photo of a fabricated ring oscillator
that includes 36 transistors is given in Fig. 2.4.4 (b). The ring oscillators are
characterized on-wafer using an Agilent E4404B spectrum analyzer for frequency-
domain measurement and a HP 54522A oscilloscope for time-domain measurement.
The DC power consumption is also recorded during the ring oscillator’s operation at
the different supply voltages, as shown in Fig. 2.4.5.
Fig. 2.4.5 Configuration of ring oscillator measurement system, including a DC source, a current meter, a spectrum analyzer and an oscilloscope.
Figure 2.4.6 shows that the frequency-domain characteristics of the ring
oscillator at RT and 350ºC, with a supply voltage of 3.5 V. From Fig. 2.4.6 (a), it can
be seen that the fundamental oscillation frequency is 146 MHz at RT. According to
the formula of propagation delay per stage ( ) 12 −= nfpdτ , where the number of stages
52
n is 17 in this work, the pdτ can be calculated to be 0.20 ns/stage at RT. When the
sample is heated to 350ºC, the ring oscillator still exhibits an output frequency of 67
MHz [Fig. 2.4.6 (b)], corresponding to a propagation delay of 0.44 ns/stage. In this
work, the E/D-mode HEMT gate lengths are 1.5 and 4 μm, resulting in a large
loading capacitance in the inverter chain. When this planar integration technology is
implemented in the sub-micrometer regime, the gate delay time is expected to be
further reduced. This demonstration illustrates promising potential of GaN-based
digital ICs for high-temperature electronics.
Fig. 2.4.6 The 17-stage E/D-mode AlGaN/GaN HEMT DCFL ring oscillator frequency spectrum at (a) room temperature (RT) and (b) 350ºC.
Figure 2.4.7 summarizes the dependences of the ring oscillator output frequency
and current consumption on working temperature at different supply voltage VDD. At
all bias conditions, both the oscillation frequency and the current consumption show
similar decreasing trend as the temperature rises. It was well known that the circuit
speed mainly relies on the drive current. When the temperature is increased, the E/D-
(a) (b)
53
mode HEMT current will drop together, leading to the degradation of the ring
oscillator frequency. Therefore, the ring oscillator frequency and current
consumption exhibit similar dependence on temperature.
Fig. 2.4.7 The dependences of the ring oscillator (a) output frequency and (b) current consumption on different environment temperatures.
0 100 200 300 4000.0
0.4
0.8
1.2
1.6
2.0
2.4
Pow
er*d
elay
/stag
e (p
J)
Temperature (oC)
1.5V; 2.0V; 2.5V 3.0V; 3.5V; 4.0V 4.5V
Fig. 2.4.8 The dependences of the ring oscillator power-delay product per stage on environment temperatures.
The relationship between the drive current and circuit speed is also confirmed by
ring oscillator power-delay product characteristics, as shown in Fig. 2.4.8. When the
0 100 200 300 400
40
80
120
160
200(a)VDD =
Freq
uenc
y (M
Hz)
Temperature (oC)
1.5V 2.0V 2.5V 3.0V 3.5V 4.0V 4.5V
0 100 200 300 4000
10
20
30
40
50(b)VDD =
I DD (m
A)
Temperature (oC)
1.5 V 2.0 V 2.5 V 3.0 V 3.5 V 4.0 V 4.5 V
54
temperature rises, the delay time of each inverter stage will be increased, while the
current consumption will be decreased at the same time. So the power-delay product
can be kept at a relatively stable value at different temperatures because these two
effects can compensate each other. In this work, the minimum power-delay product
is found to be ~ 0.22 pJ/stage at the supply voltage of 1.5 V from RT to 350ºC, as
shown in Fig. 2.4.8.
2.5 Summary
A new planar process for integrating AlGaN/GaN E/D-mode HEMTs is
developed based on fluoride-based plasma treatment. Without any dry etching for
mesa formation and gate recess, the plasma treatment can achieve the same isolation
results between active devices. Also, the plasma treatment can be used to convert D-
mode HEMTs to E-mode devices. An E/D-mode DCFL inverter and a 17-stage ring
oscillator have been demonstrated using this new technique, in which the whole
process is conducted on a pure planar surface.
The temperature-dependences and thermal stability of the planar-integrated E/D-
mode AlGaN/GaN HEMTs and digital circuits are also investigated in this work. The
E/D-mode HEMTs exhibit stable operation from RT to 350ºC. After a 153-hour
thermal stress testing at 350ºC, the devices maintain the same DC and RF
characteristics, suggesting excellent thermal reliability of the planar process. The
E/D-mode DCFL inverter and 17-stage ring osicllator, which are fabircated using
this planar-integration technique, show proper functions within the temperature range
55
from RT to 350ºC, providing a promsing potential for GaN-based high-temperature
digital ICs. This planar integration technology, free of three dimensional mesas, is
expected to be benefical to the development of GaN-based high-temperature large
scale integration (LSI).
56
CHAPTER 3
Integration of Enhancement and Depletion-mode AlGaN/GaN MIS-HFETs by
Fluoride-based Plasma Treatment
3.1 Motivation of Fabrication of E-mode AlGaN/GaN MIS-HFETs
As we discussed in Chapter 1, wide bandgap AlGaN/GaN heterostructure field
effect transistors (HFETs) are attracting interests for applications in RF power
amplifiers and high-temperature digital ICs, due to the excellent capacity of handling
high power and operating at high temperatures. However, three key problems still
remain. At first, the gate leakage current for AlGaN/GaN HFETs is typically 10-100
μA/mm at room temperature (RT), and it rapidly increases by about an order of
magnitude at 300ºC and by about three orders of magnitude at 750ºC [63]. This
temperature-induced gate leakage deteriorates the device’s RF performance and
increases the low and high frequency noise levels. It also accelerates thermal stress
related device degradation, and limits high-temperature applications of AlGaN/GaN
HFETs. Secondly, AlGaN/GaN HFETs are known to exhibit current collapse when a
high RF input drive is applied on the gate [41], [83]-[84]. This phenomenon
significantly reduces RF powers below the values expected from DC transfer curves.
Thirdly, the gate turn-on voltage is relatively low for AlGaN/GaN HEMTs, i.e. 1 V
for depletion-mode (D-mode) HFETs and 3 V for enhancement-mode (E-mode)
HEMTs. The low turn-on voltage increases the risk of circuit operation, such as
power switches. When devices work under high RF input signal, it will cause a large
57
forward gate leakage current, leading to the degradation of device performance and
reliability issue.
To solve these problems, several groups began to attempt metal-insulator-
semiconductor structure [85]-[88]. Up to now, many dielectric layers, such as SiO2
[85], [89], SiNx [86]-[88], Al2O3 [90], MgO [91] and Sc2O3 [92] have been used for
the formation of insulating gate. The MIS-HFETs structure is proven to be able to
reduce gate leakage current dramatically, and preferred for high-temperature
operations because the additional insulator under the gate provides higher potential
barrier between the gate electrode and the channel, which should suppress the
thermionic emission at high temperatures and keep the gate voltage swing reasonably
large for proper circuit operation. In addition, the dielectric insulator layer in the
gate-to-drain access region is found to be able to reduce the current collapse
effectively because of passivation effects.
Compared to D-mode AlGaN/GaN HFETs, E-mode devices may have many
advantages. For the applications such as high frequency PAs and low noise
amplifiers (LNAs), E-mode HFETs can simplify the circuit configuration by
eliminating the negative power supply. However, when threshold voltage (Vth) is
positive and gate turn-on voltage is limited by the Schottky barrier height, the gate
bias swing of E-mode AlGaN/GaN HFETs is restricted rigidly. With a smaller
maximum forward gate bias, the E-mode devices only can supply limited drain
current and then lower power density, resulting in degraded circuit performance.
Therefore, the MIS structure is more preferred in E-mode operations to enhance the
58
forward gate bias limitation. But all the works about MIS-HFET structure, which we
mentioned above, are focused on D-mode AlGaN/GaN HFETs. Up to now, the E-
mode MIS-HFETs are still lacking. In this chapter, we report the first E-mode
Si3N4/AlGaN/GaN MIS-HFETs with a two-step Si3N4 process which features a thin
layer of Si3N4 under the gate and a thick layer of Si3N4 in the access region. The
fluoride-based plasma treatment technique is adopted to convert the device from D-
mode to E-mode. At last, the E/D-mode AlGaN/GaN MIS-HFETs are integrated to
realize a direct-coupled FET logic (DCFL) inverter and a 17-stage ring oscillator.
3.2 Device Structure and Fabrications
-10 -8 -6 -4 -2 0-0.1
0.0
0.1
0.2
0.3
0.4
0.5f = 10 kHz
Capa
cita
nce
(μF/
cm2 )
Bias (V)
Fig. 3.2.1 Capacitance-voltage curves of the substrate used for the E/D-mode MIS-HFET fabrication.
The AlGaN/GaN HFET structure used in this letter is grown on (0001) sapphire
substrates in an Aixtron AIX 2000 HT metal-organic chemical vapor deposition
59
(MOCVD) system. The HFET structure consists of a ~50 nm-thick low temperature
GaN nucleation layer, a 2.5 μm-thick unintentionally doped GaN buffer layer, and an
AlGaN barrier layer with nominal 30% Al composition. The barrier layer is
composed of a 3 nm un-doped spacer, a 16nm carrier supplier layer doped with Si at
2x1018 cm-3, and a 2 nm un-doped cap layer. The Lehighton contactless measurement
exhibits a sheet resistance of ~387 Ω/sq. for this sample. The capacitance-voltage
(CV) measurement by mercury probe yields an initial threshold voltage of -4 V, as
shown in Fig. 3.2.1. The CV measurement can be referred to Appendix B.
Fig. 3.2.2 Schematics showing the process flow of E/D-mode AlGaN/GaN MIS-HFETs integration: (a) active region definition and ohmic contacts; (b) the 1st Si3N4
layer (thick) deposition and E-mode gate definition; (c) D-mode device window opened; (d) the 2nd Si3N4 layer (thin) deposition; (e) interconnects and pads openings;
(f) metallization for gate contacts and interconnects.
60
The process flow is illustrated in Fig. 3.2.2. At first, device mesa is formed using
Cl2/He plasma dry etching in a STS ICP-RIE (inductively coupled plasma reactive
ion etching) system followed by the source/drain ohmic contact formation with
Ti/Al/Ni/Au (20 nm/150 nm/50 nm/80 nm) annealed at 850ºC for 30 seconds, as
shown in Fig. 3.2.2 (a). Then the first Si3N4 layer (~125 nm) is deposited on the
sample by plasma-enhanced chemical vapor deposition (PECVD). After gate
windows with 1-μm length are opened by photolithography, the sample is treated by
CF4 plasma at 150 W for 190 seconds, which accomplishes two goals: removal of the
Si3N4 in gate region and incorporation of fluorine ions for E-mode operation [44],
[52]. Figure 3.2.2 (c) shows that D-mode device windows are opened by removing
the thick Si3N4 with CF4 plasma, while the treatment time is controlled such that the
minimum amount of fluorine ions are incorporated in the D-mode devices.
Subsequently, the second Si3N4 layer (~15 nm) is deposited by PECVD to form the
insulating layer between E/D-mode HFETs’ gate metal and the AlGaN barrier [Fig.
3.2.2 (d)]. After the Si3N4 layer is removed from the source and drain ohmic contact
regions, as shown in Fig. 3.2.2 (e), the E/D-mode devices gate electrodes and
interconnects are formed simultaneously [Fig. 3.2.2 (f)]. For E-mode MIS-HFETs,
the gate electrodes’ top length is 2 μm to assure that the gate electrode covers the
entire treated gate region, leading to a T-gate configuration. The gate metal over-
hang in the access regions is insulated from the AlGaN barrier by the thick Si3N4
layer, keeping the gate capacitances at a low level. At last, the sample is annealed at
450ºC for 10 min to repair the plasma-induced damages in the AlGaN barrier and
61
channel [44], [52], as seen from Appendix C. For the DCFL inverter shown in this
paper, the E-mode driver is designed with gate length and gate width of 1 and 50 μm
respectively; the D-mode load is designed with gate dimension of 1.5 x 7.5 μm2,
yielding a ratio of β=(WGE/LGE)/(WGD/LGD) of 10. The ring oscillator consists of 17
inverters connected into a ring and an output buffer stage, as illustrated in Fig. 2.4.4
(a) in Chapter 2. The discrete E/D-mode MIS-HFETs are fabricated with gate width
of 10 μm for DC measurement and 100 μm for RF characterizations.
3.3 Device and Circuit Characterization
3.3.1 E-mode AlGaN/GaN MIS-HFET Characteristics
The DC output characteristics of the E-mode MIS-HFETs are plotted in Fig.
3.3.1 (a). The devices exhibit a peak current density of ~420 mA/mm and an on-
resistance of ~5.15 Ω·mm (extracted around VDS = 0 V) at VGS = 7 V. It can be seen
that the gate forward bias limit of AlGaN/GaN HFET has been improved from 3 V
(conventional E-mode) to 7 V using metal-insulator-semiconductor structure. This
improvement can be attributed to two parts: AlGaN/GaN conduction band upward
bending induced by CF4 plasma treatment [Fig. 1.3.2], and the insulation layer
between the gate electrode and III-nitride semiconductor. Both of them provide a
higher potential barrier between the gate electrode and the 2DEG channel, which can
enhance the gate bias limit. In the output curve [Fig. 3.3.1 (a)], no current drop is
found at high gate bias as in the case of D-mode HEMT in chapter 2, due to smaller
62
gate dimension (1 x 10 μm2) used for measurement in this work, which will lead to
much lower current level and negligible self heating effects. Figure 3.3.1 (b) shows
that the threshold voltage Vth of E-mode MIS-HFETs is about 2 V, indicating a 6-V
shift of Vth (compared to CV measurements) achieved by the insertion of the Si3N4
insulator and the plasma treatment. The peak transcondcutance gm is ~125 mS/mm.
Figure 3.3.2 shows the gate leakage current at both the negative bias and forward
bias. The forward gate turn-on voltage is ~6.8 V, providing a much larger gate bias
swing than the conventional E-mode HFETs [52].
Fig. 3.3.1 E-mode AlGaN/GaN MIS-HFET (a) DC output and (b) transfer curves.
0 2 4 6 8 100
100
200
300
400
500(a)
I D (m
A/m
m)
VDS (V)
VGS = 0V ~ 7V; Step = 1V
-6 -4 -2 0 2 4 6 8
0
100
200
300
400
500
0
20
40
60
80
100
120
140
VGS (V)
(b)
I D (m
A/m
m)
VDS = 10 V
Gm
(m
S/m
m)
63
Fig. 3.3.2 E-mode AlGaN/GaN MIS-HFET gate leakage current performance.
Fig. 3.3.3 Pulse measurements of E-mode AlGaN/GaN MIS-HFET.
Pulse measurements, which can be referred to Appendix B, are taken on the E-
mode MIS-HFETs with 1 x 100 μm2 gate dimensions at a pulse length of 0.2 μS and
a pulse separation of 1 ms. The quiescent bias point is chosen at GSV = 0 V (below
Vth) and DSV = 20 V. Figure 3.3.3 shows that the pulsed peak current is higher than
the static one, indicating no current collapse occurred. The static maximum current
density of the large device with a 100-μm gate width is ~330 mA/mm, smaller than
the device with 10-μm gate width (~420 mA/mm). The lower peak current density in
0 2 4 6 8 10
0
100
200
300
400
500
600 Static; VGS = 0V ~ 7V, step = 1V
I D (m
A/m
m)
VDS (V)
Pulse; Bias at VGS = 0V, VDS = 20V
-6 -4 -2 0 2 4 6 810-8
10-6
10-4
10-2
100
102
I G (m
A/m
m)
VGS (V)
-6 -3 0 3 601234
I G (m
A/m
m)
VGS (V)
64
the larger device is due to the self heating effect that lowers the current density.
Since little self heating occurs during pulse measurements, the maximum current for
the 100 μm-wide device can reach the same level as the 10 μm-wide device.
On wafer small signal RF characterizations are performed from 0.1 to 39.1 GHz
on the 100 μm-wide E-mode MIS-HFETs at VDS = 10 V. As shown in Fig. 3.3.4, the
maximum current gain cutoff frequency (fT) and power gain cutoff frequency (fmax)
are 13.3 and 23.3 GHz respectively. When the gate bias is 7 V, the small signal RF
performance does not degrade too much, with a fT of 13.1 GHz and a fmax of 20.7
GHz, indicating that the Si3N4 insulator offers an excellent insulation between gate
metal and semiconductor.
Fig. 3.3.4 Small signal RF measurements of E-mode AlGaN/GaN MIS-HFETs
Large signal power measurements are also conducted on 1 x 100 μm2 devices at 2
GHz via a Maury load-pull system. The results are plotted in Fig. 3.3.5. By tuning
the input and output impedance for the maximum output power, a linear gain of 15
2 3 4 5 6 70
5
10
15
20
25
30
Ft &
Fm
ax (G
Hz)
VGS (V)
Ft FmaxVDS = 10V
65
dB together with a maximum power density of 1.2 W/mm and a PAE of 30% is
obtained with a 20-V drain supply voltage and a 3.5-V gate bias, as shown in Fig.
3.3.5 (a). When the bias condition changes to 25 V on the drain side and 3.5 V on the
gate, a linear gain of 15 dB together with a maximum power density of 1.4 W/mm
and a PAE of 24% can be achieved [Fig. 3.3.5 (b)]. The substrate is not thinned
down and no cooling treatment is employed during the measurements. The large
signal measurement details can be found in Appendix B.
-15 -10 -5 0 5 10 15 20-5
0
5
10
15
20
25
0
5
10
15
20
25
30
Pout
(dB
m),
Gai
n (d
B)
Pin (dBm)
Pout (dBm) Gain (dB)
(a)
1.20 W/mm PAE
VGS = 3.5 VVDS = 20 V
PA
E (%
)
-15 -10 -5 0 5 10 15 20-5
0
5
10
15
20
25
0
5
10
15
20
25
Pout
(dB
m),
Gai
n (d
B)
Pin (dBm)
Pout (dBm) Gain (dB)
(b)
1.40 W/mm PAE
VGS = 3.5 VVDS = 25 V
PA
E (%
)
Fig. 3.3.5 Power sweep measurements by a load-pull system at 2 GHz on E-mode AlGaN/GaN MIS-HFETs.
66
0 2 4 6 8 100
20
40
60
80
I D (m
A/m
m)
VDS (V)
VGS = 7 ~ 2 V; Step = -1 V
In certain applications such as power switches, there is a need to further increase
the threshold voltage. Figure 3.3.6 shows the output characteristics of an E-mode
MIS-HFET with longer fluoride plasma treatment time (230 s), which exhibits a
threshold voltage of 4.3 V and a maximum drain current density of 68 mA/mm.
Fig. 3.3.6 DC output characteristics of an E-mode MIS-HFET with longer fluoride plasma treatment time.
3.3.2 DCFL Integrated Circuit Applications
For D-mode AlGaN/GaN MIS-HFETs, the DC characteristics are given in Fig.
3.3.7. The devices exhibit a peak current density of ~1440 mA/mm at VGS = 7 V and
a maximum transconductance gm of 140 mS/mm. By integrating E/D-mode MIS-
HFETs, a DCFL inverter has been fabricated, as shown in the inset of Fig. 3.3.8. The
measured static voltage transfer curve of the inverter (the solid square) is plotted in
Fig. 3.3.8, with the supply voltage of 7 V. The hollow square curve is the same
voltage transfer characteristics with the axis interchanged and represent the input-
output states of the next inverter stage. The inverter high and low output logic levels
67
(VOH and VOL) are given by the two intersections of the curves in stable equilibrium
points, the difference between the two levels is defined as the output logic voltage
swing. The static noise margins are measured using the method of the largest width
[82] for both logic low noise margin (NML) and logic high noise margin (NMH). It
can be seen that the inverter VOH and VOL are 7 and 0.8 V, respectively; the NML and
NMH are 2.74 and 2.46 V, respectively. The inverter DC current is also shown as the
solid circle curve in Fig. 3.3.8. It can be seen that the E-mode driver has been turned
off completely when input voltage is lower than 2 V.
Fig. 3.3.7 D-mode AlGaN/GaN MIS-HFET (a) DC output and (b) transfer curves.
0 2 4 6 8 10 12 140
200400600800
1000120014001600 (a)VGS = -13V ~ 7V; Step = 2V
I D (m
A/m
m)
VDS (V)
-16 -12 -8 -4 0 4 80
400
800
1200
1600
0
40
80
120
160(b)
I D (m
A/m
m)
VGS (V)
VDS = 10V
Gm
(mS/
mm
)
68
Fig. 3.3.8 E/D-mode AlGaN/GaN MIS-HFET DCFL inverter voltage transfer and current consumption curve.
Based on the DCFL inverters, a 17-stage ring oscillator is fabricated with 17
inverters connected into a ring and an output stage. The ring oscillators are
characterized on-wafer using an Agilent E4404B spectrum analyzer for frequency-
domain measurement and a HP 54522A oscilloscope for time-domain measurement,
as shown in Fig. 2.4.5. The DC power consumption is also recorded during operation.
Figure 3.3.9 shows the frequency and time domain characteristics of the ring
oscillator at RT and 415°C, with a supply voltage VDD of 7 V. It can be seen that the
fundamental oscillation frequency is 181 MHz at RT, as shown in Fig. 3.3.9 (a) and
(b). According to the formula of propagation delay per stage ( ) 12 −= nfpdτ , where
the number of stage n is 17, the pdτ can be calculated to be 0.16 ns/stage at RT.
When the sample is heated to 415°C, the ring oscillator still exhibits an output
frequenc of 55 MHz [Fig. 3.3.9 (c) and (d)], corresponding to a propagation delay of
0.53 ns/stage. Figure 3.3.10 summarizes the dependences of the ring oscillator output
frequency and current consumption on working temperature with VDD of 7 V. It can
0 1 2 3 4 5 6 70
1
2
3
4
5
6
7
012345678
Vou
t (V
)
Vin (V)
Vout (V) ; VDD = 7V
IDD (mA)
I DD (m
A)
D-MISHFET
E-MISHFETVout
Vin
69
be seen that the oscillation frequency and the current consumption show similar
decreasing trend as the temperature rises. According to the curve-fitting results, both
of them are proportional to T -3/2 in Kelvin at high temperatures. The circuit speed
mainly relies on the drive current. We assume that the circuit current reduction at
high temperatures mainly results from the 2DEG mobility degradation. As the 2DEG
mobility will decrease by a T -3/2 dependence due to optical phonon dominated
scattering at high temperatures [79], the current consumption and output frequency
will also follow this trend when temperature increases.
Fig. 3.3.9 Ring oscillator frequency and time domain characteristics at RT [(a) and (b)] and 415°C [(c) and (d)].
Ref 0 dBm Atten 10 dBMkr1 181 MHz
-4.339 dBm PeakLog10dB/
W1 S2S3 FC
AA
Start 10 MHz#Res BW 100 kHz VBW 100 kHz
Stop 1 GHzSweep 247.5 ms (401 pts)
1
Marker181.000000 MHz-4.339 dBm
Ref 0 dBm Atten 10 dBMkr1 55 MHz-25.42 dBm
PeakLog10dB/
W1 S2S3 FC
AA
Start 10 MHz#Res BW 100 kHz VBW 100 kHz
Stop 1 GHzSweep 247.5 ms (401 pts)
1
Marker55.000000 MHz-25.42 dBm
(a) (c)
(b) (d)
70
Fig. 3.3.10 Temperature dependence of ring oscillator frequency and current consumption.
3.4 Conclusions
The fabrication technology for E/D-mode AlGaN/GaN MIS-HFET integration
has been developed in this work. The CF4 plasma treatment is used to converter D-
mode devices to E-mode, shifting the threshold voltage from -4 V to 2 V. A two-step
Si3N4 deposition process is used to insert a thin layer of Si3N4 as the gate insulating
layer and create a thick layer between gate electrode and the access region. The gate
bias of the E-mode MIS-HFETs can be applied up to 7 V. The E-mode MIS-HFETs
show no current collapse under pulse operation and good DC and RF performances
are obtained at the same time.
By integrating with D-mode AlGaN/GaN MIS-HFETs, the DCFL inverter and the
17-stage ring oscillator are demonstrated. The ring oscillator exhibits stable operation
from RT to 415°C, providing potential for GaN-based high-temperature mixed-signal
operations.
0 100 200 300 4000
50
100
150
200
20
40
60
80
100
T -3/2
Frequency
VDD = 7VFreq
uenc
y (M
Hz)
Temperature (oC)
Current
I DD (m
A)∝
71
CHAPTER 4
Gain Improvement of Enhancement-mode AlGaN/GaN HEMTs Using Dual-
Gate Architectures
4.1 Motivation for the Enhancement-mode AlGaN/GaN DG HEMTs
Progress in the materials growth and device process technologies for
AlGaN/GaN HEMTs has made them as promising candidates for high efficiency,
high power applications such as wireless base stations. The competitive advantages
of GaN HEMTs come from the material properties of the AlGaN/GaN material
system and the advantages afforded by various heterostructures in this material
system [13], [57]. Previously, depletion-mode (D-mode) dual-gate (DG) AlGaN/GaN
HEMTs, composed of two D-mode gates, were reported for use as broadband PAs
[93]-[97]. And dual-gate AlGaN/GaN HEMTs have been shown to exhibit higher
power gain compared to a single-gate (SG) device. In fact, the dual-gate device is
electrically equivalent to a common-source (CS)/common-gate (CG) cascode pair
[93], [95], but occupies less die area as shown in Fig. 4.1.1. By using this kind of
structure, the higher device power gain can be achieved due to smaller feedback
capacitance and higher output impedance.
As we discussed before, the enhancement-mode (E-mode) AlGaN/GaN HEMTs
have many advantages over D-mode HEMTs in circuit applications. In this paper, E-
mode DG AlGaN/GaN HEMTs, which consist of an E-mode gate and a D-mode gate,
are demonstrated by using CF4 plasma treatment technique [44], [52], [98], and
72
comparison of RF and DC characteristics is made between E-mode DG and SG
devices. At 2.1 GHz, a 9-dB gain improvement has been achieved using E/D-mode
DG structure with only one positive polarity voltage supply.
Fig. 4.1.1 Schematic structure of dual-gate AlGaN/GaN HEMTs.
4.2 E-mode Dual-Gate AlGaN/GaN HEMTs Fabrication
The AlGaN/GaN HFET structure used in this work is grown on (0001) sapphire
substrates in an Aixtron AIX 2000 HT metal-organic chemical vapor deposition
(MOCVD) system. The HFET structure consists of a ~50 nm-thick low temperature
GaN nucleation layer, a 2.5 μm-thick unintentionally doped GaN buffer layer, and an
AlGaN barrier layer with nominal 30% Al composition. The barrier layer is
composed of a 3 nm un-doped spacer, a 16nm carrier supplier layer doped with Si at
2x1018 cm-3, and a 2 nm un-doped cap layer. The Lehighton contactless measurement
exhibits a sheet resistance of ~387 Ω/sq. for this sample. The capacitance-voltage
(CV) measurement by mercury probe yields an initial threshold voltage of -4 V for
this AlGaN/GaN heterostructure.
73
Fig. 4.2.1 Schematics showing the process flow of E-mode DG HEMTs: (a) mesa and ohmic contacts; (b) D-mode gate electrodes; (c) E-mode gate definition and
plasma treatment; (d) E-mode gate metal deposition and lift-off.
The E-mode DG AlGaN/GaN HEMT process flow is similar with the MIS-
HFETs in chapter 2, as illustrated in Fig. 4.2.1. At first, the device mesa is formed
using Cl2/He plasma dry etching in a STS ICP-RIE (inductively coupled plasma
reactive ion etching) system. Then the source/drain ohmic contacts are formed by e-
beam deposition of Ti/Al/Ni/Au (20 nm/150 nm/50 nm/80 nm) and rapid thermal
annealing at 850ºC for 30 s, as shown in Fig. 4.2.1 (a). Secondly, the D-mode gate
electrodes and interconnections are defined by e-beam evaporation of Ni/Au (50 nm/
300 nm) and lift-off [Fig. 4.2.1 (b)]. Next, E-mode gate electrodes are patterned by
photolithography. Prior to deposition of Ni/Au, the gate regions are treated by CF4
plasma in a STS RIE system, as shown in Fig. 4.2.1 (c). The RF power is 150 W, and
the plasma bias is set to be 0 V. The CF4 gas flow is controlled to be 150 sccm, and
the treatment time is 150 s. This step performs the function of converting the treated
74
region from D-mode to E-mode operation [44], [52]. At last, the gate metal is
deposited and the whole sample is annealed at 400ºC for 10 min to repair the plasma-
induced damage in the AlGaN barrier and channel [Fig. 4.2.1 (d)]. The E-mode gate
electrode is separated by 1 μm from the source, and the D-mode gate is 1μm away
from the drain contact, with a 1.5-μm separation between two gates. All the gate
electrodes have the same dimensions of 1 x 100 μm2.
4.3 Device DC and RF Characteristic Comparison
The DC characteristics of the E-mode DG HEMTs are plotted in Fig. 4.3.1, with
the D-mode gate grounded as shown in the inset of Fig. 4.3.1 (b). It can be seen that
the DG devices exhibit a peak current density of ~314 mA/mm; the peak
transconductance (gm) is about 145 mS/mm. Defining threshold voltage (Vth) as the
gate bias intercept of the linear extrapolation of drain current at the point of peak gm,
the Vth of E-mode DG HEMT is determined to be 0.3 V, as shown in Fig. 4.3.1 (b).
As a comparison, the discrete E-mode and D-mode SG AlGaN/GaN HEMTs are also
fabricated on the same substrate with the same gate dimensions. The transfer
characteristics of SG devices are plotted in Fig. 4.3.2. The peak current density for
SG D-mode and E-mode HEMTs are about 520 and 328 mA/mm respectively; the
peak transconductances are 160 and 146 mS/mm. It can be concluded that E-mode
DG HEMTs have comparable DC characteristics with the E-mode SG devices. The
E-mode DG and SG HEMTs exhibit a smaller gm than the D-mode devices due to the
incomplete recovery of the plasma-induced damage [44], [52]. Compared to SG
75
HEMT, the DG structure pays a penalty of larger device size with the second gate
electrode (1 μm) and the spacing between two gates (1.5 μm). However, many RF
circuit applications require AlGaN/GaN HEMTs with high breakdown voltages that
need the device gate-to-drain spacing to be over 10 μm. In these devices, the size
penalty presented in the DG structure is less significant compared to the overall
device size.
Fig. 4.3.1 DC characteristics of E-mode DG HEMTs: (a) output curves and (b) transfer characteristics.
-4 -3 -2 -1 0 1 2 3
0
50
100
150
200
250
300
350
020406080100120140160180
(b)VDS = 10 V
I D (m
A/m
m)
VGS (V)
Vth = 0.3 V
Gm
(mS/
mm
)
0 1 2 3 4 5 6 7 8 9 100
50100150200250300350400
(a)
I D (m
A/m
m)
VDS (V)
VGS = -0.5V ~ 2.5V; Step = 0.5V
76
Fig. 4.3.2 Transfer curves of E-mode and D-mode SG HEMTs.
Fig. 4.3.3 Frequency dependence of short-circuit current gain (h21) and maximum stable/maximum available gain (MSG/MAG) for E-mode DG and SG devices.
On-wafer small signal RF characteristics of E-mode SG and DG AlGaN/GaN
HEMTs are measured from 0.1 to 39.1 GHz. The current gain (h21) and maximum
stable/maximum available gain (MSG/MAG) of both types of devices are derived
from the measured S-parameters as a function of frequency, as shown in Fig. 4.3.3.
At VDS = 10 V and VGS = 1 V, E-mode DG HEMTs reveal a similar current gain
-7 -6 -5 -4 -3 -2 -1 0 1 2 3
0
100
200
300
400
500
600
0
40
80
120
160
200
D-mode ID E-mode ID
VDS = 10 V
I D (m
A/m
m)
VGS (V)
D-mode Gm E-mode Gm
Gm
(mS/
mm
)
109 10100
5
10
15
20
25
30
35
9 dB
VGS = 1 VVDS = 10 V
E-mode SG MSG/MAG E-mode DG MSG/MAG
E-mode SG h21 E-mode DG h21
Gai
n (d
B)
Frequency (Hz)
77
cutoff frequency (fT) of 13.7 GHz with the SG devices. Comparing the MSG/MAG,
E-mode DG HEMTs exhibit about a 9-dB gain improvement at 2.1 GHz than the SG
devices, with an increase in the power gain cutoff frequency (fmax) from 30.9 and
31.9 GHz.
The MSG/MAG improvement of E-mode DG HEMTs can be attributed to the
higher output impedance and smaller feedback capacitance [93], [95], [99]. The
output impedance (RDS) and feedback capacitance (CGD) for both E-mode DG and
SG HEMTs are extracted from the S-parameters at 2.1 GHz from the equivalent
small-signal circuit of HEMT shown in Fig. 4.3.4 [100]. And the results are given in
Fig. 4.3.5. It can be seen that the RDS has been improved remarkably by using dual-
gate structure, as shown in Fig. 4.3.5 (a), and the CGD are depressed effectively at the
same time [Fig. 4.3.5 (b)].
+Vg
-
im = gmVgexp(-j )
gdCds
Rd
Ld
Cpd
Rs
Ls
Cpg
Rg
Cgs
Ri
Lg
G D
S
Cgd
im
ωτ
Fig. 4.3.4 Equivalent small-signal circuit model for AlGaN/GaN HEMTs
78
Fig. 4.3.5 Output impedance (RDS) and feedback capacitance (CGD) comparison between E-mode SG and DG HEMTs, which are extracted from S-parameters.
Fig. 4.3.6 Gain-frequency characteristic comparison between E-mode DG and SG HEMTs.
0 10 20 30 40
-10
-8
-6
-4
-2
0(a)
S 11 (d
B)
f (GHz)
SG DG
0 10 20 30 40-4
-3
-2
-1
0(b)
S 22
(dB
)
f (GHz)
SG DG
0 10 20 30 40
-50
-40
-30
-20
-10(c)
S 12 (d
B)
f (GHz)
SG DG
0 10 20 30 40-10
-8
-6
-4
-2
0(d)
S 21 (d
B)
f (GHz)
SG DG
0.0 0.5 1.0 1.5 2.0 2.54
6
8
10
12
14
16
18
20(b)
E-HEMT SG E-HEMT DG
C GD (f
F)
VGS
(V)
VDS = 10 VFrequency = 2.1 GHz
0.0 0.5 1.0 1.5 2.0 2.50.5
1.0
1.5
2.0
2.5
3.0
3.5(a)
E-mode SG E-mode DG
VDS = 10 VFrequency = 2.1 GHz
R DS (K
Ohm
)
VGS (V)
79
The S-parameters are also given in Fig. 4.3.6 under the bias conditions of VGS = 1
V and VDS = 10 V. It can be seen from Fig. 4.3.6 (a) that SG and DG AlGaN/GaN
HEMTs exhibit similar S11 performance because the input impedance mainly depend
on gate to channel capacitance in both structures, which have the same E-mode gate
dimensions (1 x 100 μm2). Due to the presence of the second D-mode gate, the DG
device substantially reduce the signal feedback (S12) by ~8 dB at 2.1 GHz [Fig. 4.3.6
(c)], and increase the output impedance (S22) by ~1 dB due to higher output
impedance [Fig. 4.3.6 (b)], leading to increased device power gain.
In this work, it is just for convenience to get small signal performance that the
bias of the D-mode gate is set to be 0 V by connecting D-mode gate with source
electrodes. In real applications, the second gate can be chosen at any appropriate bias
point to improve the whole circuit performance. In addition, the second D-mode gate
can be designed with different dimensions for various applications, e.g. a longer gate
length optimized to achieve a higher breakdown voltage [93], [95], [97], and
increased device reliability [96] by depressing the electric field at the D-mode gate
edge.
4.4 Conclusions
In this chapter, the E-mode dual-gate structure, composed of an E-mode and a D-
mode gate electrode, is demonstrated based on CF4 plasma treatment technique. The
E-mode DG AlGaN/GaN HEMTs exhibit similar DC characteristics with E-mode
SG devices. Small signal RF characteristics are also conducted for DG and SG
80
HEMTs. A 9-dB gain improvement has been achieved at 2.1 GHz by using DG
structure, compared to E-mode SG devices. This improvement can be attributed to
the higher output impedance and smaller feedback capacitance due to the presence of
the second D-mode gate in DG HEMTs.
Compared with other works about dual-gate AlGaN/GaN HEMTs, this work has
the advantage of a simple circuit configuration and only one single-polarity voltage
supply needed since the E-mode gate has been adopted in this work using fluoride-
based plasma treatment.
81
CHAPTER 5
CONCLUSION
5.1 Conclusion
In this thesis work, there are three main parts of the GaN-based HEMTs, namely
planar integration of enhancement/depletion-mode (E/D-mode) HEMTs,
Si3N4/AlGaN/GaN metal-insulator-semiconductor HFETs (MIS-HFETs), and the E-
mode dual-gate (DG) AlGaN/GaN HEMTs.
Differs from the most work in the field of GaN-based HEMTs, this thesis work is
mainly focused on the E/D-mode AlGaN/GaN HEMTs for the mixed-signal
applications. Based on CF4 plasma treatment technique, high performance E-mode
HEMTs are fabricated and integrated with D-mode HEMTs on the same chip. Novel
device structure and integration technology have been demonstrated to improve the
device or circuit performance for applications in power amplifiers and high-
temperature GaN-based digital ICs.
At first, a planar fabrication technology for integrating E/D-mode AlGaN/GaN
HEMTs has been developed. The technology relies heavily on CF4 plasma treatment,
which is used in two separate steps to achieve two objectives: 1) active device
isolation; and 2) threshold voltage control for the E-mode HEMT formation. Using
this planar process, the D-mode and E-mode AlGaN/GaN HEMTs are integrated on
the same chip, and a direct-coupled FET logic (DCFL) inverter and a 17-stage ring
82
oscillator are demonstrated. Compared to the device fabricated by standard mesa
etching technique, the HEMTs by planar process have comparable DC and RF
characteristics, without obvious difference in device isolation. The E/D-mode HEMT
high-temperature characteristics have been summarized and both of them exhibit
stable operation from RT to 350ºC. After a 153-hour thermal stress testing at 350ºC,
the devices maintain the same DC and RF characteristics, suggesting excellent
thermal reliability for the planar process. The E/D-mode DCFL inverter and ring
oscillator show proper functions within the temperature range from RT to 350ºC,
providing a promising potential for the GaN-based high-temperature digital ICs. The
planar integration technology, free of three dimensional mesas in conventional
AlGaN/GaN HEMTs, is expected to be beneficial to the development of GaN-based
high-temperature large scale integration (LSI).
Secondly, to improve the gate forward bias limit and depress gate leakage current
in E-mode AlGaN/GaN HFETs, the E-mode Si3N4/AlGaN/GaN MIS-HFETs are
demonstrated by combing the CF4 plasma treatment technique and a two-step Si3N4
deposition process. The threshold voltage has been shifted from -4 V (for D-mode
HFETs) to 2 V using this technique. A 15-nm Si3N4 layer is inserted under the metal
gate to provide additional isolation between the gate Schottky contact and AlGaN
surface, which can lead to reduced gate leakage current at high temperatures. The
two-step Si3N4 deposition process is developed to reduce the gate coupling
capacitance in the source and drain access region, while assuring the plasma treated
gate region is fully covered by the gate electrode. The forward gate bias of the E-
83
mode MIS-HFETs can be as large as 7 V, at which a maximum current density of
420 mA/mm is obtained. Compared to the conventional E-mode HFETs (gate bias
limit is ~3 V), the gate bias swing of MIS-HFETs has been improved effectively to
sustain larger input signal. The E-mode AlGaN/GaN MIS-HFETs show no current
collapse under pulse operation due to Si3N4 the passivation on the access regions. By
further increasing CF4 plasma treatment time, a higher threshold voltage of 4.3 V has
been realized for some circuit applications, such as power switches. At the same time,
D-mode MIS-HFETs are fabricated on the substrates, and the DCFL inverter and
ring oscillator are fabricated by integrating E/D-mode AlGaN/GaN MIS-HFETs.
With the supply voltage of 7 V, the ring oscillator shows a stable operation within
the temperature range from RT to 415ºC, indicating the excellent high-temperature
working capabilities.
At last, an E-mode dual-gate (DG) AlGaN/GaN HEMT, composed of an E-mode
and a D-mode gate electrode, is developed based on CF4 plasma treatment technique.
The E-mode DG AlGaN/GaN HEMTs exhibit similar DC characteristics with single-
gate (SG) devices. But in RF characteristics, a 9-dB gain improvement has been
achieved at 2.1 GHz by using DG structure, compared to E-mode SG devices. This
can be attributed to the higher output impedance and smaller feedback capacitance in
DG structure, due to the presence of the second D-mode gate. Compared with other
works on dual-gate AlGaN/GaN HEMTs, in which two D-mode gate electrodes are
used, this work has the advantage of a simple circuit configuration with only one
84
single-polarity voltage supply needed, because of the E-mode gate adopted in this
structure.
5.2 Suggestions for Future Work
Although I have worked on normally-off AlGaN/GaN HEMTs by CF4 plasma
treatment for 3 years, I found there are so many uncertainties and puzzles in this field,
and we need more detailed work to clarify them. In addition, two key problems still
need to be solved before GaN-based HEMTs can be widely used in commercial
power amplifier and RF circuit market. They are the device reliability and the cost
issue. So we should pay more attention to these areas. Some suggestions about the
future works on normally-off GaN-based HEMTs are listed as following,
(1) To pay more attention to AlGaN/GaN heterostructure on Si substrates
instead of SiC or sapphire, due to the lower cost of Si than SiC and better
thermal conductivity than sapphire substrates.
(2) To conduct more reliability measurements on both enhancement-mode
and depletion-mode AlGaN/GaN HEMTs, including thermal stress, DC
and RF stress; to apply more advanced device structure to improve the
device reliability and bridge the gap between lab research and industry
applications.
(3) To investigate the detailed mechanism of CF4 plasma treatment in
forming positive threshold voltage, such as the physical locations of the
85
fluorine ions in the lattice, the energy level introduced by fluorine ions,
the diffusion characteristics under strong electric field or at high
temperatures, and the passivation effects on fluorine ions.
(4) To conduct more high-temperature characterizations on both depletion-
mode and enhancement-mode AlGaN/GaN HEMTs, including high-
temperature DC and RF characteristics; to demonstrate high-temperature
digital circuits for power control or sensing system.
(5) To improve the breakdown voltage and threshold voltage of the
enhancement-mode AlGaN/GaN HEMTs, and reduce the device on-
resistance at the same time; to apply the enhancement-mode HEMTs to
high power applications, such as power switches.
(6) To extract the parasitic parameters for both depletion-mode and
enhancement-mode AlGaN/GaN HEMTs, and try to obtain a full device
model eventually.
86
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102
APPENDIX A
Planar Process Flow for E/D-Mode AlGaN/GaN HEMT Integration
1 Source/Drain Electrodes Definition
Solvent Cleaning
(1) Acetone ultrasonic clean, 5 minutes. (2) IPA ultrasonic clean, 5 minutes. (3) DI water rinse, 4 cycles. (4) Blow dry with N2 gun. (5) Dehydration bake, 120C, 10 minutes in oven.
Photoresist Coating
(1) Cool down after dehydration, 5 minutes. (2) Exposure to HMDS vapor, 15 minutes. (3) Put wafer on spinner chuck with vacuum on, blow with N2. (4) Coat AZ 5206 photoresist. (5) Spin at 2000 rpm for 30 seconds. (6) Soft bake, 100C, 1 minute, on hotplate.
Photoresist Exposure and Development
(1) First exposure for 2.5 seconds, Karl Suss MA6 Aligner, low-vacuum contact mode.
(2) Post-exposure bake, 115C, 2 minutes, on hotplate. (3) Second exposure for 12 seconds, MA6 aligner, flood exposure mode. (4) Develop in FHD-5 for 40 seconds. (5) DI water rinse, 4 cycles. (6) Check under microscopy.
Oxygen Plasma Descum of Photoresist
(1) Chamber O2 pressure: 300 mTorr. (2) Temperature: 70 C. (3) Run for 0.7 minute.
Surface Preparation
(1) Mix a dilute solution of HCL:H2O = 1:5. (2) Dip in dilute HCl for 15 seconds. (3) DI water rinse, 4 cycles. (4) Blow dry with N2 gun.
103
Evaporation
(1) Mount wafer into e-beam chamber. (2) Pump down to below 10-6 Torr. (3) Deposit multiple metal layers:
Material Thickness Deposition Rate
Ti 200 Å 2.0 Å/sec
Al 1500 Å 4.0 Å/sec
Ni 500 Å 2.0 Å/sec
Au 800 Å 4.0 Å/sec
Liftoff
(1) Soak wafer in Acetone until metal becomes loose and falls off. (2) Rinse with IPA. (3) DI water rinse, 4 cycles. (4) Blow dry with N2 gun. (5) Check under microscopy, and then measure the metal thickness.
Annealing
(1) Run the RTA 2~3 times with a dummy wafer to check the temperature accuracy and stability.
(2) Load wafer into the chamber, and flow N2 in for a few minutes. (3) Ramp the temperature to 850C linearly in 3 steps, and anneal the wafer at
850°C for 30 seconds. (4) Unload wafer after chamber cools down. (5) Check Ohmic contacts using TLM pattern.
2 Active Region Definition
Solvent Cleaning
(1) Acetone ultrasonic clean, 5 minutes. (2) IPA ultrasonic clean, 5 minutes. (3) DI water rinse, 4 cycles. (4) Blow dry with N2 gun. (5) Dehydration bake, 120 C, 10 minutes in oven.
Photoresist Coating
(1) Cool down after dehydration, 5 minutes. (2) Put wafer on spinner chuck with vacuum on, blow with N2. (3) Coat AZ 703 photoresist. (4) Spin at 4000 rpm for 30 seconds.
104
(5) Soft bake, 90 C, 1 minute, on hotplate.
Photoresist Exposure and Development
(1) Exposure for 3.8 seconds, MA6 aligner, low-vacuum contact mode. (2) Post-exposure bake, 110 C, 1 minute, on hotplate. (3) Develop in FHD-5 for 60 seconds. (4) DI water rinse, 4 cycles. (5) Check under microscopy.
Oxygen Plasma Descum of Photoresist
(1) Chamber O2 pressure: 300 mTorr. (2) Temperature: 70C. (3) Run for 0.7 minute.
CF4 Plasma Treatment for Device Isolation
(1) CF4 flow rate: 150 sccm. (2) Chamber pressure: 50 mTorr. (3) Chamber temperature: 25°C. (4) RF power on showerhead: 300 W. (5) Treatment time: 100 seconds.
Solvent Cleaning to Remove Residue Photoresist
(1) Acetone ultrasonic clean, 5 minutes. (2) IPA ultrasonic clean, 5 minutes. (3) DI water rinse, 4 cycles. (4) Blow dry with N2 gun.
3 D-mode Gate Electrodes Definition
Solvent Cleaning
(1) Acetone ultrasonic clean, 5 minutes. (2) IPA ultrasonic clean, 5 minutes. (3) DI water rinse, 4 cycles. (4) Blow dry with N2 gun. (5) Dehydration bake, 120 C, 10 minutes in oven.
Photoresist Coating
(1) Cool down after dehydration, 5 minutes. (2) Exposure to HMDS vapor, 15 minutes. (3) Put wafer on spinner chuck with vacuum on, blow with N2. (4) Coat AZ 5206 photoresist. (5) Spin at 2000 rpm for 30 seconds.
105
(6) Soft bake, 100 C, 1 minute, on hotplate.
Photoresist Exposure and Development
(1) First exposure for 2.5 seconds, MA6 aligner, low-vacuum contact mode. (2) Post-exposure bake, 115 C, 2 minutes, on hotplate. (3) Second exposure for 12 seconds, MA6 aligner, flood exposure mode. (4) Develop in FHD-5 for 40 seconds. (5) DI water rinse, 4 cycles. (6) Check under microscopy.
Oxygen Plasma Descum of Photoresist
(1) Chamber O2 pressure: 300 mTorr. (2) Temperature: 70C. (3) Run for 0.7 minute.
Surface Preparation
(1) Mix a dilute solution of HCL:H2O = 1:5. (2) Dip in dilute HCl for 15 seconds. (3) DI water rinse, 4 cycles. (4) Blow dry with N2 gun.
Evaporation
(1) Mount wafer into e-beam chamber. (2) Pump down to below 10-6 Torr. (3) Deposit multiple metal layers:
Material Thickness Deposition Rate
Ni 200 Å 2.0 Å/sec
Au 3000 Å 4.0 Å/sec
Liftoff
(1) Soak wafer in Acetone until metal becomes loose and falls off. (2) Rinse with IPA. (3) DI water rinse, 4 cycles. (4) Blow dry with N2 gun. (5) Check under microscopy, and then measure the metal thickness.
4 E-mode Gate Electrodes Definition
Solvent Cleaning
(1) Acetone ultrasonic clean, 5 minutes. (2) IPA ultrasonic clean, 5 minutes.
106
(3) DI water rinse, 4 cycles. (4) Blow dry with N2 gun. (5) Dehydration bake, 120 C, 10 minutes in oven.
Photoresist Coating
(1) Cool down after dehydration, 5 minutes. (2) Exposure to HMDS vapor, 15 minutes. (3) Put wafer on spinner chuck with vacuum on, blow with N2. (4) Coat AZ 5206 photoresist. (5) Spin at 2000 rpm for 30 seconds. (6) Soft bake, 100 C, 1 minute, on hotplate.
Photoresist Exposure and Development
(1) First exposure for 2.5 seconds, MA6 aligner, low-vacuum contact mode. (2) Post-exposure bake, 115 C, 2 minutes, on hotplate. (3) Second exposure for 12 seconds, MA6 aligner, flood exposure mode. (4) Develop in FHD-5 for 40 seconds. (5) DI water rinse, 4 cycles. (6) Check under microscopy.
Oxygen Plasma Descum of Photoresist
(1) Chamber O2 pressure: 300 mTorr. (2) Temperature: 70C. (3) Run for 0.7 minute.
CF4 Plasma Treatment for E-mode Operation
(1) CF4 flow rate: 150 sccm. (2) Chamber pressure: 50 mTorr. (3) Chamber temperature: 25°C. (4) RF power on showerhead: 170 W. (5) Treatment time: 150 seconds.
Surface Preparation
(1) Mix a dilute solution of HCL:H2O = 1:5. (2) Dip in dilute HCl for 15 seconds. (3) DI water rinse, 4 cycles. (4) Blow dry with N2 gun.
Evaporation
(1) Mount wafer into e-beam chamber. (2) Pump down to below 10-6 Torr. (3) Deposit multiple metal layers:
107
Material Thickness Deposition Rate
Ni 200 Å 2.0 Å/sec
Au 3000 Å 4.0 Å/sec
Liftoff
(1) Soak wafer in Acetone until metal becomes loose and falls off. (2) Rinse with IPA. (3) DI water rinse, 4 cycles. (4) Blow dry with N2 gun. (5) Check under microscopy, and then measure the metal thickness.
5 Device Passivation and Annealing
Solvent Cleaning
(1) Acetone ultrasonic clean, 5 minutes. (2) IPA ultrasonic clean, 5 minutes. (3) DI water rinse, 4 cycles. (4) Blow dry with N2 gun. (5) Dehydration bake, 120 C, 10 minutes in oven.
Si3N4 Deposition
(1) SiH4 flow rate: 30 sccm. (2) NH3 flow rate: 40 sccm. (3) N2 flow rate: 1960 sccm. (4) Chamber temperature: 300°C. (5) Chamber pressure: 900 mTorr. (6) RF power: 20 W @ 13.56 MHz. (7) Process time: 20 minutes, 1970 Å.
Solvent Cleaning
(1) Acetone ultrasonic clean, 5 minutes. (2) IPA ultrasonic clean, 5 minutes. (3) DI water rinse, 4 cycles. (4) Blow dry with N2 gun. (5) Dehydration bake, 120 C, 10 minutes in oven.
Photoresist Coating
(1) Cool down after dehydration, 5 minutes. (2) Put wafer on spinner chuck with vacuum on, blow with N2. (3) Coat AZ 703 photoresist. (4) Spin at 4000 rpm for 30 seconds. (5) Soft bake, 90 C, 1 minute, on hotplate.
108
Photoresist Exposure and Development
(1) Exposure for 3.8 seconds, MA6 aligner, low-vacuum contact mode. (2) Post-exposure bake, 110 C, 1 minute, on hotplate. (3) Develop in FHD-5 for 60 seconds. (4) DI water rinse, 4 cycles. (5) Check under microscopy.
Oxygen Plasma Descum of Photoresist
(1) Chamber O2 pressure: 300 mT. (2) Temperature: 70C. (3) Run for 0.7 minute.
Si3N4 Dry Etching to Open Probing Pads
(1) CF4 flow rate: 150 sccm. (2) O2 flow rate: 10 sccm. (3) Chamber pressure: 50 mTorr. (4) Chamber temperature: 25°C. (5) RF power on showerhead: 200 W. (6) Treatment time: 4 minutes.
Solvent Cleaning to Remove Residue Photoresist
(1) Acetone ultrasonic clean, 5 minutes. (2) IPA ultrasonic clean, 5 minutes. (3) DI water rinse, 4 cycles. (4) Blow dry with N2 gun. (5) Dehydration bake, 120 C, 10 minutes in oven.
Annealing to Repair Plasma Induced Damages Under the Gate
(1) Run the RTA 2~3 times with a dummy wafer to check the temperature accuracy and stability.
(2) Load wafer into the chamber, and flow N2 in for a few minutes. (3) Ramp the temperature to 400C linearly in 2 steps, and anneal the wafer at
400°C for 10 minutes. (4) Unload wafer after chamber cools down. (5) Check Device Performance.
109
APPENDIX B
Device DC and RF Characterization
1. DC Characterization
Generally, the on-wafer statistic and dynamic DC characterization of devices can
be performed by using the semiconductor parameter analyzer and the dynamic I-V
analyzer (DIVA), respectively.
Figure B.1 (a) shows the configuration of the static DC measurement. It consists
of a semiconductor parameter analyzer and an on-wafer probe station (not shown
here). Usually a small device with the shape shown in Fig B.1 (b) is used for static
DC measurements. The gate dimension is 1 × 10 μm2. The device is connected to the
semiconductor parameter analyzer with pin-shape probes and cables.
DUT
Semiconductor Parameter Analyzer
Keyboard
SOURCE DRAIN
GATE
Fig. B.1 (a) Configuration of the static DC measurement with a semiconductor parameter analyzer; (b) the shape of the device for the static DC measurement.
(a) (b)
110
Usually, the measurements include the output characteristic IDS-VDS, the transfer
characteristic IDS-VGS, the transconductance characteristic Gm-VGS, the I-V
characteristic of the gate-to-drain Schottky diode IGD-VGD, and the off-state
breakdown voltage VBR. These are basic DC performances of the devices and provide
quick-check after the fabrication of the devices.
PC
DUT
DIVA
Source
Source
DrainGate
Ground
Ground
Signal
Fig. B.2 (a) Configuration of the dynamic I-V measurement with a dynamic I-V
analyzer; (b) the shape of the device for the dynamic I-V measurement; (c) the shape of the GSG probe for RF measurements.
For the dynamic I-V characterization, a dynamic IV analyzer (DIVA) controlled
by PC is used together with GSG (ground-signal-ground) probes and the on-wafer
probe station. The configuration of the measuring system is shown in Fig. B.2 (a).
(a)
(b) (c)
111
The devices for the dynamic I-V measurements have a larger gate dimension than the
ones used in the static DC characterization. The shape of the device and the GSG
probe are shown in Fig. B.2 (b) and (c), respectively. The gate dimension is 1 × 100
μm2.
In the dynamic IV measurements, from the PC software, the quiescent bias point,
the pulse width and duty cycle, the steps of bias sweeping, and the integration factors
can be set. The dynamic IV (or pulse IV) characteristics are good criteria for
investigating the current collapse of the devices, which is a very important issue in
the GaN-based HEMTs.
2. Capacitance-Voltage (CV) Characterization
LCR Meter
DUT
Semiconductor Parameter Analyzer
Keyboard
Fig. B.3 (a) Configuration of the CV measurement with a LCR meter and a semiconductor parameter analyzer; (b) the shape of Schottky diode for the CV
measurement.
Capacitance-Voltage (CV) characterizations are usually conducted on the GaN-
based HEMTs wafers via a circular Schottky diode fabricated on them. The
(a) (b)
112
configuration of the CV measurement system is shown in Fig. B.3 (a), which
includes a LCR Meter and a semiconductor parameter analyzer. The LCR meter is
used for the measurement of the differential capacitance of the Schottky diode and
the semiconductor parameter analyzer is used for controlling the LCR meter, setting
measuring parameters, displaying the CV curves and storing the data. The shape of
the Schottky diode is shown in Fig. B.3 (b), which is formed by a ring-shape Ohmic
contact and a circle-shape Schottky contact in the center.
By applying a small AC signal on the DC-biased Schottky contact, the
differential capacitance of the diode can be measured. The differential capacitance of
the depletion layer is:
dVdQC = (B.1)
The charge in the depletion layer is:
⎟⎟⎠
⎞⎜⎜⎝
⎛−±=⎟⎟
⎠
⎞⎜⎜⎝
⎛−±==
qTk
VVqNAq
TkVV
qNAqNWAqNQ B
biBB
biB
BB2
222 εε
(B.2)
Where A is the area of the Schottky contact, W is the thickness of the depletion layer,
NB is the carrier density, Vbi is the build-in potential, V is the applied DC bias, kB is
Boltzmann’s constant, T is the absolute temperature, and q is the charge of electron.
Applying (B.2) to (B.1), the capacitance can be written as:
113
21
22
−
⎟⎟⎠
⎞⎜⎜⎝
⎛−±=
qTkVVqNAC B
biBε (B.3)
Then, ⎟⎟⎠
⎞⎜⎜⎝
⎛−±=
⎟⎠⎞
⎜⎝⎛ q
TkVVqN
AC
Bbi
B
2212 ε
(B.4)
In an AlGaN/GaN heterostructure, the carrier density NB is a function of depth:
)(xNN BB = . By differentiating (B.4), we can get:
)(2
12
xqNdVC
d
Bε=
⎟⎠⎞
⎜⎝⎛
(B.5)
Then the carrier density can be written as:
dVdCq
C
dVC
dqxN B
εε
3
2
112)( =
⎟⎠⎞
⎜⎝⎛
= (B.6)
And the depth can be written as:
CWx ε
== (B.7)
114
Now, by using (B.6) and (B.7), the carrier density distribution along the depth
can be found out through bias-dependent C-V measurement.
3. Small-Signal RF Characterization
Basically, the small-signal RF characterization is performed on devices by
measuring the scattering parameters (S-parameters) at high frequencies. The
configuration of the S-parameters measurements is shown in Fig. B.4, which consists
of a two-port vector network analyzer (VNA) and a DC bias source. The measuring
system is controlled by a PC running Agilent® IC-CAP software. The bias point and
measuring frequencies can all be set via the software.
DUT
VNA
PCDC Bias
Fig. B.4 Configuration of the S-parameters measurement with a vector network analyzer (VNA) and a DC bias source controlled by PC.
In order to perform accurate RF characterizations of on-wafer devices, the
Impedance Standard Substrate (ISS) is used to calibrate the loss of the coaxial lines
115
loss and to offer the calibration reference plane to the probe tips. “SOLT” is one of
the calibration methods used to measure the “short”, “open”, “load” and “through”
standards. The ISS for SOLT calibration are shown in Fig. B.5.
OPEN SHORT
LOAD THROUGH
Fig. B.5 SOLT calibration standards for on-wafer RF small-signal measurement.
With a calibrated VNA, accurate and precise small-signal S-parameter
measurements can be easily carried out. The S-parameters are the ratio between the
reflected and transmitted voltage waves over a broad bandwidth. When applying the
sinusoidal small-signals to the terminals of the device, the linear circuit performance
is described by its S-parameters.
Apart from the use of the calibration, pad de-dembeding is also applied to
improve the accuracy of the S-parameter measurements. A simplified pad de-
embeding in this work involves an additional S-parameter measurement of the
dummy open probe pad, which is similar to the device but without the active region
and the gate electrode. The shape of the open pad for de-embeding is shown in Fig.
116
B.6. The inevitable parasitic capacitance associated with the pads can be calibrated,
and the reference plane also can be further moved closer to the device plane.
Fig. B.6 The shape of the “open” pad for device de-embeding.
4. Large-Signal RF Characterization
Large-signal RF characterization, or RF power characterization, is different from
the small-signal RF characterization, because the device is under non-linear
operation for high-power applications. This results in different impedances between
small-signal and large-signal applications. These are very important for the optimum
design of oscillators, mixers and power amplifiers in RFICs. The large-signal
characteristic is sensitive to many factors such as DC bias conditions, frequencies,
input and output terminations, signal amplitudes, waveforms and power levels.
Large-signal characterization is performed in a load-pull system. This system is
universally accepted by transistor manufacturers and circuit designers and provides a
systematic RF PA design procedure.
To characterize the RF power performance of the device, usually the one-tone
large-signal measurement is carried out in a load-pull system. The configuration of
117
the one-tone large-signal measurement is shown in Fig. B.7, which includes a load-
pull system, a DC bias source, a RF signal generator and a power meter. The whole
system is controlled by a PC via software named “Automatic Tuner System” (ATS).
Signal Generator
Tuner Controller
Tuner Tuner
Power Meter
DC Bias
PC
DUTPower Sensor
Bias Tee Bias Tee
Fig. B.7 Configuration of the large-signal power measurement, including a load-pull system, a signal generator, a DC bias source, and a power meter controlled by a
PC.PC.
The load-pull system is utilized for large-signal RF characterization at various
tuned impedances, input power levels and bias voltages or currents. Large-signal
characteristics, such as power gain and PAE, are easily and accurately obtained by
the load-pull system. Before the measurement, calibration is usually done with an
ISS “through” pattern.
118
APPENDIX C
Process Flow for E/D-Mode AlGaN/GaN MIS-HFETs
1 Active Region Definition
Solvent Cleaning
(1) Acetone ultrasonic clean, 5 minutes. (2) IPA ultrasonic clean, 5 minutes. (3) DI water rinse, 4 cycles. (4) Blow dry with N2 gun. (5) Dehydration bake, 120 C, 10 minutes in oven.
Photoresist Coating
(1) Cool down after dehydration, 5 minutes. (2) Put wafer on spinner chuck with vacuum on, blow with N2. (3) Coat AZ 703 photoresist. (4) Spin at 4000 rpm for 30 seconds. (5) Soft bake, 90 C, 1 minute, on hotplate.
Photoresist Exposure and Development
(1) Exposure for 3.9 seconds, Karl Suss MA6 aligner, low-vacuum contact mode.
(2) Post-exposure bake, 110 C, 1 minute, on hotplate. (3) Develop in FHD-5 for 60 seconds. (4) DI water rinse, 4 cycles. (5) Check under microscopy.
Oxygen Plasma Descum of Photoresist
(1) Chamber O2 pressure: 300 mTorr. (2) Temperature: 70C. (3) Run for 0.7 minute.
ICP Mesa Etching
(1) Cl2 flow rate: 15 sccm. (2) He flow rate: 10 sccm (3) Chamber pressure: 5 mTorr. (4) RF power on coil: 500 W @ 13.56 MHz. (5) RF power on platen: 135 W @ 13.56 MHz. (6) Etching time: 25 seconds, 1400 Å.
119
Solvent Cleaning to Remove Residue Photoresist
(1) Acetone ultrasonic clean, 5 minutes. (2) IPA ultrasonic clean, 5 minutes. (3) DI water rinse, 4 cycles. (4) Blow dry with N2 gun.
2 Source/Drain Electrodes Definition
Solvent Cleaning
(1) Acetone ultrasonic clean, 5 minutes. (2) IPA ultrasonic clean, 5 minutes. (3) DI water rinse, 4 cycles. (4) Blow dry with N2 gun. (5) Dehydration bake, 120 C, 10 minutes in oven.
Photoresist Coating
(1) Cool down after dehydration, 5 minutes. (2) Put wafer on spinner chuck with vacuum on, blow with N2. (3) Coat AZ 703 photoresist. (4) Spin at 4000 rpm for 30 seconds. (5) Soft bake, 90C, 1 minute, on hotplate.
Photoresist Exposure and Development
(1) Exposure for 3.9 seconds, MA6 aligner, low-vacuum contact mode. (2) Post-exposure bake, 110 C, 1 minute, on hotplate. (3) Develop in FHD-5 for 60 seconds. (4) DI water rinse, 4 cycles. (5) Check under microscopy.
Oxygen Plasma Descum of Photoresist
(1) Chamber O2 pressure: 300 mTorr. (2) Temperature: 70 C. (3) Run for 0.7 minute.
Surface Preparation
(1) Mix a dilute solution of HCL:H2O = 1:5. (2) Dip in dilute HCl for 15 seconds. (3) DI water rinse, 4 cycles. (4) Blow dry with N2 gun.
120
Evaporation
(1) Mount wafer into e-beam chamber. (2) Pump down to below 10-6 Torr. (3) Deposit multiple metal layers:
Material Thickness Deposition Rate
Ti 200 Å 2.0 Å/sec
Al 1500 Å 4.0 Å/sec
Ni 500 Å 2.0 Å/sec
Au 800 Å 4.0 Å/sec
Liftoff
(1) Soak wafer in Acetone until metal becomes loose and falls off. (2) Rinse with IPA. (3) DI water rinse, 4 cycles. (4) Blow dry with N2 gun. (5) Check under microscopy, and then measure the metal thickness.
Annealing
(1) Run the RTA 2~3 times with a dummy wafer to check the temperature accuracy and stability.
(2) Load wafer into the chamber, and flow N2 in for a few minutes. (3) Ramp the temperature to 850C linearly in 3 steps, and anneal the wafer at
850°C for 30 seconds. (4) Unload wafer after chamber cools down. (5) Check Ohmic contacts using TLM pattern.
3 The 1st Si3N4 Layer Patterning
Solvent Cleaning
(1) Acetone ultrasonic clean, 5 minutes. (2) IPA ultrasonic clean, 5 minutes. (3) DI water rinse, 4 cycles. (4) Blow dry with N2 gun. (5) Dehydration bake, 120 C, 10 minutes in oven.
The 1st Si3N4 Deposition
(1) SiH4 flow rate: 30 sccm. (2) NH3 flow rate: 40 sccm. (3) N2 flow rate: 1960 sccm. (4) Chamber temperature: 300°C.
121
(5) Chamber pressure: 900 mTorr. (6) RF power: 20 W @ 13.56 MHz. (7) Process time: 11 minutes, 1140 Å.
Solvent Cleaning
(1) Acetone ultrasonic clean, 5 minutes. (2) IPA ultrasonic clean, 5 minutes. (3) DI water rinse, 4 cycles. (4) Blow dry with N2 gun. (5) Dehydration bake, 120 C, 10 minutes in oven.
Photoresist Coating
(1) Cool down after dehydration, 5 minutes. (2) Put wafer on spinner chuck with vacuum on, blow with N2. (3) Coat AZ 703 photoresist. (4) Spin at 4000 rpm for 30 seconds. (5) Soft bake, 90 C, 1 minute, on hotplate.
Photoresist Exposure and Development
(1) Exposure for 3.9 seconds, MA6 aligner, low-vacuum contact mode. (2) Post-exposure bake, 110 C, 1 minute, on hotplate. (3) Develop in FHD-5 for 60 seconds. (4) DI water rinse, 4 cycles. (5) Check under microscopy.
Oxygen Plasma Descum of Photoresist
(1) Chamber O2 pressure: 300 mTorr. (2) Temperature: 70C. (3) Run for 0.7 minute.
CF4 Plasma Used to Etch Si3N4 and Treat E-mode Gate Region
(1) CF4 flow rate: 150 sccm. (2) Chamber pressure: 50 mTorr. (3) Chamber temperature: 25°C. (4) RF power on showerhead: 150 W. (5) Treatment time: 190 seconds.
Solvent Cleaning to Remove Residue Photoresist
(1) Acetone ultrasonic clean, 5 minutes. (2) IPA ultrasonic clean, 5 minutes. (3) DI water rinse, 4 cycles. (4) Blow dry with N2 gun.
122
4 D-mode Device Window Opened
Solvent Cleaning
(1) Acetone ultrasonic clean, 5 minutes. (2) IPA ultrasonic clean, 5 minutes. (3) DI water rinse, 4 cycles. (4) Blow dry with N2 gun. (5) Dehydration bake, 120 C, 10 minutes in oven.
Photoresist Coating
(1) Cool down after dehydration, 5 minutes. (2) Put wafer on spinner chuck with vacuum on, blow with N2. (3) Coat AZ 703 photoresist. (4) Spin at 4000 rpm for 30 seconds. (5) Soft bake, 90 C, 1 minute, on hotplate.
Photoresist Exposure and Development
(1) Exposure for 3.9 seconds, MA6 aligner, low-vacuum contact mode. (2) Post-exposure bake, 110 C, 1 minute, on hotplate. (3) Develop in FHD-5 for 60 seconds. (4) DI water rinse, 4 cycles. (5) Check under microscopy.
Oxygen Plasma Descum of Photoresist
(1) Chamber O2 pressure: 300 mTorr. (2) Temperature: 70C. (3) Run for 0.7 minute.
Si3N4 Etching to Open D-mode Device Window
(1) CF4 flow rate: 150 sccm. (2) O2 flow rate: 10 sccm. (3) Chamber pressure: 50 mTorr. (4) Chamber temperature: 25°C. (5) RF power on showerhead: 100 W. (6) Etching time: 180 seconds.
Solvent Cleaning to Remove Residue Photoresist
(1) Acetone ultrasonic clean, 5 minutes. (2) IPA ultrasonic clean, 5 minutes. (3) DI water rinse, 4 cycles. (4) Blow dry with N2 gun.
123
5 The 2nd Si3N4 Layer Patterning
Solvent Cleaning
(1) Acetone ultrasonic clean, 5 minutes. (2) IPA ultrasonic clean, 5 minutes. (3) DI water rinse, 4 cycles. (4) Blow dry with N2 gun. (5) Dehydration bake, 120 C, 10 minutes in oven
The 2nd Si3N4 Deposition
(1) SiH4 flow rate: 30 sccm. (2) NH3 flow rate: 40 sccm. (3) N2 flow rate: 1960 sccm. (4) Chamber temperature: 300°C. (5) Chamber pressure: 900 mTorr. (6) RF power: 20 W @ 13.56 MHz. (7) Process time: 100 seconds, ~150 Å.
Solvent Cleaning
(1) Acetone ultrasonic clean, 5 minutes. (2) IPA ultrasonic clean, 5 minutes. (3) DI water rinse, 4 cycles. (4) Blow dry with N2 gun. (5) Dehydration bake, 120 C, 10 minutes in oven.
Photoresist Coating
(1) Cool down after dehydration, 5 minutes. (2) Put wafer on spinner chuck with vacuum on, blow with N2. (3) Coat AZ 703 photoresist. (4) Spin at 4000 rpm for 30 seconds. (5) Soft bake, 90 C, 1 minute, on hotplate.
Photoresist Exposure and Development
(1) Exposure for 3.9 seconds, MA6 aligner, low-vacuum contact mode. (2) Post-exposure bake, 110 C, 1 minute, on hotplate. (3) Develop in FHD-5 for 60 seconds. (4) DI water rinse, 4 cycles. (5) Check under microscopy.
Oxygen Plasma Descum of Photoresist
(1) Chamber O2 pressure: 300 mTorr. (2) Temperature: 70C. (3) Run for 0.7 minute.
124
Total Si3N4 Layer Patterning by CF4 Plasma
(1) CF4 flow rate: 150 sccm. (2) O2 flow rate: 10 sccm. (3) Chamber pressure: 50 mTorr. (4) Chamber temperature: 25°C. (5) RF power on showerhead: 150 W. (6) Treatment time: 180 seconds.
Solvent Cleaning to Remove Residue Photoresist
(1) Acetone ultrasonic clean, 5 minutes. (2) IPA ultrasonic clean, 5 minutes. (3) DI water rinse, 4 cycles. (4) Blow dry with N2 gun.
6 E-mode and D-mode Gate Electrodes Definition
Solvent Cleaning
(1) Acetone ultrasonic clean, 5 minutes. (2) IPA ultrasonic clean, 5 minutes. (3) DI water rinse, 4 cycles. (4) Blow dry with N2 gun. (5) Dehydration bake, 120 C, 10 minutes in oven.
Photoresist Coating
(1) Cool down after dehydration, 5 minutes. (2) Put wafer on spinner chuck with vacuum on, blow with N2. (3) Coat AZ 703 photoresist. (4) Spin at 4000 rpm for 30 seconds. (5) Soft bake, 90 C, 1 minute, on hotplate.
Photoresist Exposure and Development
(1) Exposure for 3.9 seconds, MA6 aligner, low-vacuum contact mode. (2) Post-exposure bake, 110 C, 1 minute, on hotplate. (3) Develop in FHD-5 for 60 seconds. (4) DI water rinse, 4 cycles. (5) Check under microscopy.
Oxygen Plasma Descum of Photoresist
(1) Chamber O2 pressure: 300 mTorr. (2) Temperature: 70C. (3) Run for 0.7 minute.
125
Surface Preparation
(1) Mix a dilute solution of HCL:H2O = 1:5. (2) Dip in dilute HCl for 15 seconds. (3) DI water rinse, 4 cycles. (4) Blow dry with N2 gun.
Evaporation
(1) Mount wafer into e-beam chamber. (2) Pump down to below 10-6 Torr. (3) Deposit multiple metal layers:
Material Thickness Deposition Rate
Ni 200 Å 2.0 Å/sec
Au 3000 Å 4.0 Å/sec
Liftoff
(1) Soak wafer in Acetone until metal becomes loose and falls off. (2) Rinse with IPA. (3) DI water rinse, 4 cycles. (4) Blow dry with N2 gun. (5) Check under microscopy, and then measure the metal thickness.
Annealing to Repair Plasma Induced Damages Under the Gate
(1) Run the RTA 2~3 times with a dummy wafer to check the temperature accuracy and stability.
(2) Load wafer into the chamber, and flow N2 in for a few minutes. (3) Ramp the temperature to 450C linearly in 2 steps, and anneal the wafer at
450°C for 10 minutes. (4) Unload wafer after chamber cools down. (5) Check Device Performance.
126
APPENDIX D
Publication List
A: Publications Related to This Thesis
[1] R. N. Wang, Y. Cai, C. W. Tang, K. M. Lau, and K. J. Chen, “Enhancement-
mode Si3N4/AlGaN/GaN MISHFETs,” IEEE Electron Device Letters, vol. 27,
pp. 793-795, 2006.
[2] R. N. Wang, Y. Cai, C. W. Tang, K. M. Lau, and K. J. Chen, “Planar
integration of E/D-mode AlGaN/GaN HEMTs Using fluoride-based plasma
treatment,” IEEE Electron Device Letters, vol. 27, pp. 633-635, 2006.
[3] R. N. Wang, Y. Cai, W. C. W. Tang, K. M. Lau, and K. J. Chen, “Device
Isolation by plasma treatment for planar integration of E/D-mode AlGaN/GaN
HEMTs,” Japanese Journal of Applied Physics, vol. 46, No. 4B, pp. 2330-
2333, 2007.
[4] R. N. Wang, Y. Cai, W. C. W. Tang, K. M. Lau, and K. J. Chen, “Integration
of Enhancement and depletion-mode AlGaN/GaN MIS-HFETs by fluoride-
based plasma treatment,” Physica Status Solidi (a), vol. 204, no. 6, pp. 2023-
2027, 2007.
[5] R. N. Wang, Y. C. Wu, and K. J. Chen, “Gain improvement of enhancement-
mode AlGaN/GaN HEMTs using dual-gate architectures”, Japanese Journal of
Applied Physics, to be published.
127
[6] R. N. Wang, and K. J. Chen, “Temperature dependence and thermal stability
of planar-integrated enhancement/depletion-mode AlGaN/GaN HEMTs and
digital circuits,” IEEE Trans. Electron Devices, submitted
[7] R. N. Wang, W. C. W. Tang, K. M. Lau, and K. J. Chen, “High temperature
performance and thermal stability of planar integrated enhancement/depletion-
mode AlGaN/GaN HEMTs,” 7th Topical Workshop on Heterostructure
Microelectronics, Chiba, Japan, Aug. 21-24, 2007.
[8] R. N. Wang, Y. C. Wu, C. W. Tang, K. M. Lau, and K. J. Chen, “Gain
improvement of enhancement-mode AlGaN/GaN HEMTs using dual-gate
architectures”, 2007 International Conference on Solid State Devices and
Materials (SSDM 2007), Ibaraki, Japan, Sep. 19-21, 2007.
[9] R. N. Wang, Y. Cai, Z. Cheng, C. W. Tang, K. M. Lau, and K. J. Chen, “A
planar integration process for E/D-mode AlGaN/GaN HEMT DCFL integrated
circuits”, 2006 IEEE Compound Semiconductor IC Symposium, San Antonio,
USA, Nov. 12-15, 2006.
[10] R. N. Wang, Y. Cai, Z. Cheng, C. W. Tang, K. M. Lau, and K. J. Chen,
“Enhancement-mode AlGaN/GaN insulator semiconductor HFETs using
fluoride-based plasma treatment technique”, International Workshop on Nitride
Semiconductors (IWN 2006), Kyoto, Japan, Oct. 22-27, 2006.
[11] R. N. Wang, Y. Cai, C. W. Tang, K. M. Lau, and K. J. Chen, “Device isolation
by plasma treatment for planar integration of E/D-mode AlGaN/GaN HEMTs”
2006 International Conference on Solid State Devices and Materials (SSDM
128
2006), Yokohama, Japan, Sep. 12-15, 2006.
[12] C. W. Yi, R. N. Wang, W. Huang, C. W. Tang, K. M. Lau, and K. J. Chen,
“Reliability of enhancement-mode AlGaN/GaN HEMTs fabricated by fluorine
plasma treatment”, 2007 International Electron Device Meeting (IEDM 2007),
Washington D. C., USA, Dec. 10-12, 2007.
B: Other Publications
[1] Z. Yang, R. N. Wang, S. Jia, D. Wang, B. S. Zhang, K. M. Lau, and K. J.
Chen, “Mechanical characterizations of suspended GaN microstructures
fabricated by GaN-on-patterned-silicon technique,” Applied Physics Letters,
vol. 88, 041913, 2006.
[2] Z. Yang, R. N. Wang, S. Jia, D. Wang, B. S. Zhang, K. M. Lau, and K. J.
Chen, “Fabrication of suspended GaN microstructures using GaN-on-
patterned-silicon (GPS) technique,” Physica Status Solidi (a), vol. 203, pp.
1712-1715, 2006.
[3] Z. Yang, R. N. Wang, D. Wang, B. S. Zhang, K. M. Lau, and K. J. Chen,
“GaN-on-patterned-silicon (GPS) technique for fabrication of GaN-based
MEMS,” Sensors and Actuators A, vol. 130-131, pp. 371-378, 2006.
[4] Z. Yang, R. N. Wang, D. Wang, B. Zhang, K. J. Chen, and K. M. Lau, “GaN
on patterned silicon (GPS) technique for GaN based integrated microsensors”,
2005 International Electron Device Meeting (IEDM 2005), Washington D. C.,
129
USA, Dec. 4-7, 2005.
[5] Z. yang, R. N. Wang, S. Jia, D. Wang, B. Zhang, K. J. Chen, and K. M. Lau,
“Fabrication of suspended GaN microstructures using GaN on patterned silicon
(GPS) technique”, 6th International Conference on Nitride Semiconductors
(ICNS 2006), Bremen, Germany, Aug. 28-Sep. 2, 2005.
[6] Z. Yang, S. Jia, R. N. Wang, D. Wang, K. J. Chen, and K. M. Lau, “GaN on
patterned silicon (GPS) technique for fabrication of GaN-based MEMS”, 13th
Int. Conf. Solid-State Sensors, Actuators, and Microsystems (TRANSDUCERS’
05), Seoul, Korea, June 5-9, 2005.
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