Error Control, Digital Data Communication Technique

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ERRORDETECTION

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Introduction

Regardless of the design of the transmission system, there

will be errors, resulting in the change of one or more bits in

a transmitted frame.

Let us define these probabilities with respect to errors intransmitted frames:

Pb: Probability of a single bit error; also known as the bit

error rate.

P1: Probability that a frame arrives with no bit errors. P2: Probability that a frame arrives with one or more

undetected bit errors.

P3: Probability that a frame arrives with one or more

detected bit errors but no undetected bit errors. 2


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Introduction

First, consider the case when no means are taken

to detect errors; the probability of detected

errors (P3), then, is zero.

To express the remaining probabilities, assume

that the probability that any bit is in error (Pb) is

constant and independent for each bit. Then we

haveP1= (1- Pb)

F

P2

=1 - P1

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Introduction

where F is the number of bits per frame.

In words, the probability that a frame arrives with

no bit errors decreases when the probability of a

single bit error increases, as you would expect.

Also, the probability that a frame arrives with no

bit errors decreases with increasing frame length;

The longer the frame, the more bits it has andthe higher the probability that one of these is in

error.

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Introduction

Figure illustrates the error detection process.

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Introduction

For a given frame of bits, additional bits that

constitute an error-detecting codeare added by the

transmitter.

This code is calculated as a function of the othertransmitted bits.

Typically, for a data block of k bits, the error-

detecting algorithm yields an error-detecting code of

nkbits, where (nk) < k.

The error-detecting code, also referred to as the

check bits, is appended to the data block to produce

a frame of nbits, which is then transmitted. 6


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Introduction

The receiver separates the incoming frame into thek

bits of data and (n k) bits of the error-detecting

code.

The receiver performs the same error-detectingcalculation on the data bits and compares this value

with the value of the incoming error-detecting code.

A detected error occurs if and only if there is a

mismatch.

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Introduction

Popular techniques are:

1. Simple Parity check

2. Two-dimensional Parity check3. Checksum

4. Cyclic redundancy check

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Parity Check

The most common and least expensive mechanism

for errordetection is the simple parity check.

In this technique, a redundant bit called parity bit, is

appended to every data unit so that the number of1s in the unit (including the parity becomes even).

Blocks of data from the source are subjected to a

check bit or Parity bit generator form, where a parity

of 1 is added to the block if it contains an odd

number of 1s (ON bits) and 0 is added if it contains

an even number of 1s.

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Parity Check

At the receiving end the parity bit is computed from the

received data bits and compared with the received parity

bit, as shown in Fig.

This scheme makes the total number of 1seven, that iswhy it is called even parity checking.

Considering a 4-bit word, different combinations of the

data words and the corresponding code words are given

in Table

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Two-dimension Parity Check

Performance can be improved by using two-

dimensional parity check, which organizes the block

of bits in the form of a table.

Parity check bits are calculated for each row, which isequivalent to a simple parity check bit.

Parity check bits are also calculated for all columns

then both are sent along with the data.

At the receiving end these are compared with the

parity bits calculated on the received data.

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Checksum

In checksum error detection scheme, the data

is divided into k segments each of m bits.

In the senders end the segments are added

using 1s complement arithmetic to get the

sum. The sum is complemented to get the

checksum.

The checksum segment is sent along with the

data segments as shown in Fig.

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At Senders Site

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Checksum

At the receivers end, all received segments

are added using 1scomplement arithmetic to

get the sum.

The sum is complemented.

If the result is zero, the received data is

accepted; otherwise discarded, as shown in

Fig.

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At Receivers Site

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CRC

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Cyclic Redundancy Checks (CRC)

This Cyclic Redundancy Check is the most

powerful and easy to implement technique.

Unlike checksum scheme, which is based on

addition, CRC is based on binary division.

In CRC, a sequence of redundant bits, called cyclic

redundancy check bits, are appended to the end

of data unit so that the resulting data unitbecomes exactly divisible by a second,

predetermined binary number.

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At the destination, the incoming data unit is

divided by the same number.

If at this step there is no remainder, the data unit

is assumed to be correct and is thereforeaccepted.

A remainder indicates that the data unit has been

damaged in transit and therefore must berejected.

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Given a k-bit block of bits, or message, the

transmitter generates an (nk)-bit sequence, known

as a frame check sequence (FCS), such that the

resulting frame, consisting of n bits, is exactlydivisible by some predetermined number.

The receiver then divides the incoming frame by that

number and, if there is no remainder, assumes there

was no error.

Can state this procedure in three equivalent ways:

modulo 2 arithmetic, polynomials, and digital logic,

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Modulo 2 Arithmetic

Modulo 2 arithmetic uses binary addition with nocarries, which is just the exclusive or operation.

For example:

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Modulo 2 Arithmetic

Now define:

T = n-bit frame to be transmitted

D = k-bit message, the first k bits of T F = (n-k)-bit FCS, the last (n-k) bits of T

P = pattern of n -k+ 1 bits; this is the

predetermined divisor

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Modulo 2 Arithmetic

We would like T/P to have no remainder. It

should be clear that

T=2 n-k D + F

That is, by multiplying D by 2 n-k , we have, in effect,

shifted it to the left by (n-k) bits and padded out the

result with zeroes.

Adding F yields the concatenation of D and F, whichis T. We want T to be exactly divisible by P. Suppose

that we divided 2 n-k D by P:

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Modulo 2 Arithmetic

(2 n-k D)/P = Q + (R/P) ----------------------(1)

There is a quotient and a remainder. Because division

is modulo 2, the remainder is always at least one bit

less than the divisor. We will use this remainder asour FCS.

Then

T=2

n-k

D + R ------------------------(2) Question: Does this R satisfy our condition that T/P

have no remainder? To see that it does, consider

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Modulo 2 Arithmetic

T/P=(2 n-k D + R)/P =(2 n-k D/P) + (R/P)

Substituting equation 1 we have

(T/P) =Q + (R/P) + (R/P)

However, any binary number added to itself (modulo 2)yields zero. Thus,

(T/P) = Q + ((R+R)/P) =Q

There is no remainder, and, therefore, T is exactlydivisible by P. Thus, the FCS is easily generated:

Simply divide 2 n-k D by P and use the remainder as the

FCS. On reception, the receiver will divide T by P and will

get no remainder if there have been no errors. 27


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Example

Given

Message D = 1010001101 (10 bits)

Pattern P = 110101 (6 bits)

FCS R = to be calculated (5 bits)

n = 15, k=10 and (n-k) =5

The message M is multiplied by 25, yielding

101000110100000. This product is divided by P:

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Example

The remainder (R = 01110) is added to 25D to give T =

101000110101110, which is transmitted.

If there are no errors, the receiver receives T intact.

The received frame is divided by P:

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Modulo 2 Arithmetic

Because there is no remainder, it is assumed that

there have been no errors

The pattern P is chosen to be one bit longer than the

desired FCS, and the exact bit pattern chosendepends on the type of errors expected.

At minimum, both the high- and low-order bits of P

must be 1.

The occurrence of an error is easily expressed.

An error results in the reversal of a bit.

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Modulo 2 Arithmetic

This is equivalent to taking the exclusive-or of

the bit and 1 (modulo 2 addition of 1 to the

bit): 0 + 1 = 1; 1 + 1 = 0.

Thus, the errors in an n -bit frame can be

represented by an n -bit field with 1s in each

error position.

The resulting frame Tr, can be expressed as

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Modulo 2 Arithmetic

where

T = transmitted frame

E = error pattern with 1s in positions where errors

occur Tr= received frame

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Polynomials

A second way of viewing the CRC process is to

express all values as polynomials in a dummy

variable X, with binary coefficients.

The coefficients correspond to the bits in the binarynumber

Thus, for D= 110011, we have D(X) = x5+ x4+ X + 1,

and, for P = 11001, we have P(X) = x4+ x3+ 1.

Arithmetic operations are again modulo 2.

The CRC process can now be described as

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Polynomials

(X n-kD(X))/P(X) = Q(X) + R(X)/P(X)

T(X) = X n-kD(X) + R(X)

An error E(X) will only be undetectable if it is divisible

by P(X).

It can be shown that all of the following errors arenot divisible by a suitably chosen P(X)and, hence,

are detectable:

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Polynomials

All single-bit errors.

All double-bit errors, as long as P(X) has at least three

Is.

Any odd number of errors, as long as P(X) contains afactor (X + 1).

Any burst error for which the length of the burst is

less than the length of the divisor polynomial; that is,

less than or equal to the length of the FCS.

Most larger burst errors.

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Polynomials

In addition, it can be shown that if all error

patterns are considered equally likely,

then for a burst error of length r + 1,

the probability that E(X) is divisible by P(X) is

1/2 r-1,

and for a longer burst, the probability is 1/2 r

where r is the length of the FCS.

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Polynomials

Four version of P(X) are widely used:

CRC-12= X12+ X11+X3+X2+ X +1

CRC-16 = X16+ X15+ X2+ 1

CRC-CCITT = X16+ X12+ X5+ 1

CRC-32 = X32+ X23+ X22+ X16+ X12+ X11+ X10+ X8

+ X7+ X5 + X4+ X2+ X+ 1

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LECTURE 25b

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Digital Logic

The CRC process can be represented by, and indeedimplemented as, a dividing circuit consisting of exclusive-or gates and a shift register.

The shift register is a string of 1-bit storage devices.

Each device has an output line, that indicates the valuecurrently stored, and an input line.

At discrete time instants, known as clock times, the valuein the storage device is replaced by the value indicated by

its input line. The entire register is clocked simultaneously, causing a 1-

bit shift along the entire register.

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Digital Logic

The circuit is implemented as follows:

1. The register contains n-k bits, equal to the length of

the FCS.

2. There are up to n-k exclusive-or gates.3. The presence or absence of a gate corresponds to

the presence or absence of a term in the divisor

polynomial, P(X).

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Digital Logic

The architecture is best explained by the

following example

For example

D= 1010001101, D(X) = X9+ X7+X3+ X2 + 1,

for P = 110101, we have P(X) = X5+ X4+ X2+ 1.

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Digital Logic

The general architecture of the shift register

implementation of a CRC for the polynomial

where a0= an= 1 and all other aiequal either

0 or 1.

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Error Control, Digital Data Communication Technique