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eSB Series
Turbo Tiny Controller
Pad Diagrams Doc. Version 2
ELAN MICROELECTRONICS CORP. Sep 2005
Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM. Windows is a trademark of Microsoft Corporation. ELAN and ELAN logo are trademarks of ELAN Microelectronics Corporation. Copyright © 2005 by ELAN Microelectronics Corporation All Rights Reserved Printed in Taiwan The contents of in this specification are subject to change without notice. ELAN Microelectronics assumes no responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics makes no commitment to update, or to keep current the information and material contained in this specification. Such information and material may change to conform to each confirmed order.
In no event shall ELAN Microelectronics be made responsible to any claims attributed to errors, omissions, or other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not be liable for direct, indirect, special incidental, or consequential damages arising out of the use of such information or material.
The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of such agreement.
ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of ELAN Microelectronics product in such applications is not supported and is prohibited. NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESS WRITTEN PERMISSION OF ELAN MICROELECTRONICS.
ELAN MICROELECTRONICS CORPORATION Headquarters: No. 12, Innovation Road 1 Science-based Industrial Park Hsinchu, Taiwan, R.O.C. 30077 Tel: +886 3 563-9977 Fax: +886 3 563-9966 http://www.emc.com.tw
Hong Kong: Elan (HK) Microelectronics Corporation, Ltd. Rm. 1005B, 10/F Empire Centre 68 Mody Road, Tsimshatsui Kowloon , HONG KONG Tel: +852 2723-3376 Fax: +852 2723-7780 [email protected]
USA: Elan Information Technology Group 1821 Saratoga Ave., Suite 250 Saratoga, CA 95070 USA Tel: +1 408 366-8223 Fax: +1 408 366-8220
Europe: Elan Microelectronics Corp. (Europe) Siewerdtstrasse 105 8050 Zurich, SWITZERLAND Tel: +41 43 299-4060 Fax: +41 43 299-4079 http://www.elan-europe.com
Shenzhen: Elan Microelectronics Shenzhen, Ltd. SSMEC Bldg., 3F, Gaoxin S. Ave. Shenzhen Hi-Tech Industrial Park Shenzhen, Guandong, CHINA Tel: +86 755 2601-0565 Fax: +86 755 2601-0500
Shanghai: Elan Microelectronics Shanghai Corporation, Ltd. 23/Bldg. #115 Lane 572, Bibo RoadZhangjiang Hi-Tech Park Shanghai, CHINA Tel: +86 021 5080-3866 Fax: +86 021 5080-4600
eSB Series
Contents 0. PIN DIMENSIONS .............................................................................................................1
1. eSB015 Pad Diagram .......................................................................................................2
2. eSB020 Pad Diagram .......................................................................................................3
3. eSB030 Pad Diagram .......................................................................................................4
4. eSB040 Pad Diagram .......................................................................................................5
5. eSB065 Pad Diagram .......................................................................................................6
6. eSB080 Pad Diagram .......................................................................................................7
7. eSB100 Pad Diagram .......................................................................................................8
8. eSB120 Pad Diagram .......................................................................................................9
9. eSB170 Pad Diagram .....................................................................................................10
10. eSB200 Pad Diagram ..................................................................................................... 11
11. eSB270 Pad Diagram .....................................................................................................12
12. eSB320 Pad Diagram .....................................................................................................13
13. eSCZ000 Pad Diagram ...................................................................................................14
Pad Diagrams (V2) 09.30.2005 • iii
eSC Series
Revision History Version Revision Description Date
1 Initial version 2005/07/07
2 Add eSB170; eSB200; eSB270; eSB320 2005/09/30
iv • Pad Diagrams (V2) 09.30.2005
eSB Series
0. PIN DIMENSIONS 0.1. Pad dimensions diagram pad size
30μm
pad pitch
120μm
pad gappad siz
e
90μm(x)
90μm(y)
0.2. Pin Dimensions for eSA series
Size Unit Item X Y
Pad size 90 90 Pad pitch 120 Pad gap 30
μm
Pad Diagrams (V2) 09.30.2005 • 1 (These diagrams are subject to change without further notice)
eSB Series
1. eSB015 Pad Diagram
P1.3
VD
D0
P2.0
P2.1
P2.2
P2.3
P3.0
P3.1
P3.2
P3.3
36
30
11
12
13
14
15162122232425 27282926 34313233
38
37
VSS1
VO1B
VO1A
VDD1
P1.2
P1.1
P1.0
VSS0
OSCO
OSCI
IRin
IRout
RESET B
(0,0)
eSB015
Pin NO. Symbol X Y Pin NO. Symbol X Y 11 VSS1 -991.7 135.9 27 P2.1 -19.8 -513.4 12 VO1B -877.4 -26.1 28 P2.0 106.6 -513.4 13 VO1A -877.4 -146.1 29 VDD0 244.2 -513.4 14 VDD1 -991.7 -303.7 30 P1.3 383.1 -513.4 15 IRin -1012.5 -513.4 31 P1.2 509.5 -513.4 16 IRout -891.0 -513.4 32 P1.1 629.5 -513.4 21 P3.3 -768.0 -513.4 33 P1.0 755.9 -513.4 22 P3.2 -641.6 -513.4 34 RESETB 875.9 -513.4 23 P3.1 -518.6 -513.4 36 OSCI 978.4 -314.7 24 P3.0 -392.2 -513.4 37 OSCO 978.4 -190.2 25 P2.3 -269.2 -513.4 38 VSS0 978.4 -50.7 26 P2.2 -142.8 -513.4
Chip size : 2250 * 1350 um For PCB layout, IC substrate must be connected to ground. Note : 1. VO1B should be floating or connected to VDD1 when not in use.
2. VSS0 & VSS1 should be connected together with negative power.
2 • Pad Diagrams (V2) 09.30.2005 (These diagrams are subject to change without further notice)
eSB Series
2. eSB020 Pad Diagram
P1.3
VD
D0
P2.0
P2.1
P2.2
P2.3
P3.0
P3.1
P3.2
P3.3
36
30
11
12
13
14
15162122232425 27282926 34313233
38
37
VSS1
VO1B
VO1A
VDD1
P1.2
P1.1
P1.0
VSS0
OSCO
OSCI
IRin
IRout
RESET B
(0,0)
eSB020
Pin NO. Symbol X Y Pin NO. Symbol X Y 11 VSS1 -991.7 135.9 27 P2.1 -19.8 -513.4 12 VO1B -877.4 -26.1 28 P2.0 106.6 -513.4 13 VO1A -877.4 -146.1 29 VDD0 244.2 -513.4 14 VDD1 -991.7 -303.7 30 P1.3 383.1 -513.4 15 IRin -1012.5 -513.4 31 P1.2 509.5 -513.4 16 IRout -891.0 -513.4 32 P1.1 629.5 -513.4 21 P3.3 -768.0 -513.4 33 P1.0 755.9 -513.4 22 P3.2 -641.6 -513.4 34 RESETB 875.9 -513.4 23 P3.1 -518.6 -513.4 36 OSCI 978.4 -314.7 24 P3.0 -392.2 -513.4 37 OSCO 978.4 -190.2 25 P2.3 -269.2 -513.4 38 VSS0 978.4 -50.7 26 P2.2 -142.8 -513.4
Chip size : 2300 * 1400 um For PCB layout, IC substrate must be connected to ground. Note : 1. VO1B should be floating or connected to VDD1 when not in use.
2. VSS0 & VSS1 should be connected together with negative power.
Pad Diagrams (V2) 09.30.2005 • 3 (These diagrams are subject to change without further notice)
eSB Series
3. eSB030 Pad Diagram
P1.3
VD
D0
P2.0
P2.1
P2.2
P2.3
P3.0
P3.1
P3.2
P3.3
36
30
11
12
13
14
15162122232425 27282926 34313233
38
37
VSS1
VO1B
VO1A
VDD1
P1.2
P1.1
P1.0
VSS0
OSCO
OSCI
IRin
IRout
RESET B
(0,0)
eSB030
Pin NO. Symbol X Y Pin NO. Symbol X Y 11 VSS1 -991.7 15.9 27 P2.1 -19.8 -633.4 12 VO1B -877.4 -146.1 28 P2.0 106.6 -633.4 13 VO1A -877.4 -266.1 29 VDD0 244.2 -633.4 14 VDD1 -991.7 -423.7 30 P1.3 383.1 -633.4 15 IRin -1012.5 -633.4 31 P1.2 509.5 -633.4 16 IRout -891.0 -633.4 32 P1.1 629.5 -633.4 21 P3.3 -768.0 -633.4 33 P1.0 755.9 -633.4 22 P3.2 -641.6 -633.4 34 RESETB 875.9 -633.4 23 P3.1 -518.6 -633.4 36 OSCI 978.4 -434.7 24 P3.0 -392.2 -633.4 37 OSCO 978.4 -310.2 25 P2.3 -269.2 -633.4 38 VSS0 978.4 -170.7 26 P2.2 -142.8 -633.4
Chip size : 2300 * 1600 um For PCB layout, IC substrate must be connected to ground. Note : 1. VO1B should be floating or connected to VDD1 when not in use.
2. VSS0 & VSS1 should be connected together with negative power.
4 • Pad Diagrams (V2) 09.30.2005 (These diagrams are subject to change without further notice)
eSB Series
4. eSB040 Pad Diagram
P1.3
VD
D0
P2.0
P2.1
P2.2
P2.3
P3.0
P3.1
P3.2
P3.3
36
30
11
12
13
14
15162122232425 27282926 34313233
38
37
VSS1
VO1B
VO1A
VDD1
P1.2
P1.1
P1.0
VSS0
OSCO
OSCI
IRin
IRout
RESET B
(0,0)
eSB040
Pin NO. Symbol X Y Pin NO. Symbol X Y 11 VSS1 -991.7 15.9 27 P2.1 -19.8 -633.4 12 VO1B -877.4 -146.1 28 P2.0 106.6 -633.4 13 VO1A -877.4 -266.1 29 VDD0 244.2 -633.4 14 VDD1 -991.7 -423.7 30 P1.3 383.1 -633.4 15 IRin -1012.5 -633.4 31 P1.2 509.5 -633.4 16 IRout -891.0 -633.4 32 P1.1 629.5 -633.4 21 P3.3 -768.0 -633.4 33 P1.0 755.9 -633.4 22 P3.2 -641.6 -633.4 34 RESETB 875.9 -633.4 23 P3.1 -518.6 -633.4 36 OSCI 978.4 -434.7 24 P3.0 -392.2 -633.4 37 OSCO 978.4 -310.2 25 P2.3 -269.2 -633.4 38 VSS0 978.4 -170.7 26 P2.2 -142.8 -633.4
Chip size : 2300 * 1600 um For PCB layout, IC substrate must be connected to ground. Note : 1. VO1B should be floating or connected to VDD1 when not in use.
2. VSS0 & VSS1 should be connected together with negative power.
Pad Diagrams (V2) 09.30.2005 • 5 (These diagrams are subject to change without further notice)
eSB Series
5. eSB065 Pad Diagram
P2.0
P2.1
P2.2
P2.3
P3.0
P3.1
P3.2
P3.3
31
26
7
8 9
1112131415161718 2021
25
19
30
27
28
29
33
32
VSS0
OSCO
OSCI
IRin
IRout
(0,0)
eSB065
22 2410 23
RESETB
P1.0
P1.1
P1.2
P1.3
VDD0
P4.0
P4.1
P4.2
P4.3
VO
1A
VO
1B
VSS1
VD
D1
Pin NO. Symbol X Y Pin NO. Symbol X Y 7 VSS1 -1142.9 -841.7 21 P2.3 776.2 -818.4 8 VO1B -980.9 -727.4 22 P2.2 902.6 -818.4 9 VO1A -860.9 -727.4 23 P2.1 1025.6 -818.4 10 VDD1 -703.3 -841.7 24 P2.0 1152.0 -818.4 11 IRin -453.1 -818.4 25 VDD0 1184.4 -528.8 12 IRout -331.6 -818.4 26 P1.3 1184.4 -389.9 13 P4.3 -208.6 -818.4 27 P1.2 1184.4 -263.5 14 P4.2 -88.6 -818.4 28 P1.1 1184.4 -143.5 15 P4.1 34.4 -818.4 29 P1.0 1184.4 -17.1 16 P4.0 154.4 -818.4 30 RESETB 1184.4 102.9 17 P3.3 277.4 -818.4 31 OSCI 1184.4 225.9 18 P3.2 403.8 -818.4 32 OSCO 1184.4 350.4 19 P3.1 526.8 -818.4 33 VSS0 1184.4 489.9 20 P3.0 653.2 -818.4
Chip size : 2550 * 1950 um For PCB layout, IC substrate must be connected to ground. Note : 1. VO1B should be floating or connected to VDD1 when not in use.
2. VSS0 & VSS1 should be connected together with negative power.
6 • Pad Diagrams (V2) 09.30.2005 (These diagrams are subject to change without further notice)
eSB Series
6. eSB080 Pad Diagram
P2.0
P2.1
P2.2
P2.3
P3.0
P3.1
P3.2
P3.3
31
26
7
8 9
1112131415161718 2021
25
19
30
27
28
29
33
32
VSS0
OSCO
OSCI
IRin
IRout
(0,0)
eSB080
22 2410 23
RESETB
P1.0
P1.1
P1.2
P1.3
VDD0
P4.0
P4.1
P4.2
P4.3
VO
1A
VO
1B
VSS1
VD
D1
Pin NO. Symbol X Y Pin NO. Symbol X Y 7 VSS1 -1142.9 -841.7 21 P2.3 776.2 -818.4 8 VO1B -980.9 -727.4 22 P2.2 902.6 -818.4 9 VO1A -860.9 -727.4 23 P2.1 1025.6 -818.4 10 VDD1 -703.3 -841.7 24 P2.0 1152.0 -818.4 11 IRin -453.1 -818.4 25 VDD0 1184.4 -528.8 12 IRout -331.6 -818.4 26 P1.3 1184.4 -389.9 13 P4.3 -208.6 -818.4 27 P1.2 1184.4 -263.5 14 P4.2 -88.6 -818.4 28 P1.1 1184.4 -143.5 15 P4.1 34.4 -818.4 29 P1.0 1184.4 -17.1 16 P4.0 154.4 -818.4 30 RESETB 1184.4 102.9 17 P3.3 277.4 -818.4 31 OSCI 1184.4 225.9 18 P3.2 403.8 -818.4 32 OSCO 1184.4 350.4 19 P3.1 526.8 -818.4 33 VSS0 1184.4 489.9 20 P3.0 653.2 -818.4
Chip size : 2600 * 2000 um For PCB layout, IC substrate must be connected to ground. Note : 1. VO1B should be floating or connected to VDD1 when not in use.
2. VSS0 & VSS1 should be connected together with negative power.
Pad Diagrams (V2) 09.30.2005 • 7 (These diagrams are subject to change without further notice)
eSB Series
7. eSB100 Pad Diagram
P3.0
P3.1
P3.2
P3.3
P4.0
P4.1
P4.2
P4.3
31
26
7
8 9
1112131415161718 2021
25
19
30
27
28
29
33
32
VSS0
OSCO
OSCI
IRin
IRout
(0,0)
eSB100
22 2410 23
RESETB
P1.0
P1.1
P1.2
P1.3
VDD0
P5.0
P5.1
P5.2
P5.3
VO
1A
VO
1B
VSS1
VD
D1
31
30
33
32
P2.0
P2.1
P2.2
P2.3
Pin NO. Symbol X Y Pin NO. Symbol X Y
7 VSS1 -1142.9 -1096.7 23 P3.1 1025.6 -1073.4 8 VO1B -980.9 -982.4 24 P3.0 1152.6 -1073.4 9 VO1A -860.9 -982.4 25 P2.3 1118.4 -793.2 10 VDD1 -703.3 -1096.7 26 P2.2 1118.4 -666.8 11 IRin -4440.3 -1073.4 27 P2.1 1118.4 -543.8 12 IRout -318.8 -1073.4 28 P2.0 1118.4 -417.4 13 P5.3 -195.8 -1073.4 29 VDD0 1118.4 -279.8 14 P5.2 -75.8 -1073.4 30 P1.3 1118.4 -140.9 15 P5.1 47.2 -1073.4 31 P1.2 1118.4 -14.5 16 P5.0 167.2 -1073.4 32 P1.1 1118.4 105.5 17 P4.3 290.2 -1073.4 33 P1.0 1118.4 231.9 18 P4.2 410.2 -1073.4 30 RESETB 1118.4 351.9 19 P4.1 533.2 -1073.4 31 OSCI 1118.4 474.9 20 P4.0 653.2 -1073.4 32 OSCO 1118.4 599.4 21 P3.3 776.2 -1073.4 33 VSS0 1118.4 738.9 22 P3.2 902.6 -1073.4
Chip size : 2550 * 2450 um For PCB layout, IC substrate must be connected to ground. Note : 1. VO1B should be floating or connected to VDD1 when not in use.
2. VSS0 & VSS1 should be connected together with negative power.
8 • Pad Diagrams (V2) 09.30.2005 (These diagrams are subject to change without further notice)
eSB Series
8. eSB120 Pad Diagram
P3.0
P3.1
P3.2
P3.3
P4.0
P4.1
P4.2
P4.3
31
26
7
8 9
1112131415161718 2021
25
19
30
27
28
29
33
32
VSS0
OSCO
OSCI
IRin
IRout
(0,0)
eSB120
22 2410 23
RESETB
P1.0
P1.1
P1.2
P1.3
VDD0
P5.0
P5.1
P5.2
P5.3
VO
1A
VO
1B
VSS1
VD
D1
31
30
33
32
P2.0
P2.1
P2.2
P2.3
Pin NO. Symbol X Y Pin NO. Symbol X Y
7 VSS1 -1142.9 -1096.7 23 P3.1 1025.6 -1073.4 8 VO1B -980.9 -982.4 24 P3.0 1152.6 -1073.4 9 VO1A -860.9 -982.4 25 P2.3 1118.4 -793.2 10 VDD1 -703.3 -1096.7 26 P2.2 1118.4 -666.8 11 IRin -4440.3 -1073.4 27 P2.1 1118.4 -543.8 12 IRout -318.8 -1073.4 28 P2.0 1118.4 -417.4 13 P5.3 -195.8 -1073.4 29 VDD0 1118.4 -279.8 14 P5.2 -75.8 -1073.4 30 P1.3 1118.4 -140.9 15 P5.1 47.2 -1073.4 31 P1.2 1118.4 -14.5 16 P5.0 167.2 -1073.4 32 P1.1 1118.4 105.5 17 P4.3 290.2 -1073.4 33 P1.0 1118.4 231.9 18 P4.2 410.2 -1073.4 30 RESETB 1118.4 351.9 19 P4.1 533.2 -1073.4 31 OSCI 1118.4 474.9 20 P4.0 653.2 -1073.4 32 OSCO 1118.4 599.4 21 P3.3 776.2 -1073.4 33 VSS0 1118.4 738.9 22 P3.2 902.6 -1073.4
Chip size : 2600 * 2500 um For PCB layout, IC substrate must be connected to ground. Note : 1. VO1B should be floating or connected to VDD1 when not in use.
2. VSS0 & VSS1 should be connected together with negative power.
Pad Diagrams (V2) 09.30.2005 • 9 (These diagrams are subject to change without further notice)
eSB Series
9. eSB170 Pad Diagram
P3.3
P4.0
P4.1
P4.2
P4.3
42 37
9
1011
1314151617181920 2223
36
21
41 3839404443
VSS0
OSC
O
OSCI
IRin
IRout
(0,0)
eSB170
24
26
12
25
RESETB
P1.0
P1.1
P1.2
P1.3
VD
D0
P5.0
P5.1
P5.2
P5.3
VO
1A
VO
1B
VSS1
VD
D1
46454847
P2.0
P3.0
P3.1
P3.2
P2.1
P2.2
P2.3
Pin NO. Symbol X Y Pin NO. Symbol X Y 9 VSS1 -895.3 -1751.7 25 P3.1 883.4 -1403.4
10 VO1B -733.3 -1637.4 26 P3.0 883.4 -1293.4 11 VO1A -613.3 -1637.4 36 P2.3 910.0 1738.4 12 VDD1 -455.7 -1751.7 37 P2.2 800.0 1738.4 13 IRin -193.6 -1738.4 38 P2.1 687.0 1738.4 14 IRout -83.6 -1738.4 39 P2.0 577.0 1738.4 15 P5.3 29.4 -1738.4 40 VDD0 438.1 1738.4 16 P5.2 139.4 -1738.4 41 P1.3 303.1 1738.4 17 P5.1 252.4 -1738.4 42 P1.2 193.1 1738.4 18 P5.0 362.4 -1738.4 43 P1.1 80.1 1738.4 19 P4.3 475.4 -1738.4 44 P1.0 -29.9 1738.4 20 P4.2 585.4 -1738.4 45 RESETB -142.9 1738.4 21 P4.1 698.4 -1738.4 46 OSCI -259.4 1738.4 22 P4.0 808.4 -1738.4 47 OSCO -383.9 1738.4 23 P3.3 921.4 -1738.4 48 VSS0 -523.4 1738.4 24 P3.2 883.4 -1516.4
Chip size : 2080 * 3790 um For PCB layout, IC substrate must be connected to ground. Note : 1. VO1B should be floating or connected to VDD1 when not in use.
2. VSS0 & VSS1 should be connected together with negative power.
10 • Pad Diagrams (V2) 09.30.2005 (These diagrams are subject to change without further notice)
eSB Series
10. eSB200 Pad Diagram
P3.3
P4.0
P4.1
P4.2
P4.3
42 37
9
1011
13 141516 17 1819 20 2223
36
21
41 3839404443
VSS0
OSC
O
OSC
I
IRin
IRout
(0,0)
eSB200
24
26
12
25
RESETB
P1.0
P1.1
P1.2
P1.3
VD
D0
P5.0
P5.1
P5.2
P5.3
VO
1A
VO
1B
VSS1
VD
D1
464548 47
P2.0
P3.0
P3.1
P3.2
P2.1
P2.2
P2.3
Pin NO. Symbol X Y Pin NO. Symbol X Y 9 VSS1 -895.3 -1751.7 25 P3.1 883.4 -1403.4 10 VO1B -733.3 -1637.4 26 P3.0 883.4 -1293.4 11 VO1A -613.3 -1637.4 36 P2.3 910.0 1738.4 12 VDD1 -455.7 -1751.7 37 P2.2 800.0 1738.4 13 IRin -193.6 -1738.4 38 P2.1 687.0 1738.4 14 IRout -83.6 -1738.4 39 P2.0 577.0 1738.4 15 P5.3 29.4 -1738.4 40 VDD0 438.1 1738.4 16 P5.2 139.4 -1738.4 41 P1.3 303.1 1738.4 17 P5.1 252.4 -1738.4 42 P1.2 193.1 1738.4 18 P5.0 362.4 -1738.4 43 P1.1 80.1 1738.4 19 P4.3 475.4 -1738.4 44 P1.0 -29.9 1738.4 20 P4.2 585.4 -1738.4 45 RESETB -142.9 1738.4 21 P4.1 698.4 -1738.4 46 OSCI -259.4 1738.4 22 P4.0 808.4 -1738.4 47 OSCO -383.9 1738.4 23 P3.3 921.4 -1738.4 48 VSS0 -523.4 1738.4 24 P3.2 883.4 -1516.4
Chip size : 2100 * 3800 um For PCB layout, IC substrate must be connected to ground. Note : 1. VO1B should be floating or connected to VDD1 when not in use.
2. VSS0 & VSS1 should be connected together with negative power.
Pad Diagrams (V2) 09.30.2005 • 11 (These diagrams are subject to change without further notice)
eSB Series
11. eSB270 Pad Diagram
P3.3
P4.0
P4.1
P4.2
P4.3
42 37
9
1011
13 141516 17 1819 20 2223
36
21
41 3839404443
VSS0
OSC
O
OSC
I
IRin
IRout
(0,0)
eSB270
24
26
12
25
RESETB
P1.0
P1.1
P1.2
P1.3
VD
D0
P5.0
P5.1
P5.2
P5.3
VO
1A
VO
1B
VSS1
VD
D1
464548 47
P2.0
P3.0
P3.1
P3.2
P2.1
P2.2
P2.3
Pin NO. Symbol X Y Pin NO. Symbol X Y 3 VSS1 -895.3 -2461.7 19 P3.1 883.4 -2113.4 4 VO1B -733.3 -2347.4 20 P3.0 883.4 -2003.4 5 VO1A -613.3 -2347.4 36 P2.3 910.0 2444.4 6 VDD1 -455.7 -2461.7 37 P2.2 800.0 2444.4 7 IRin -193.6 -2448.4 38 P2.1 687.0 2444.4 8 IRout -83.6 -2448.4 39 P2.0 577.0 2444.4 9 P5.3 29.4 -2448.4 40 VDD0 438.1 2444.4 10 P5.2 139.4 -2448.4 41 P1.3 303.1 2444.4 11 P5.1 252.4 -2448.4 42 P1.2 193.1 2444.4 12 P5.0 362.4 -2448.4 43 P1.1 80.1 2444.4 13 P4.3 475.4 -2448.4 44 P1.0 -29.9 2444.4 14 P4.2 585.4 -2448.4 45 RESETB -142.9 2444.4 15 P4.1 698.4 -2448.4 46 OSCI -259.4 2444.4 16 P4.0 808.4 -2448.4 47 OSCO -383.9 2444.4 17 P3.3 921.4 -2448.4 48 VSS0 -523.4 2444.4 18 P3.2 883.4 -2226.4
Chip size : 2080 * 5210 um For PCB layout, IC substrate must be connected to ground. Note : 1. VO1B should be floating or connected to VDD1 when not in use.
2. VSS0 & VSS1 should be connected together with negative power.
12 • Pad Diagrams (V2) 09.30.2005 (These diagrams are subject to change without further notice)
eSB Series
12. eSB320 Pad Diagram
P3.3
P4.0
P4.1
P4.2
P4.3
42 37
9
1011
13 141516 17 1819 20 2223
36
21
41 3839404443
VSS0
OSC
O
OSC
I
IRin
IRout
(0,0)
eSB320
24
26
12
25
RESETB
P1.0
P1.1
P1.2
P1.3
VD
D0
P5.0
P5.1
P5.2
P5.3
VO
1A
VO
1B
VSS1
VD
D1
464548 47
P2.0
P3.0
P3.1
P3.2
P2.1
P2.2
P2.3
Pin NO. Symbol X Y Pin NO. Symbol X Y 3 VSS1 -895.3 -2461.7 19 P3.1 883.4 -2113.4 4 VO1B -733.3 -2347.4 20 P3.0 883.4 -2003.4 5 VO1A -613.3 -2347.4 36 P2.3 910.0 2444.4 6 VDD1 -455.7 -2461.7 37 P2.2 800.0 2444.4 7 IRin -193.6 -2448.4 38 P2.1 687.0 2444.4 8 IRout -83.6 -2448.4 39 P2.0 577.0 2444.4 9 P5.3 29.4 -2448.4 40 VDD0 438.1 2444.4 10 P5.2 139.4 -2448.4 41 P1.3 303.1 2444.4 11 P5.1 252.4 -2448.4 42 P1.2 193.1 2444.4 12 P5.0 362.4 -2448.4 43 P1.1 80.1 2444.4 13 P4.3 475.4 -2448.4 44 P1.0 -29.9 2444.4 14 P4.2 585.4 -2448.4 45 RESETB -142.9 2444.4 15 P4.1 698.4 -2448.4 46 OSCI -259.4 2444.4 16 P4.0 808.4 -2448.4 47 OSCO -383.9 2444.4 17 P3.3 921.4 -2448.4 48 VSS0 -523.4 2444.4 18 P3.2 883.4 -2226.4
Chip size : 2100 * 5250 um For PCB layout, IC substrate must be connected to ground. Note : 1. VO1B should be floating or connected to VDD1 when not in use.
2. VSS0 & VSS1 should be connected together with negative power.
Pad Diagrams (V2) 09.30.2005 • 13 (These diagrams are subject to change without further notice)
eSB Series
13. eSCZ000 Pad Diagram
1
2
VSS6
(0,0)
eSCZ000
100999897 96
VSS1
9594939291908988878685848382818079787776
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
29303132333435363738394041424344454647484950
51
53
52
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75CE1
CE2
RESETB
ADD20
ADD19
ADD16
ADD15
ADD12
ADD7
ADD6
VSS2
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
RD0
RD1
RD2
VSS3
VO1A
VO1B
NC
NC
VDD3
ADD18
ADD17
ADD14
ADD13
ADD8
ADD9
ADD11
ADD10
VD2
CE
RD7
RD6
RD5
RD4
RD3
CE11
CE12
CE13
CE14
IDLE
ENICE
VDD6
OSCO
OSCI
IRout
IRin
VD
D1
VD
D0
P53
P52
P51
P50
P43
P42
P41
P40
P33
P32
P31
P30
P23
P22
P21
P20
P13
P12
P11
P10
VD
D3
VD
D4
BU
SY
NC
NC
NC
NC
NC
NC
NC
NC NC
VSS4
TMW
EB
TMCLK
VD
D5
VSS5
TEST
VSS6
NC
NC
NC
14 • Pad Diagrams (V2) 09.30.2005 (These diagrams are subject to change without further notice)
eSB Series
Pin NO. Symbol X Y Pin NO. Symbol X Y
1 CE1 -1515.0 1463.5 26 NC 2 CE2 -1515.0 1353.5 27 NC 3 RESETB -1515.0 1243.5 28 NC 4 ADD20 -1515.0 1133.5 29 VDD3 -1229.5 -1566.5 5 ADD19 -1515.0 1023.5 30 VDD4 -779.0 -1655.0 6 ADD16 -1515.0 913.5 31 BUSY -669.0 -1655.0 7 ADD15 -1515.0 803.5 32 NC -559.0 -1655.0 8 ADD12 -1515.0 693.5 33 NC -449.0 -1655.0 9 ADD7 -1515.0 583.5 34 NC -339.0 -1655.0 10 ADD6 -1515.0 473.5 35 NC -229.0 -1655.0 11 VSS2 -1515.0 363.5 36 NC -119.0 -1655.0 12 ADD5 -1515.0 253.5 37 NC -9.0 -1655.0 13 ADD4 -1515.0 143.5 38 NC 101.0 -1655.0 14 ADD3 -1515.0 33.5 39 NC 211.0 -1655.0 15 ADD2 -1515.0 -76.5 40 NC 321.0 -1655.0 16 ADD1 -1515.0 -186.5 41 VSS4 431.0 -1655.0 17 ADD0 -1515.0 -296.5 42 NC 541.0 -1655.0 18 RD0 -1515.0 -406.5 43 TMWEB 651.0 -1655.0 19 RD1 -1515.0 -516.5 44 NC 761.0 -1655.0 20 RD2 -1515.0 -626.5 45 TMCLK 871.0 -1655.0 21 VSS3 -1485.5 -937.0 46 NC 981.0 -1655.0 22 VO1A -1372.7 -1086.5 47 VDD5 1091.0 -1655.0 23 VO1B -1372.7 -1206.5 48 VSS5 1201.0 -1655.0 24 NC -1372.7 -1326.5 49 TEST 1311.0 -1655.0 25 NC -1372.7 -1446.5 50 VSS6 1421.0 -1655.0
Pad Diagrams (V2) 09.30.2005 • 15 (These diagrams are subject to change without further notice)
eSB Series
16 • Pad Diagrams (V2) 09.30.2005 (These diagrams are subject to change without further notice)
Pin NO. Symbol X Y Pin NO. Symbol X Y
51 OSCI 1515.0 -1370.0 76 P10 1500.0 1655.0 52 OSCO 1515.0 -1260.0 77 P11 1390.0 1655.0 53 VDD6 1515.0 -1150.0 78 P12 1280.0 1655.0 54 ENICE 1515.0 -1040.0 79 P13 1170.0 1655.0 55 IDLE 1515.0 -930.0 80 P20 1060.0 1655.0 56 CE14 1515.0 -820.0 81 P21 950.0 1655.0 57 CE13 1515.0 -710.0 82 P22 840.0 1655.0 58 CE12 1515.0 -600.0 83 P23 730.0 1655.0 59 CE11 1515.0 -490.0 84 P30 620.0 1655.0 60 RD3 1515.0 -380.0 85 P31 510.0 1655.0 61 RD4 1515.0 -270.0 86 P32 400.0 1655.0 62 RD5 1515.0 -160.0 87 P33 290.0 1655.0 63 RD6 1515.0 -50.0 88 P40 180.0 1655.0 64 RD7 1515.0 60.0 89 P41 70.0 1655.0 65 CE 1515.0 170.0 90 P42 -40.0 1655.0 66 VDD2 1515.0 280.0 91 P43 -150.0 1655.0 67 ADD10 1515.0 390.0 92 P50 -260.0 1655.0 68 ADD11 1515.0 500.0 93 P51 -370.0 1655.0 69 ADD9 1515.0 610.0 94 P52 -480.0 1655.0 70 ADD8 1515.0 720.0 95 P53 -590.0 1655.0 71 ADD13 1515.0 830.0 96 VDD0 -700.0 1655.0 72 ADD14 1515.0 940.0 97 VDD1 -915.0 1655.0 73 ADD17 1515.0 1050.0 98 IRIN -1025.0 1655.0 74 ADD18 1515.0 1160.0 99 IROUT -1135.0 1655.0 75 VSS0 1515.0 1376.5 100 VSS1 -1245.0 1655.0
Chip size : 3250 * 35500 um For PCB layout, IC substrate must be connected to ground. Note : 1. VO1B should be floating or connected to VDD1 when not in use.
2. VSS0 & VSS1 should be connected together with negative power.
