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Presented to NATEA 02/23/10 2/24/10
Copyright 2010 XtremeEDA Corp. - All rights reserved 1
ESL, SystemC and TLM 2.0: Why You Should Care
• David C Black, XtremeEDA Corporation
© 2010 XtremeEDA USA Corporation - Version 1002.1
• Who is Xtreme-EDA?
• ESL definition
• ESL why/motivation
• ESL Language
• SystemC overview 50km
• Organizational Implications
• TLM overview
• TLM 2.0 introduction
• Summary
• Q&A
Agenda
Presented to NATEA 02/23/10 2/24/10
Copyright 2010 XtremeEDA Corp. - All rights reserved 2
© 2010 XtremeEDA USA Corporation - Version 1002.1
ESL Practice
Verification Practice
XtremeEDA: Trusted High Value Expertise & Methodology Boost
Abstraction drives
system level design ! Architectural analysis
! S/W Development
! H/W Implementation
! Verification
A coherent ESL strategy is a must for today’s system design
Complex Product Designs
drive exponentially
complex verification environments. ! Number of features to test
grows exponentially
! Constrained Project resources
! Must be provably correct
Efficient environments
must be designed that can scale
XtremeEDA: Vision
DFT Practice
Complex High Quality
Products. ! Large SoC’s
! Smaller Process Nodes
! ATPG not scalable.
! More rigid quality
requirements.
! Costly factory test times
Today’s designs require more then ATPG
© 2010 XtremeEDA USA Corporation - Version 1002.1 4
• ASIC/FPGA/SoC Design Verification, ESL and DFT services
• World Class Training
– Verification languages and methodology
– Project Management training
• Highly specialized expertise for MIL/AERO companies
– DO-254 requirements
– XtremeEDA USA provides US citizens
• Controlled Good Certified (ITAR equivalent for Canada)
– ITAR (International Traffic in Arms Regulations) in process
• Headquartered in Ottawa, Canada
– XtremeEDA USA in Austin, TX
– www.xtreme-eda.com
Presented to NATEA 02/23/10 2/24/10
Copyright 2010 XtremeEDA Corp. - All rights reserved 3
© 2010 XtremeEDA USA Corporation - Version 1002.1
• XtremeEDA ESL Expertise - Worldwide
• What we do
– Adoption Planning
– Methodology & Flow
– Schedule Acceleration
– Mentors
– Training
– Turnkey SystemC/C++ Modeling
• History
– Consultancy focused on ESL
– Founded 2003 (formerly Eklectically Inc DBA ESLX Inc.)
– Work with OSCI (participate in standards, wrote examples)
– Wrote book, “SystemC: From the Ground Up”
Who is XtremeEDA USA?
5
© 2010 XtremeEDA USA Corporation - Version 1002.1
• DEFINITION: Electronic System-Level design
– Level of abstraction encompassing all aspects of the electronics portion of the system including hardware,
software, and surrounding environment
– More than just electronic hardware
– Functional behavior of digital systems without
implementation details
• An ESL description provides an machine-readable
architectural specification of a system
– Simulation executable
– Potentially sufficient for automated analysis and
transformation
What is ESL?
6
Presented to NATEA 02/23/10 2/24/10
Copyright 2010 XtremeEDA Corp. - All rights reserved 4
© 2010 XtremeEDA USA Corporation - Version 1002.1
• A collection of parts that interact to function purposefully as a whole.
• One man's system is another's sub-system
– System-on-a-chip or system on chip (SoC or SOC) refers to integrating all components of a computer or other electronic system into a single integrated circuit (chip). It may contain digital, analog, mixed-signal, and
often radio-frequency functions – all on one chip.
What is a System?
7
• Embedded systems range from digital watches
and MP3 players, to large stationary installations like traffic lights, factory controllers, or the
systems controlling nuclear power plants. They may contain one or more SoC's.
• An electronic flight instrument system (EFIS) is a flight deck instrument display system with
electronic display technology. It employs multiple embedded systems.
© 2010 XtremeEDA USA Corporation - Version 1002.1
• Practical modern approach to Concurrent Engineering
• Emerging Methodology for developing electronic systems by concurrently using a common system model among architecture, hardware, software, and verification organizations
• Methodology enables reduced schedules, increased productivity, and reduced product risk despite exponentially growing system complexity
Pragmatic Definitions of ESL
8
Presented to NATEA 02/23/10 2/24/10
Copyright 2010 XtremeEDA Corp. - All rights reserved 5
© 2010 XtremeEDA USA Corporation - Version 1002.1
• Systems have become enormously complex
– Today's cell phone: more compute power than yesterday's Cray
– Automobile electronics exceeded all other costs as of 2000
• Large Systems
– Software cannot wait for hardware – needs simulated environment
– Larger designs take to long to simulate at hardware level
– Complexity makes it almost impossible to get sufficient coverage
• Schedules have become shorter
– Market driven environment is moving quickly
– Schedule of software can dwarf hardware development
Why ESL now?
9
© 2010 XtremeEDA USA Corporation - Version 1002.1
Design Complexity
10
Exp
on
en
tia
l L
ine
s o
f C
od
e
A
Be
h
RT
L
Ga
tes
Arc
h
Be
ha
vio
ral
RT
L
Ga
tes
Arc
hit
ectu
ral
Be
ha
vio
ral
RT
L
Ga
tes
Yesterday Now Tomorrow
Unwieldy
Spreadsheet
Impossible
10K
1M
100M
1M
10 M
100M
100
1.5K
8K
100K
Presented to NATEA 02/23/10 2/24/10
Copyright 2010 XtremeEDA Corp. - All rights reserved 6
© 2010 XtremeEDA USA Corporation - Version 1002.1
Algorithm
Disparate Teams:
Architecture Hardware Verification Software
Architectural
Verification
Hardware
Development
Hardware
Verification
Software
Development
System
Integration
ESL Impacts on Schedule – before ESL
11
Longest
© 2010 XtremeEDA USA Corporation - Version 1002.1
Algorithm
Disparate Teams:
Architecture Hardware Verification Software
Architectural
Verification
Hardware
Development
Hardware
Verification
Software
Development
System
Integration
ESL Impacts on Schedule – with ESL
12
Start together
Presented to NATEA 02/23/10 2/24/10
Copyright 2010 XtremeEDA Corp. - All rights reserved 7
© 2010 XtremeEDA USA Corporation - Version 1002.1
• Pay now or pay later
– Under design
• Too slow, not enough memory, not enough processor(s) power
• Insufficient bandwidth
– Over design
• Extra cost to implement
• Competition outbids
• Too much power, slow schedule, overly complex verification
– Fail to design to the right specification
• Doesn't meet real needs
• Doesn't match design requirements
• Insufficient flexibility
• Unable to adapt quickly to changing requirements
What if companies don't adopt ESL?
$
© 2010 XtremeEDA USA Corporation - Version 1002.1
• Architect - Algorithmic Development
• Architect - Performance Modeling
• Software – Early Development
• Verification - Head start
• Implementation - Behavioral Synthesis
Discussed in following slides
ESL Use Cases
Presented to NATEA 02/23/10 2/24/10
Copyright 2010 XtremeEDA Corp. - All rights reserved 8
© 2010 XtremeEDA USA Corporation - Version 1002.1
• Examine feasibility of new designs
– Figure out the best formula
• ESL TLM offers
– Great Performance
– Leverage existing C++ and C libraries
– Leverage open-source Productivity tools
Architect – Algorithmic Development
© 2010 XtremeEDA USA Corporation - Version 1002.1
• Determine if elements are appropriately sized
– Does the design hit the target?
• ESL TLM offers
– TLM 2.0 interface now available
• Simplifies assembly of model
• Off-the-shelf models available from several vendors
– Speed and accuracy are good to great if done correctly
Architect – Performance Modeling
Presented to NATEA 02/23/10 2/24/10
Copyright 2010 XtremeEDA Corp. - All rights reserved 9
© 2010 XtremeEDA USA Corporation - Version 1002.1
• Software Schedule often longer than hardware
– Get a head start to reduce schedule
• ESL TLM offers
– Instruction Set Simulators (ISS) available
– Performance adequate for full software implementation
– Mixed/Accelerated implementations can be very fast
Software – Early Development
© 2010 XtremeEDA USA Corporation - Version 1002.1
• Ensure correct implementation of specification
– Everyone starts as soon as possible
• ESL TLM offers
– Integrates easily into a Verilog/SystemVerilog testbench
– Supports modern verification techniques
• SCV for pseudo-random and constrained stimulus
• STL for scoreboarding
• Dynamic processes allow for temporal assertions
– Used to create original OVM concepts
• Standard verification methodology
Verification - Early Development
Presented to NATEA 02/23/10 2/24/10
Copyright 2010 XtremeEDA Corp. - All rights reserved 10
© 2010 XtremeEDA USA Corporation - Version 1002.1
• Explore more options
– Use a higher level of abstraction to examine more tradeoffs
• ESL TLM offers
– Raise the level of abstraction
• Engineer specifies the macro architecture
• Tools explore the micro architecture
– Quite successful for many companies
• Reduces design time
• Improves QoR
Implementation – Behavioral Synthesis
© 2010 XtremeEDA USA Corporation - Version 1002.1
• No mention of a language to implement ESL to this point
• Would like a language with the following characteristics:
– Standard (IEEE, ISO, Mil-std) and Open
– Common skill in existing work force and new graduates
– Component models from 3rd parties available
– Multi-EDA Vendor support
– Productivity Tools available
– Appropriate Performance
– Fully Support Simulation Concurrency
– Independent refinement of Functionality and Interface
– Interoperates well with Software
ESL Languages
20
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Presented to NATEA 02/23/10 2/24/10
Copyright 2010 XtremeEDA Corp. - All rights reserved 11
© 2010 XtremeEDA USA Corporation - Version 1002.1
ESL and SystemC
• Standard and Open
" Standard IEEE 1666-2005
• Common skill in existing work force and new graduates
" C++ skills commonly taught
• Appropriate Performance
" Designed for Performance
• Multi-EDA Vendor support
" Many EDA vendors
• Productivity Tools available
" Tool Support
• Fully Support Simulation Concurrency
" Support Simulation Concurrency
• Independent refinement of Functionality and Interface
" Supports TLM and independent refinement
• Component models from 3rd parties available
" Models available
# Interoperates well with Software
" Direct execution or ISS
21 on - Version 1002.1
peSoftware
""""""""""""""""""""""DiDiDiDiDiDiDiDiDiDiDiDiDiDiDiDiDiDiDiDiDiDiDiDiDiDiDiDiDiDiDiDirerererererererererererererererererererererererererererererererererererect exe
21
© 2010 XtremeEDA USA Corporation - Version 1002.1
• Who is Xtreme-EDA?
• ESL definition
• ESL why/motivation
• ESL Language
• SystemC overview 50km
• Organizational Implications
• TLM overview
• TLM 2.0 introduction
• Summary
Agenda
Presented to NATEA 02/23/10 2/24/10
Copyright 2010 XtremeEDA Corp. - All rights reserved 12
© 2010 XtremeEDA USA Corporation - Version 1002.1
• A "language" for Electronic System Level modeling (ESL)
• C++ library specification
– Simulator kernel and classes that enable hardware and
software modeling at a variety of abstraction levels.
• A group of methodologies for designing systems that
include software above the RTL level.
What is SystemC?
23 on - Version 1002.1
23
© 2010 XtremeEDA USA Corporation - Version 1002.1
• Performance
– For large systems models, performance is key
• Compatibility with software
– Can easily incorporate C/C++
– Links with lots of other languages
– Directly execute or link to application software
• Multi-paradigm language capabilities
– Functional Programming
– Modular Programming
– Object Oriented Programming
– Generic Programming
• Standard and widely supported
• Freely available (GNU, Visual Studio)
Why C++?
24
Presented to NATEA 02/23/10 2/24/10
Copyright 2010 XtremeEDA Corp. - All rights reserved 13
© 2010 XtremeEDA USA Corporation - Version 1002.1
How does it compare with other HDLs?
Requirements
Algorithm and Architectural
Func & SW Development
Behavioural
SoC Verif.
IP Verif.
RTL
Gates
Transistors
Verilog VHDL
System Verilog
Vera e
PSL
* Modified from DVCon
- Gabe Moretti EDN
Matlab C/C++ Java
© 2010 XtremeEDA USA Corporation - Version 1002.1
• SystemC began as a joint development between UC Irvine, Synopsys, and CoWare/IMEC in 1999
– C/C++ language base
– Cycle based simulator
– Awkward syntax
• Open SystemC Initiative (OSCI) formed in 2000
– Purpose
• coordinate efforts
• ensure industry acceptance
– Non-profit, Membership funded
– www.SystemC.org
SystemC Background
26
Presented to NATEA 02/23/10 2/24/10
Copyright 2010 XtremeEDA Corp. - All rights reserved 14
© 2010 XtremeEDA USA Corporation - Version 1002.1
History of SystemC - Timeline
• SC v0.9 established
• SC v1.0 approved & ESCUG formed
• SC v2.0 announced
• OSCI formed
• SC Verification Library v1.0p1
• NASCUG formed by ESLX
• TLM 1.0 released
• SC v2.1.v1 released
• IEEE 1666-2005 approved
• SC v2.2 released – IEEE compliance
• TLM 2.0 Draft 1 available for Public Review
• SC v2.3 alpha – better process controls
• TLM 2.0 Released!
Sep 1999
Mar 2000
Feb 2001
Jun 2001
Dec 2003
Jun 2004
Apr 2005
Dec 2005
Dec 2005
Jan 2007
Nov 2006
May 2007
Jun 2008
27
ESLX Inc. Feb 2003
SystemC: From the Ground Up
ESLX examples ple
Xtreme-EDA Corp. July 2008
© 2010 XtremeEDA USA Corporation - Version 1002.1
• Time & event abstractions
– Time sequenced operations
• Simulator Kernel provides concurrency
– Hardware and systems are inherently concurrent
– Schedules processes
– Manages events and time
• Modules provide hierarchical design designating
hardware
• Channels provide efficient high-level communications
• Hardware Data Types provide necessary precision
– Bit type, bit-vector type, multi-valued logic type, signed and unsigned integer types and fixed-point types
SystemC classes extend C++
Presented to NATEA 02/23/10 2/24/10
Copyright 2010 XtremeEDA Corp. - All rights reserved 15
© 2010 XtremeEDA USA Corporation - Version 1002.1
SystemC Language Architecture
C++ Language Standard
Core Language Modules
Ports Processes Interfaces Channels
Events & Time Event-driven simulation
Data Types 4-valued Logic type
4-valued Logic Vectors Bits and Bit Vectors
Arbitrary Precision Integers Fixed-point types
C++ user-defined types
Primitive Channels
Signal, Mutex, Semaphore, FIFO, etc.
Layered Libraries Verification Library, etc.
© 2010 XtremeEDA USA Corporation - Version 1002.1
• ARM, AMCC, AMD, AMI Semiconductor, Astute Networks, Broadcom, Canon, Concordia Univ, Ceva, Conexant, Cisco Systems, Dallas Semiconductor, Denali, Element CXI, Epson, Florida Atlantic Univ, Freescale, Fraunhaufer Institute, Fujitsu, HP, Hitachi, IBM, Intel, Infineon Technologies, IDT, Intellon, iVivity, ITRI, Lightfleet Corporation, Lockheed Martin, Marvell, MIPS, Motorola, The Mitre Corporation, Nokia, NEC, NetAffect, Northrop Grumman, Northeastern University, NXP Semiconductor, Oki, Ohio State Univ, Philips, Panasonic, Qualcomm, Samsung, Sandia, Sanyo, Sun Microsystems, SpringSoft Inc., STARC, Tuft University, National Labs, ST Microelectronics, Sony, Texas Instruments, University of Texas, Toshiba, Virginia Tech, Xilinx
Who Uses SystemC?
30
Presented to NATEA 02/23/10 2/24/10
Copyright 2010 XtremeEDA Corp. - All rights reserved 16
© 2010 XtremeEDA USA Corporation - Version 1002.1
EDA Vendors Supporting ESL and SystemC
31
© 2010 XtremeEDA USA Corporation - Version 1002.1
SystemC Books
Presented to NATEA 02/23/10 2/24/10
Copyright 2010 XtremeEDA Corp. - All rights reserved 17
© 2010 XtremeEDA USA Corporation - Version 1002.1
• OSCI - systemc.org
– LWG (Language Working Group) $ IEEE Standards Group 1666
– VWG (Verification Working Group)
– SWG (Synthesis Working Group)
– TWG (Transaction Level Modeling Working Group)
– AMS (Analog Mixed Signal working group)
– CCI (Configuration, Control & Inspection working group)
• Users Groups – European SystemC User’s Group
– North American SystemC User’s Group
– Japan SystemC User's Group
– Latin America SystemC User's Group
– India SystemC User's Group
– Taiwan SystemC User's Group (new)
SystemC Organizations
© 2010 XtremeEDA USA Corporation - Version 1002.1
Organizational Implications of ESL
• ESL cuts across boundaries
– Architectural Groups
– Software Groups
– Hardware Groups
– Verification Groups
• ESL assures – Meeting functional goals
– Achieving performance
– Making schedule
• ESL provides
– Shared language
– Rallying point
– Better understanding of goals
• Inherent parallelism
– Affects resource allocation
– Improves predictability
Presented to NATEA 02/23/10 2/24/10
Copyright 2010 XtremeEDA Corp. - All rights reserved 18
© 2010 XtremeEDA USA Corporation - Version 1002.1
• Who is Xtreme-EDA?
• ESL definition
• ESL why/motivation
• ESL Language
• SystemC overview 50km
• Organizational Implications
• TLM overview
• TLM 2.0 introduction
• Summary
Agenda
© 2010 XtremeEDA USA Corporation - Version 1002.1
• Transaction Level Modeling
– A style of modeling that centers around transactions
– Focused on communications within the architecture
– Modeling level above RTL that does not map directly to
gates
• Characteristics
– Less detailed than usual hardware description
• Simple enough for architectural exploration
– Easier to code
• Less implementation time
– Less details to simulate
• Fast enough to use for software development
What is TLM?
36
Presented to NATEA 02/23/10 2/24/10
Copyright 2010 XtremeEDA Corp. - All rights reserved 19
© 2010 XtremeEDA USA Corporation - Version 1002.1
• An abstract model where both data and control are conveyed (communicated) together (ESL Design & Verification, Bailey)
• An input message to a computer system that must be dealt with as a single unit of work (Oxford American Dictionary)
– transaction across bus may consist of several sub-transactions
• An operation to transfer information between processes
What is a transaction?
37
© 2010 XtremeEDA USA Corporation - Version 1002.1
Hardware vs TLM
38
RTL
Simulate every event
RTL
Functional
Model
Functional
Model
100-100,000 X faster simulation
Fu ti
write(address,data)
Transaction level
– function call
Network
RTL L Pin accurate,
cycle accurate
Presented to NATEA 02/23/10 2/24/10
Copyright 2010 XtremeEDA Corp. - All rights reserved 20
© 2010 XtremeEDA USA Corporation - Version 1002.1
Reasons for using TLM
• Fast enough for software
– Much faster than RTL
– Simulated platform reasonable
– Fidelity to hardware
• Sufficiently accurate
– Represents key architectural components of system
– Start verification early
• Available before hardware
– Software & verification may begin in parallel to hardware
Accelerates schedule 39
Accelerates product release schedule
Verification
Hardware
Software
Architecture
Integration
time
No
longer serial
© 2010 XtremeEDA USA Corporation - Version 1002.1
• Multiple definitions of terminology $ confusing
– Hard to select TLM IP or tools
– Need ability to compare
• Ability to integrate IP easily
– Standard interfaces
– Standard methods of handling timing
– Reduce designer learning curve
• Ability to interoperate different Modeling Styles
– Take advantage of SystemC independent refinement
– Create fast simulation environments by focusing
components
Why Standardize TLM?
40
Presented to NATEA 02/23/10 2/24/10
Copyright 2010 XtremeEDA Corp. - All rights reserved 21
© 2010 XtremeEDA USA Corporation - Version 1002.1
• Defined Use Cases
• Focussed on TLM for Memory Mapped Buses
• Specifies several modelling styles w.r.t timing
• Interoperability tested against use cases
• Generic payload with an extension mechanism
• Avoids need for adapters where possible
TLM 2.0 Characteristics
41
© 2010 XtremeEDA USA Corporation - Version 1002.1
• Algorithm Design
– Feasibility analysis
• System Architecture Design
– Hardware/Software Partitioning
– Performance analysis
• Software Application Development
– Software execution on virtual model of system
– Software performance
• Hardware Functional Verification
– Begin verification before RTL
Typical Use Cases for TLM
42
Presented to NATEA 02/23/10 2/24/10
Copyright 2010 XtremeEDA Corp. - All rights reserved 22
© 2010 XtremeEDA USA Corporation - Version 1002.1
top
Bus
TLM 2.0 Example
Memory
CPU DMA
Video Network
initiator_socket
target_socket
© 2010 XtremeEDA USA Corporation - Version 1002.1
clock
bus_ack
bus_req<0..1>
bus_gnt<0..1>
acknowledge
device 0 request
device 0 grant
addr_data addr data0 data1 data2
Cycle Callable
payload
TLM - Intuitive Example
bus
Transaction
bus->b_transport(payload, annotated_delay)
Request Time Response Time
Presented to NATEA 02/23/10 2/24/10
Copyright 2010 XtremeEDA Corp. - All rights reserved 23
© 2010 XtremeEDA USA Corporation - Version 1002.1
• Who is Xtreme-EDA?
• ESL definition
• ESL why/motivation
• ESL Language
• SystemC overview 50km
• Organizational Implications
• TLM overview
• TLM 2.0 introduction
• Summary
Agenda
•
© 2010 XtremeEDA USA Corporation - Version 1002.1
• Predict & Understand Performance
– Today's systems are too big to guess with spreadsheets
– TLM 2.0 provides well defined timing definitions
• Quickly integrate – Leverage IP
– Developing & integrating models takes time
– TLM 2.0 provides interoperability to reduce this time
• Appropriate speed & accuracy
– Doesn't just happen – guidance is needed
– TLM 2.0 provides guidance & terminology to understand
• Need software earlier
– Software drives schedule – earlier start = shorter schedule
– TLM 2.0 makes it possible to use simulated environment
Why You Care
Presented to NATEA 02/23/10 2/24/10
Copyright 2010 XtremeEDA Corp. - All rights reserved 24
© 2010 XtremeEDA USA Corporation - Version 1002.1
• Mentor your team with Xtreme-EDA consultants
– Jump start strategy and planning
– Technical jump start for all aspects of ESL
– Guide your team towards first time success
• Educate your team with Xtreme-EDA training
– Xtreme-EDA brings groups together – the future depends on this
• Architects, software, hardware, verification
– Xtreme-EDA understands the technical intricacies of TLM 2.0
– Xtreme-EDA experts are aware of the pitfalls to avoid
• Xtreme-EDA experts can quickly provide missing models
– TLM 2.0 IP is only just beginning to become available
– Modeling expertise is special – Xtreme-EDA has the people
How Xtreme-EDA can Help
© 2010 XtremeEDA USA Corporation - Version 1002.1
• Xtreme ESL Expertise Worldwide
• Our services
– Adoption Planning
– Methodology & Flow
– Schedule Acceleration
– Mentors
– Training
– Turnkey SystemC/TLM Modeling
• Contact
– Email: [email protected]
– Phone: 888-467-4609
– Web: http://www.Xtreme-EDA.com
Experience for Hire
48
Presented to NATEA 02/23/10 2/24/10
Copyright 2010 XtremeEDA Corp. - All rights reserved 25
Going Deeper The technical side of SystemC & TLM
• A Brief Look
© 2010 XtremeEDA USA Corporation - Version 1002.1
• SystemC Fundamental Concepts
• SystemC Example
• TLM 2.0 Fundamental Concepts
• TLM 2.0 Example
• Summary
Going Deeper - Agenda
Presented to NATEA 02/23/10 2/24/10
Copyright 2010 XtremeEDA Corp. - All rights reserved 26
© 2010 XtremeEDA USA Corporation - Version 1002.1
• SystemC is C++ Class Library plus methodology
– #include <systemc>
– Library includes simulator kernel
• C++ advantages
– Very efficient and safe it used correctly
– Can (re)use C code with a little effort
– Access to a large body of C++ on the Internet
• Design boundaries maintained using modules & hierarchy
– Modules derived from sc_module class
• Wealth of easy to use data types and containers
– Hardware types
– Software types
SystemC Fundamental Concepts (1 of 2)
© 2010 XtremeEDA USA Corporation - Version 1002.1
• Concurrency modeled using processes
– Register named functions to represent processes
– SC_THREAD and SC_METHOD types
• Synchronization occurs using events
– sc_event::notify()
– wait(sc_event)
– wait(sc_time)
• Communicate with sc_channel's via sc_port/sc_export
– Powerful abstraction using C++ polymorphism
• Adaptors allow mixed levels of abstraction
SystemC Fundamental Concepts (2 of 2)
Presented to NATEA 02/23/10 2/24/10
Copyright 2010 XtremeEDA Corp. - All rights reserved 27
© 2010 XtremeEDA USA Corporation - Version 1002.1
Simple Example – Block diagram
53
sc_main
top
Datagen Mixer Checker
top.cpp
datagen.cpp
datagen.h
mixer.cpp checker.cpp
checker.h
main.cpp
top.h
mixer.h
Mixer
i1
i2 vo
Response checker
vi
Data Generator
d1
d2
Top
c1
c2 c3 c2 d1
c2 c2 d2 vo
© 2010 XtremeEDA USA Corporation - Version 1002.1
top.cpp
datagen.cpp
datagen.h
mixer.cpp checker.cpp
checker.h
main.cpp
top.h
mixer.h
Simple Example – mixer.h
#ifndef _mixer_H_
#define _mixer_H_
SC_MODULE(mixer) {
// Ports
sc_port<sc_fifo_in_if<int> > i1;
sc_port<sc_fifo_in_if<int> > i2;
sc_port<sc_fifo_out_if<int> > vo;
// Process declaration
void mixer_thread();
// Module constructor
SC_CTOR(mixer);
};
#endif
54
Mixer
i1
i2 vo
Response checker
vi
Data Generator
d1
d2
Top
c1
c2 c3 c2 d1
c2 c2 d2 vo
Presented to NATEA 02/23/10 2/24/10
Copyright 2010 XtremeEDA Corp. - All rights reserved 28
© 2010 XtremeEDA USA Corporation - Version 1002.1
top.cpp
datagen.cpp
datagen.h
mixer.cpp checker.cpp
checker.h
main.cpp
top.h
mixer.h
Simple Example - mixer.cpp
#include <systemc>
#include "mixer.h"
// Constructor
SC_HAS_PROCESS(mixer);
mixer::mixer(sc_module_name nm)
: sc_module(nm)
{ // Register processes
SC_THREAD(mixer_thread);
}
// Processes
void mixer::mixer_thread() {
int k1, val1, k2, val2;
while (true) {
k1 = i1->read();
val1 = i1->read();
k2 = i2->read();
val2 = i2->read();
vo->write(k1*val1 + k2*val2);
}
} 55
Mixer
i1
i2 vo
Response checker
vi
Data Generator
d1
d2
Top
c1
c2 c3 c2 d1
c2 c2 d2 vo
© 2010 XtremeEDA USA Corporation - Version 1002.1
• SystemC Fundamental Concepts
• SystemC Example
• TLM 2.0 Fundamental Concepts
• TLM 2.0 Example
• Summary
Agenda
•
Presented to NATEA 02/23/10 2/24/10
Copyright 2010 XtremeEDA Corp. - All rights reserved 29
© 2010 XtremeEDA USA Corporation - Version 1002.1
• TLM standard
– Only specifies the API
– Designed specifically for Memory Mapped Bus modeling
– Describes modeling styles as relates to timing/use of API
• Convenience components part of proof-of-concept kit
– Bundle up port pairs into "sockets" to simplify connectivity
– Support for time warping via Quantum Keeper
– Support for big/little endian conversion
• Presumes models meeting standard will appear
– No conformance or qualification beyond reading the standard
– Specialized modeling expertise to implement
• Not the same as RTL, software or architect skillset
TLM 2.0 Fundamental Concepts
© 2010 XtremeEDA USA Corporation - Version 1002.1
top
bus
TLM 2.0 Example
mem
cpu dma
net
t
t t
vid
t
t
t
initiator_socket
target_socket
t
Presented to NATEA 02/23/10 2/24/10
Copyright 2010 XtremeEDA Corp. - All rights reserved 30
© 2010 XtremeEDA USA Corporation - Version 1002.1
TLM – Sequence Diagram
initiator target get
b_transport(gp,dly=2)
wait(6 ns) gp.data = value dly += 5 ns
b_transport(gp,dly=7)
wait(7 ns)
15 ns
21 ns
28 ns
sc_time
return
© 2010 XtremeEDA USA Corporation - Version 1002.1
• SystemC is a C++ library
– Specified by IEEE-1666-2005
• Proficiency in C++ is essential to effective modeling
– SystemC uses most of the ANSI C++ standard's features
– Object-oriented
• Can get by without C++ if and only if
– Only concerned with block level analysis
– Obtain all models from others
– Use EDA tools to configure, compile, run, analyze
• Mentoring and training pays off
– Fewer false starts
– Effective modeling
Need for Mentoring/Training
e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e
Presented to NATEA 02/23/10 2/24/10
Copyright 2010 XtremeEDA Corp. - All rights reserved 31
© 2010 XtremeEDA USA Corporation - Version 1002.1
• XtremeEDA ESL Expertise Worldwide
– Adoption Planning
– Methodology & Flow
– Schedule Acceleration
– Mentors
– Training
– Turnkey SystemC/TLM Modeling
• Contact
– Email: [email protected]
– Phone: 888-467-4609
– Web: http://www.Xtreme-EDA.com
Experience for Hire
61