Esterel By: Geoff Houston

Britney MendezJon Calhoun

Travis Blanchette

Intro Reactive systems Features of

reactive systems The Language

◦ Syntax◦ examples◦ FSM pro/con◦ compiling diagrams

Compliers◦ Alternative◦ New

Summary Conclusion References

Content

Situation 1 - stop light Situation 2 - airplane flight computer Situation 3 - vending machine Situation 4 – anti-lock breaks

Introduction

What are reactive systems Why we need them

◦ safety◦ efficient◦ quality control

Solutions to the situations

Reactive Systems

Deterministic Formally Verifiable

Features of Reactive systems

1983 Developed by Gérard Berry 1984 First semantics, LISP-based V2 compiler 1988 Better semantics, Efficient V3 compiler 1990 First hardware synthesis to FPGAs (DEC) 1992 BDD-based verification facilities (Dassault) 1995 Causality and cyclic circuits 1997 Sequential optimization 1999 V7 specification started 2001 Esterel Technologies founded 2003 Esterel V7 compiler released 2005 First silicon produced by Esterel V7 2007 Fast code generation, System C backend 2008 IEEE Standardization process started

Timeline

• BNF Definition:• Module :

– module ModuleIdentifier :– InterfaceDeclListopt– Statement– end moduleopt

• Interface Declaration• Type Declarations• Constant Declarations• Function Declarations

– FunctionDecls :• function FunctionDeclList ;

• Procedure Declarations– ProcedureDecls :

• procedure ProcedureDeclList ;

• Signal Declarations• Variable Declarations• Task Declarations• Sensor Declarations• Input Relation

Declarations• Expressions• Statements

Esterel – the language

Reactions Instants or ticks Status of a signal Trace Occurrences

Some definitions

Also called Strong synchrony hypothesis Import: Central to the theory of reactive

systems

Strong synchrony model

• var x := 0 : integer in i end; • Type identifier is either integer or boolean• Execution

– In Parallel with the || operator– Sequentially with the ; operator

• Modules are interfaces and instructions.• Modules are executed in parallel in an

Esterel program.

Some Syntax

A channel on which events occur Two kinds:

◦ Pure – present or absent in an instant, not both◦ Valued – pure signals with an associated value

which only changes on event boundaries

Signals

Await – waits for its occurrence to elapse, then terminates◦ await s

Emit – triggers an event on a signal s in the current instant and terminates instantly◦ emit s◦ emit s (e)

Await/Emit

module simple:input A, B, C;output D, E, F;

loop await A; emit D; await Aend

||every B doemit Fend

||await B; emit E; await C; emit E;

.

Module example

Input/output of module simple

• Halt – fundamental time consumer in Esterel

• Preemptiondo

i1watching otimeout i2 end

• Exception trap E in i1handle E do i2end

Halt/Preemption and exceptions

if e then i1else i2end

present s then i1else i2 end

Conditionals

Basic loop iend do….upto loop….each every…do

Loops

trap HeartAttack in

|| run CheckHeart

exit HeartAttack

handle HeartAttack do run RushToHospitalend trap

abort

when 2 Lap

every Morning do

end every

abort every Step do run Jump || run Breathe end every when 15 Second ; run FullSpeed

loop

each Lap

abort run Slowly when 100 Meter ;

Signal

Error Signal

Process

The Stopwatch – Inputs/Outputs

Start/Stop

Time

Lap/Reset

Image Source: http://www.ewashtenaw.org/government/departments/cmhpsm/provider_information/images/Stopwatch%20for%20PI

The Stopwatch - Code

module STOPWATCH:

input SS, LR, SECOND;output TIME(integer);

signal RESET, LAP, RUN, FROZEN in

The Stopwatch – Start/Stop Code

loopawait SS;do

sustain RUNup to SS

end

||

Sustain RUN translates to

Every TICK do emit RUNend

The Stopwatch – Lap/Reset Code

every LR dopresent RUN then emit LAP

else present FROZENelse emit RESET

endend

end||

The Stopwatch – Frozen Display Code

loopawait LAP;trap T in

sustain FROZEN||

await LAP; exit Tend

end||

The Stopwatch – Counter Codeloop

var second := 0 : integer inemit TIME(second) ;every SECOND do

present RUN thensecond := second + 1

end ;present FROZEN else

emit TIME(second)end

endend

upto RESETend .

Esterel as an FSM - Pros

Faster runtime

If FSM can be found, the program is guaranteed to run.

Esterel as an FSM - Cons

Exponential file size

Long compilation times

Debugging is challenging

2 Signals 4 States3 Signals 8 States4 Signals 16States5 Signals 32 States6 Signals 64Statesn Signals 2n States

Exponential Growth of States

Esterel Compilation Alternatives Intermediate code is generated instead of

an FSM Each instant is broken into a series of steps

Another examplemodule simple:input A, C;output B, E;

every reset do loop await A; emit B; await A; emit Eend

||loopif B emit E; await C; emit Aend

end

RESET

BA

A

B

E

E

C

A

every RESET do loop await A; emit B; if C emit D; pause end|| loop if B emit C; pause endend

s=2

CB

DCB

A21 s

s=1

RESET

s=2

CB

DCB

A21 s

s=1

RESET

t=0 t=1

DCs=2 s=1

RESET

A1 s

B2

B C

t0 1

Esterel

Concurrent Control-Flow

GraphScheduled

CCFGSequential

Control-Flow Graph

Step 1: Translate

Step 2: Schedule

Step 3: Sequentialize

Void foo(){ switch (st) { 0: if (IN=3) st = 5; goto L5; 1: if (RES) st = 3; goto L8; } L5: switch}

C

Step 4: Generate C

A Typical Compiler

Stephen A.Edwards

every RESET do loop await A; emit B; if C emit D; pause end|| loop if B emit C; pause endend

Reset

Step 1: Build Concurrent CFG

Fork

Join

S2

1

S=1S=2

C

B

C

B

D

A

Step 2: Schedule

RESET

S=2S=1

C

s

B

A

C

B

D

21

Add arcs for communication

B

Step 3: Concurrency removed

s=2

CD

C

B

A21 s

s=1

RESETRESET

SB A

1 2

B

A21 s

T=1T=0

B CC

B

T0 1

S=2

C D

s=1S=2

CD

s=1

s=2 CBDCBA 21 s s=1RESET

RESET

S=1

S 21

Step 3: Sequentialize Hardest part: Removing concurrency

Simulate the Concurrent CFG

Main Loop:◦ For each node in scheduled order,

Insert context switch if from different thread

Esterel Compiler Alternatives Smaller filesize and compilation times

◦ 20 min and 3.7mb vs 7s and 80kb

Causality checking is left to runtimepresent A else emit A end

Esterel Compiler Alternatives Introduces several new elements within

processes◦ Program counters◦ Set Calculator◦ Process status

Terminated (0) Halted (1) Waiting (-1)

• 1988: INRIA compiler (G. Berry)• 1999: Synopsys Esterel v5 Compiler (S. Edwards)• 1998: GMD Esterel compiler (A. Poigné, L. Holenderski)• 2001: Xerox TCCP time constraint language (V. Saraswat)• 2001: France Telecom Esterel->C compiler (Weil & Closse)• 2001: Cadence Esterel/C Language = ECL (Lavagno, Sentovich)• 2002: Columbia Esterel v5 Compiler (S. Edwards)• 2002: Kaiserslautern Quartz compiler / verifier (K. Schneider)• 2004: INRIA Esterel->FastC compiler (D. Potop)• 2005: Dassault Systèmes Esterel for PLCs compiler• 2006: Kaiserslautern Averest system (K. Schneider)

Known Compilers

Summary Features – reactive template, concurrency,

signals, Benefits – C files, Concurrency for control

systems, deterministic, finite state lang, implemented in hardware

Suckage - bad for data flow, C files huge, C files inefficient and bulky, Semantic challenges: loop emit E end impossible

Conclusion Proposal for Esterel v7 to make it more

efficient without the hardware. Great with the right hardware. started SCADE

References Prof. Stephen A. Edwards Columbia University,

New York www.cs.columbia.edu/~sedwards The Esterel v5 Language Primer Version 5.21

release 2.0 G´erard Berry Centre de Math´ematiques Appliqu´ees Ecole des Mines and INRIA http://dvlabweb.soe.ucsc.edu/ucsc/esterel/esterel_primer.pdf

An Esterel Compiler for a Synchronus / Reactive Development System by Stephan Edwards

Esterel By: Geoff Houston

Britney MendezJon Calhoun

Travis Blanchette