ETE 2 04 - Digital Electronics

ETE 204 - Digital Electronics

Flip-Flops and Registers

[Lecture:13]Instructor: Sajib RoyLecturer, ETE, ULAB

Flip-Flops

(continued)

Summer 2012 ETE 204 - Digital Electronics 2

SR Flip-Flop● The SR Flip-Flop has three inputs- Clock (Ck) --- denoted by the small arrowhead

- Set (S) and Reset (R)

● Similar to an SR Latch

- S = 1 sets the flip-flop (Q+ = 1)- R = 1 resets the flip-flop (Q+ = 0)

● Like the D Flip-Flop, the Q output of an SR Flip-Floponly changes in response to an active clock edge.

- Positive edge-triggered- Negative edge-triggered

3Summer 2012 ETE 204 - Digital Electronics

SR Flip-FlopS R Q Q+

0 00 00 10 11 01 0

0 01 10 01 00 11 1

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Q+ = Qstore

Q+ = 0reset

Q+ = 1set

positive edge-triggeredSR Flip-Flop

1 1 0 not1 1 1 allowed

State change occursafter active Clock edge


SR Flip-Flop (master-slave)SR Latches

Enabled on opposite levels of the clock


SR Flip-Flop: Timing Diagram


JK Flip-Flop● The JK Flip-Flop has three inputs- Clock (Ck) --- denoted by the small arrowhead

- J and K

● Similar to the SR Flip-Flop- J corresponds to S: J = 1 → Q+ = 1

– K corresponds to R: K = 1 → Q+ = 0

● Different from the SR Flip-Flop in that the inputcombination J = 1, K = 1 is allowed.

- J = K = 1 causes the Q output to toggle after anactive clock edge.


JK Flip-Flop

}}}}

Q+ = Qstore

Q+ = 0reset

Q+ = 1set Characteristic Equation:

Q+ = J.Q' + K'.QQ+ = Q'toggle


JK Flip-Flop (master-slave)SR Latches

Enabled on opposite levels of the clock


JK Flip-Flop: Timing Diagram


T Flip-Flop

● The Toggle (T) Flip-Flop has two inputs- Clock (Ck) --- denoted by the small arrowhead

- Toggle (T)

● The T input controls the state change- when T = 0, the state does not change (Q+ = Q)- when T = 1, the state changes following an active

clock edge (Q + = Q')● T Flip-Flops are often used in the design of counters.


T Flip-Flop

Characteristic Equation:

Q+ = T.Q' + T'.Q = T xor Q


T Flip-Flop: Timing Diagram


Building a T Flip-Flop


Asynchronous Control Signals


Asynchronous Control Signals:Timing Diagram


D FF with Clock Enable


Registers


Registers

Several D flip-flops may be grouped together with a commonclock to form a register. Because each flip-flop can store onebit of information, a register with n D flip-flops can store n bitsof information.

A load signal can be ANDed with the clock to enable anddisable loading the registers.

A better approach is to use registers with clock enables ifthey are available.


Register: 4 bits


Data Transfer between Registers

● Data transfer between registers is a commonoperation in computer (i.e. digital) systems.● Multiple registers can be interconnected usingtri-state buffers.● Data can be transferred between two registersby enabling the proper tri-state buffer.


Data Transfer between Registers


Register with Tri-state Output


Data Transfer using Tri-state Bus


Shift Register

A shift register is a register in which binary data can be storedand shifted either left or right. The data is shifted according tothe applied shift signal; often there is a left shift signal and aright shift signal.

A shift register must be constructed using flip-flops (i.e. edge-triggered devices); it cannot be constructed using latches orgated-latches (i.e. level-sensitive devices).


Shift Register: 4 bits


Shift Register (4 bits): Timing Diagram


8-bit SI SO Shift Register


4-bit PIPO Shift Register


4-bit PI PO Shift Register: Operation


Parallel Adder with Accumulator


Parallel Adder with Accumulator

In computer circuits, it is frequently desirable to store onenumber in a register (called an accumulator) and add asecond number to it, leaving the result stored in the register.


n-bit Parallel Adder with Accumulator


Loading the Accumulator

Before addition in the previous circuit can take place, theaccumulator must be loaded with X. This can beaccomplished in several ways. The easiest way is to firstclear the accumulator using the asynchronous clear inputson the flip-flops, and then put the X data on the Y inputs tothe adder and add the accumulator in the normal way.

Alternatively, we could add multiplexers at the accumulatorinputs so that we could select either the Y input data or theadder output to load into the accumulator.


Adder Cell with Multiplexer


Questions?


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ETE 2 04 - Digital Electronics