Eunil Won/Korea U1 Vertex/Tracker summary Jul-07-2005 Eunil Won/Korea University

Eunil Won/Korea U 1

Vertex/Tracker summary

Jul-07-2005Eunil Won/Korea University

Eunil Won/Korea U 2

Vertex/Tracking Summary

• Probably I am not the right person to summarize...

• There were 5 talks during the workshop - 1 vertex, 2 TPC, 2 Silicon tracking R&D status of FPCCD vertex detector GEM TPC beam test result Micromegas TPC beam test result Silicon tracking for ILC (for SiLC) DSSD R&D Status

first (serious) beam test results with B on

Eunil Won/Korea U 3

Fine Pixel CCD (FPCCD)by Y. Sugimoto (KEK)

• Accumulate hit signals for one train and read out between trains (Other options read out 20 times per train)

• Fine pixel of ~5m (x20 more pixels than “standard” pixels) to keep low pixel occupancy

• Fully depleted epitaxial layer to minimize the number of hit pixels due to charge spread by diffusion

• Two layers in proximity make a doublet (super layer) to minimize the wrong-tracking probability due to multiple scattering

• Tracking capability with single layer using cluster shape can help background rejection

• Three doublets (6 CCD layers) make the detector• Operation at low temperature to keep dark current

negligible (r.o. cycle=200ms)

Eunil Won/Korea U 4

Baseline design

3 super-layers (three doublets)

- 6 single layers grouped in three radial positions - R = 20,22,39,41,58,60 mm - thickness = 80 m/layer - position resolution = 2 m

Eunil Won/Korea U 5

Tracking efficiency

cos

p mis d=10mm, =40/mm2

d=2mm, =40/mm2

d=10mm, =2/mm2

Mis-identification Probability (p=1 GeV/c,tSi=50m)

Expected hit density 40/mm2/train (TESLA) 20/mm2/train (Nominal) 15/mm2/train (LowQ)

at R=20 mm, B=3 T

Double structure helps in reducing mis-identification probability !

: background hit density

Eunil Won/Korea U 6

Impact parameter resolution

p=1, 3, 5, 10, 20, 50, 100 GeV/c

T. Nagamine

Old standard conf.

R=24,36,48,60 mm t = 330 m/layer = 4 m

FPCCD configuration

R= 20, 22, 39, 41, 58, 60 mm t = 80 m/layer = 2 m

Eunil Won/Korea U 7

Lorentz angle• Lorentz angle in depleted-

layer– tan=nB

n: electron mobility

– Carrier velocity saturates at high E field:

n =0.07 m2/Vs

@T=300K, E=1x104V/cm n =0.045 m2/Vs

@T=300K, E=2x104V/cm

– Small angle can be cancelled by tilting the wafer

• May not be a serious problem– Number of hit pixels does not

increase so much

B=3T B=5T

E=1x104V/cm

=12deg =19deg

E=2x104V/cm

=7.7deg

=13deg

Eunil Won/Korea U 8

Lorentz angle• Calculation of E-field in epi-layer

– Tools • FEMLAB (COMSOL in Japan) 3.1• Solve Poisson equation by finite element analysis

(FEA)– Parameters

• Material is assumed fully depleted (No free charge)• n-layer: ND=1x1016/cm3=1.6x103 C/m3

• Epi-layer: NA=1x1013/cm3=-1.6 C/m3

• VG=4 V• tSiO2=100 nm• tn=1 m• tepi=15 m

Eunil Won/Korea U 9

Lorentz angle

– Almost constant E-field of ~104V/cm in epi-layer can be achieved

– E-field in epi-layer depends on gate voltage• Higher (positive) gate voltage gives higher E-field• Positive gate voltage should be applied during train crossing

in order to get saturated carrier velocity and less Lorentz angle (Inverted (MPP) mode can be maintained for ~1ms)

– The Lorentz angle of 12 degrees is expected at B=3T

• Result of E-field calculation - Summary

Ele

ctri

c Pote

nti

al

Eunil Won/Korea U 10

TPC reports (two talks)• In the TPC R&D, one of major issues is the readout scheme • There are three readout schemes for LC-TPC in the market

• “Ultimate” MWPC : (well established fall back option)1 mm thin gap between anode-wires to cathode-pad2 mm small pitched anode-wires

• Gas Electron Multiplier (GEM) Narrow pad response function & fast signal (t~ 20ns) only electrons are collected by the readout structure High flexibility in the geometry of the readout pads

• Micro Mesh Gaseous Structure (MicroMEGAS) Micromesh supported by 50-100μm - high insulating pillars Direct detection of avalanche electrons

K. Ikematsu (DESY)

H.Kuroiwa (Hiroshima Univ.)

Beam test on Apr 05 (KEK)

Beam test on Jun 05 (KEK)


GEM


GEM


GEM


GEM


GEM


GEM


GEM


GEM


GEM


Micromegas

• Micromesh supported by 50-100μm - high insulating pillars

• Multiplication takes place between the anode and the mesh

• One stage• Direct detection of avalanche

electrons– Small E×B effect– Fast signals– Self-suppression of positive ion

feedback(ions return to the grid)

– Better spatial resolution– No wire angular effect

50μm

S1

S2

Micromegas


TPC

• Length of FC : 26 cm• Pad

– 2×6 mm, 0.3mm gap– 32 pads×12 pad rows ⇒ 384 readout channels– Non-staggered– Pad plane : 10×10cm

• Readout– ALEPH TPC electronics 24 amplifiers, 16 channels each 500ns shaping time, charge

sensitive sampled every 80 ns digitized by 6 TPDs

Micromegas


X Resolution as a function of Z

cmmMagCd /469)(

cmmMagCd /285)(

cmmMagCd /193)(

Cd fixed for each B

12/3.2 mm

Row6 + Row7Cd = Cd(PRF)

Preliminary resultsPreliminary results

Micromegas


Z Resolution as a function of Z

• σz ⋍ 500μm at 0.5T

B = 0T

B = 1T

B = 0.5T

Unlike σX, σZ has no significant B-dependence

Preliminary resultsPreliminary results

Micromegas


Summary

• To measure Micromegas TPC performance– We did the beam test at KEK-PS π2 beam

line using 4GeV neg. pions in magnetic field

– Micromegas in TPC worked stably Measured diffusion constants are

consistent with Mag. simulation σx ⋍ 200μm , σz ⋍ 800μm at 1T

– But these results are still very preliminary

Micromegas


Comparison btw GEM and MicroMegasby me...

Readout MWPC GEM MicroMEGASgas TDR TDR P5 Ar +

isobutane (95:5)

PR(0) 1.39 mm (1T)

423 m (1T)

506 m (1T)

800 m(*) (1T)

CD 208 m/cm1/2

169 m/cm1/

2

188 m/cm1/2

Z < 500 m @ 260 mm

< 400 m @ 260 mm

~800 m @ 260 mm

(*) see the figure

2 track resolution

track-cluster matching

It may not be fair comparison as MicroMEGAS beam test finished just before (June)


SiLC (Silicon tracking for the International Linear Collider)

http://silc.in2p3.fr

H.J.Kim (KyungPook National U.)

on behalf of the SILC R&D Collaboration(major transpariencies from Aurore Savoy-

Navarro)

SiLCby H.J. Kim


First Prototype on Si strips of different First Prototype on Si strips of different lengthlength

VA64_hdrTsh=3.7µs

28cm x N=1,4 Built by Geneva U., ETH Zurich & Pariswith AMS technique

Courtesy G.Ambrosi(Perrugia)

‘’Serpentine technique’’

recto/verso

SiLC


Signal over noise as a function of strip length

Signal spectrum is summed over a cluster after pedestal and common mode subtraction.

The radioactive source is aSr90-Y90 beta source.

The S/N measurements were achievedon variable length strips with the prototype

at Paris test bench

sensorto be measured

Results see next slide

SiLC


Results on S/N Results on S/N Collaboration Paris-Prague New

L=28cm, S/N(MPV)=2020or S/N(Mean)=30

L=56cm, S/N(MPV)=12or S/N(Mean)=18

Cluster size~2

Noise vs capa

Next steps: Change detector & FE prototypesgo to test beam

SiLC


Some other S/N measurements and/or Some other S/N measurements and/or computationscomputations

Nomad experiment: results from beam tests on S/N with same sensors and VA1 FE chips

These results and the ones we have obtained are confirmingthat 30 cm long strips have S/N greater than 20, and 60 cm long strips have S/N greater than 10.

Nota bene: These results are of course dependent of the detector prototype and the associated F.E.E.

Curve computed with the

known parametersof VA_64hdr

SiLC


2) Development of fabrication line for new 2) Development of fabrication line for new sensorssensors

Several Institutions in SILC(also Helsinki U.) are developing new

sensor research lines Such facilities are very usefull for developing& testing new ideas and transfer to Industry.

For large production, high quality and reliability: HAMAMATSU Monopoly

Ex1: 5’’ DSSD fab. line in Korean U.Ex2: rad hard sensor techno at IMB-CNM

J.Lee’s talk

SiLC


R&D on ElectronicsThe Si tracking system: a few 100m2, a few 106 stripsEvents tagged every bunch (300ns) during the overall train (1 ms)Data taking/pre-processing ~ 200 msOccupancy: < a few %

Goals:Goals:Low noise preamplifiers

Shaping time (from 0.5 to 5 µs,depending the strip length)

Analogue samplingHighly shared ADC

Digitization @ sparsification Very low power dissipation

Power cyclingCompact and transparent

First LPNHE prototypeFirst LPNHE prototypefulfills most of these fulfills most of these

goalsgoals

NEW!!NEW!!

SiLC


Two designsTwo designs

SCIPP-UCSC: Double-comparator discrimination system

Improve spatial resolution (25%) Next foundry: May 9.

LPNHE-Paris:Analogue sampling+A/D,

including sparsification on sums of 3 adjacent strips.

Deep sub micron CMOS techno.First chip successfully submitted

and now under testNext version: in progress

SiLC


LPNHE chip: layout results & LPNHE chip: layout results & teststests

3 mm

1.6

mm

Shaper: simu vs measurement

the layout: 16 +1 ch.(Nov 04) the chip (Feb 05) the test board

VERY ENCOURAGING FIRST RESULTSVERY ENCOURAGING FIRST RESULTS

SiLC


DSSD’s from Latest Fab outP-side IV

CV

P-side Guard Ring ~ 1uA/sensor @100VAll P-strips ~ 8-50nA/strip @100VNo extremely Leaky P-strips

Full Depletion Voltage ~100VOperation Voltage ~120V

DSSD by J. Lee


S/N of DSSD 32ch pattern (bulk signal)

Signal mean = 504.3Pedestal mean = 108.6Pedestal sigma = 15.9S/N = 24.9

Readout system (pad) with VA1 being

prepared

DSSD


Vertex/Tracking Summary

R&D status of FPCCD vertex detector - Doublet option studied - Lorentz angle : 12o @ 3T

GEM TPC beam test resultMicromegas TPC beam test result

Silicon tracking for ILC (for SiLC) - first prototype on various length Si detectors - readout R&D ongoing

DSSD R&D Status - latest fab. result promising - hybrid readout in progress

both results are very promising

Documents

Eunil Won/Korea U1 Vertex/Tracker summary Jul-07-2005 Eunil Won/Korea University