INFORMATION AND COMMUNICATION TECHNOLOGIES

COORDINATION AND SUPPORT ACTION

EUROSOI+

European Platform for Low-Power Applications on Silicon-On-Insulator Technology

Grant Agreement nº 216373

D3.4 Second upgraded version of the inventory of available training material

Due date of deliverable: 30-06-2010 Actual submission date: 30-06-2010

Start date of project: 01-01-2008 Duration: 42 months

Project coordinator: Prof. Francisco Gámiz, UGR Project coordinator organisation: University of Granada, Spain Rev.1

Table of contents

Project co-funded by the European Commission within the Seventh Framework Programme (FP7) Dissemination Level

PU Public X PP Restricted to other programme participants (including the Commission Services) RE Restricted to a group specified by the consortium (including the Commission Services) CO Confidential, only for members of the consortium (including the Commission Services)

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1. Introduction ......................................................................................... 3

2. Books

a) General Textbooks on SOI ....................................................... 4 b) Books Focused on a particular SOI topic .............................. 6

3. Short Courses

a) EUROSOI 2005, Granada, Spain ........................................... 12 b) EUROSOI 2006, Grenoble, France ........................................ 13 c) EUROSOI 2007, Leuven, Belgium ......................................... 14 d) EUROSOI 2008, Cork, Ireland ................................................ 15 e) Tutorial “SOI for analog, digital and RF SOCs and

Microsystems applications” May 15-16, 2008, IMEC, Leuven, Belgium ............................. 16

f) First FDSOI tutorial of the Thematic Network on SOI technology, devices and circuits. November 20008, Grenoble, France ...................................... 17

g) EUROSOI 2009, Goteborg, Sweden ...................................... 18 h) MIGAS '09 - SOI concepts: from materials to devices and

applications, June 2009, Autrans, France ............................ 19 i) Workshop: "FD SOI architecture, technology platform for

Low Power applications for 22nm and beyond October 2009, Leuven, Belgium ............................................ 20

j) Tutorial "Fully Depleted SOI", Baltimore, USA .................... 21 k) EUROSOI 2010, Grenoble, France ........................................ 22 l) Tutorial "Fully Depleted SOI", September 2010

University of Tokyo, Japan .................................................... 23 m) Tutorial: “Silicon on Insulator: Materials to Circuit Design”

September 2010, Seville, Spain ............................................. 25 n) Workshop: "Fully Depleted SOI" December 2010

San Francisco, USA .............................................................. 26 o) EUROSOI 2011, Granada, Spain ............................................ 27 p) Workshop: "Fully Depleted SOI", April 2011

Hsinchu, Taiwan .................................................................... 28

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1. Introduction As one of the aims of the network, during these months we have performed the elaboration of an inventory of the SOI related training material available among the different partners. To this end, several announcements were published on the website and in the monthly EUROSOI Newsletter requesting the participation not only of the members of the network but also of other members from the international SOI community. We regard this task as very useful for our community, especially for the youngest in the field. A selection of this material is available to all partners through the website. The creation of new didactic materials will be a concern during the whole life of the network.

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2. Books. General Textbooks on SOI Silicon-on-insulator: its technology and applications Furukawa, S. 1985; 295 p., Hardcover KTK Scientific Publishers / Kluwer Academic Publishers. ISBN: 978-9-0277-1940-9 Table of contents 1. Preface 2. Laser and Electron-Beam Recrystallization 3. Zone Melting Recrystallization 4. Solid Phase Epitaxy 5. Characterization and Device Applications Index Electrical Characterization of Silicon-on-Insulator Materials and Devices Cristoloveanu, Sorin, Li, Sheng 1995, 400 p., Hardcover Kluwer/Springer ISBN: 978-0-7923-9548-5 Table of contents 1. Introduction 2. Methods of Forming SOI Wafers 3. SOI Devices 4. Wafer Screening Techniques 5. Transport Measurements 6. SUS Capacitor Based Characterization Techniques 7. Diode Measurements 8. Transistor Characteristics 9. Transistor Based Characterization Techniques 10. Monitoring the Transistor Degradation Index.

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CMOS VLSI Engineering: Silicon on Insulator Kuo, James B., Ker-Wei Su 1998 460pp, Hardcover Springer, ISBN 978-0-7923-8272-0 Table of contents

1. Introduction. 2. SOI CMOS Technology. 3. SOI CMOS Circuits. 4. SOI CMOS Devices – Basic. 5. SOI CMOS Devices - Advanced. 6. SOI-Technology ST-SPICE. 7. Special-Purpose SOI Index.

Silicon-on-Insulator Technology: Materials to VLSI Colinge, J.-P. 3rd ed., 2004, 384 p., Hardcover Kluwer/Springer ISBN: 978-1-4020-7773-9 Table of contents 1. Introduction 2. SOI Materials 3. SOI Materials Characterization 4. SOI CMOS Technology 5. The SOI MOSFET 6. Other SOI Devices 7. The SOI MOSFET in a Harsh Environment 8. SOI Circuits. Index

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Books focused on a particular SOI topic Physical and Technical Problems of SOI Structures and Devices Colinge, J.-P.; Lysenko, Vladimir S.; Nazarov, Alexei N. 1995, 300p Hardcover Springer, ISBN 978-0-7923-3600-6 SOI Circuit Design Concepts Bernstein, Kerry, Rohrer, Norman J. 2000, 240 p., Hardcover Kluwer/Springer ISBN: 0-7923-7762-1 Table of contents 1. The Time for SOI 2. SOI Device Structures 3. SOI Device Electrical Properties 4. Static Circuit Design Response 5. Dynamic Circuit Design Considerations 6. SRAM Cache Design Considerations 7. Specialized Function Circuits in SOI 8. Global Chip Design Considerations 9. Future Opportunities in SOI. Low-Voltage Circuits Kuo, Shih-Chia Lin 2001, 424pp., Hardcover Wiley, John & Sons, Incorporated ISBN: 0-4714-1777-7 Table of Contents Preface Acknowledgments 1. Introduction 2. SOI CMOS Devices - Part I 3. SOI CMOS Devices - Part II 4. Fundamentals of SOI CMOS Circuits 5. SOI CMOS Digital Circuits 6. SOI CMOS Analog Circuits 7. PD SOI-Technology SPICE Models Index

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Silicon Wafer Bonding Technology for VLSI and Mems Applications Subramanian S. Iyer (Editor), A. J. Auberton-Herve (Editor), Andre J. Auberton-Herve (Editor) 2001, 149pp, Hardcover Institution of Engineering and Technology (IET) ISBN: 0852960395 Table of Contents Dedication Editors Authors Abbreviations Introduction and overview 1. Principles of wafer bonding 2. Bond, grind-back and polish SOI 3. Smart Cut: the technology used for high volume SOI wafer production 4. ELTRAN (SOI-Epi wafer) technology 5. Wafer characterization 6. Advanced applications of wafer bonding A 1. A manufacturing process for silicon-on-silicon wafer bonding A 2. Glossary A 3. Comparison of bonded wafer technologies A 4. Further reading and websites Subject index SOI Design: Analog, Memory and Digital Techniques Marshall, Andrew, Natarajan, Sreedhar 2002, 416 p., Hardcover Kluwer/Springer ISBN: 0-7923-7640-4 Table of contents 1. Overview 2. SOI Materials 3. Components 4. SOI Modeling 5. Layout for SOI 6. Static SOI Design 7. Dynamic SOI Design 8. SOI SRAMs 9. SOI DRAMs 10. SOI Analog Design 11. Global Design Issues 12. Low Power Design 13. SOI in Development Appendix 1: Internet Sites (issue 1.0) Appendix 2: Trade Mark / Technology Information (issue 1.0).

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Fully-Depleted SOI CMOS Circuits and Technology for Ultralow-Power Applications Sakurai, Takayasu, Matsuzawa, Akira, Douseki, Takakuni 2006, XV, 411 p., Hardcover Kluwer/Springer ISBN: 0-387-29217-9 Table of contents 1. Introduction 2. FD-SOI Device and Process Technologies 3. Ultralow-Power Circuit Design with FD-SOI Devices 4. 0.5-V MTCMOS/SOI Digital Circuits 5. 0.5-1V MTCMOS/SOI Analog/RF Circuits 6. SPICE Model for SOI MOSFETs 7. Applications 8. Prospects for FD-SOI Technology Ultra-Low Voltage Nano-Scale Memories Kiyoo Itoh, Hitoshi Tanaka, Masashi Horiguchi 2007, 346p, Hardcover Springer-Verlag ISBN: 0-3873-3398-3 Nanoscaled Semiconductor-On-Insulator Structures and Devices A. N. Nazarov, V. S. Lysenko, S. Hall 2007, Paperback, 384pp Springer-Verlag ISBN: 1-4020-6379-2 Table of contents Introduction Nanoscaled SOI Material and Device Technologies Physics of Novel Nanoscaled SemOI Devices Reliability and Characterization of Nanoscaled SOI Devices Theory and Modeling of Nanoscaled Devices Authors Index

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FinFETs and Other Multi-Gate Transistors Colinge, J.-P. (Ed.) 2008, XVI, 340 p., Hardcover Springer ISBN: 978-0-387-71751-7 Table of contents 1. The SOI MOSFET: From Single Gate to Multigate 2. Multigate MOSFET Technology 3. BSIM-CMG: A Compact Model for Multi-Gate Transistors 4. Physics of the Multigate MOS System 5. Mobility in Multigate MOSFETs 6. Radiation Effects in Advanced Single- and Multi-Gate SOI MOSFETs 7. Multi-Gate MOSFET Circuit Design Index Progress in SOI Structures and Devices Operating at Extreme Conditions Francis Balestra, Vladimir S. Lysenko, Alexei N. Nazarov 2008 Hardcover, 364pp Springer 978-1-4020-0575-6 Micromachined Thin-Film Sensors For Soi-Cmos Co-Integration J. Laconte, D. Flandre, Jean-Pierre Raskin, D. Flandre, J. P. Raskin 2009 Hardcover, 308pp Springer ISBN: 0-3872-8842-2 Table of Contents I Introduction : context and motivations II Techniques and materials 1 Silicon bulk micromachining with TMAH 2 Thin dielectric films stress extraction III Microsensors 1 Low power microhotplate as basic cell 2 Microheater based flow sensor 3 Gas sensors on microhotplate 4 SOI-CMOS compatibility validation IV Conclusions and outlook App. A (100) silicon crystallography App. B About interferometry ... App. C About reflectometry ...

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Simulation, Fabrication And Characterization Of Advanced MOSFETs: Graded-Channel and Multiple-Gate Devices in SOI Technology for Analog and RF Applications. Tsung Ming Chung 2009 Paperback, 268pp VDM Verlag ISBN: 978-3-6391-4600-4

Variation Aware Analog And Mixed-Signal Circuit Design In Emerging Multi-Gate Cmos Technologies, Vol. 28 Michael Fulde 2010 Hardcover, 140pp Springer Verlag GmbH ISBN: 9-0481-3279-7 Table of Contents 1. Introduction 2. Analog Properties of Multi-Gate MOSFETs 3. High-k Related Design Issues 4. Multi-Gate Related Design Aspects 5. Multi-Gate Tunneling FETs 6. Conclusions and Outlook Symbols and Abbreviations References Semiconductor-On-Insulator Materials for Nanoelectronics Applications Nazarov, A.; Colinge, J.-P.; Balestra, F.; Raskin, J.-P.; Gamiz, F.; Lysenko, V.S. 2011 Hardcover, 400pp Springer Verlag GmbH ISBN: 978-3-642-15867-4 Table of Contents Part I. New Semiconductor-On-Insulator Materials 1. Germanium Processing 2. Low-Temperature Fabrication of Germanium-on-Insulator Using Remote

Plasma Activation Bonding and Hydrogen Exfoliation 3. Engineering Pseudosubstrates with Porous Silicon Technology 4. Confined and Guided Vapor–Liquid–Solid Catalytic Growth of Silicon

Nanoribbons: From Nanowires to Structured Silicon-on-Insulator Layers SOI 5. CMOS: A Mature and Still Improving Technology for RF Applications.

Part II. Physics of Modern SemOI Devices 6. Silicon-based Devices and Materials for Nanoscale FETs 7. FinFETs and Their Futures 8. Ultrathin Body Silicon on Insulator 9. Transistors for 22 nm Node and Beyond

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10. Ultrathin n-Channel and p-Channel SOI MOSFETs 11. Junctionless Transistors: Physics and Properties 12. Gate Modulated Resonant Tunneling Transistor (RT-FET): Performance

Investigation of a Steep Slope, High On-Current Device Through 3D Non-Equilibrium Green Function Simulations

13. Ohmic and Schottky Contact CNTFET: Transport Properties and Device Performance Using Semi-classical and Quantum Particle Simulation

14. Quantum Simulation of Silicon-Nanowire FETs 15. Single Dopant and Single Electron Effects in CMOS Devices Part III. Diagnostics of the SOI Devices 16. SOI MOSFET Transconductance Behavior from Micro to Nano Era 17. Investigation of Tri-Gate FinFETs by Noise Methods 18. Mobility Characterization in Advanced FD-SOI CMOS Device 19. Special Features of the Back-Gate Effects in Ultra-Thin Body SOI MOSFETs

Part IV. Sensors and MEMS on Memory SOI 20. SOI Nanowire Transistors for Femtomole Electronic Detectors of Single

Particles and Molecules in Bioliquids and Gases 21. Sensing and MEMS Devices in Thin-Film SOI MOS Technology 22. Floating-Body SOI Memory: The Scaling Tournament Part V. Afterword 23. A Selection of SOI Puzzles and Tentative Answers Index

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6. Short Courses EUROSOI Granada, Spain 19/01/2005 • SOI Microprocessors (Dr. Ghavam Shahidi, IBM) • Ultimate SOI Devices (Prof. Sorin Cristoloveanu, IMEP) • SOI market and applications (Dr. Pierre Delatte, CISSOID) • Partially Depleted SOI design for low power applications (Dr. Philippe Flatresse, STMicroelectronics) • Simulation of SOI devices (Prof. F. Gámiz, UGR) • Recent advances in SOI materials (Dr. Bruno Ghyselen, SOITEC) • SOI Technology for high performance low power microprocessors (Dr. Asanga Perera, Freescale) Available at http://www.eurosoi.org/tutorials.asp

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EUROSOI Grenoble, France 08/03/2006 • Designing Around SOI (Dr. Bill Redman-White, Univ. Southampton & Philips) • Characterization and Simulation Issues for SOI Devices (Prof. David Esseni, Univ. Udine) • Industrial SOI Technologies & Applications (Dr. Piet Wessels, Philips) • SOI Materials Zoo (from SOS and ZMR to Unibond) (Dr. Hubert Moriceau, LETI) • Multiple Gates and Strained Films for SOI MOSFETs: from Technology to Characterization and Applications (Dr. Anne Vandooren, Freescale) • Non-CMOS Applications for SOI (Prof. Neil Mitchell, Queens Univ. Belfast) Available at http://www.eurosoi.org/tutorials.asp

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EUROSOI Leuven, Belgium 24/01/2007 • Wideband characterization of SOI materials and devices (Prof. J.P. Raskin) • Trends in SOI technologies (Dr. O. Faynot, CEA-LETI) • Quantum Wire Effects in Trigate SOI MOSFETs (Prof. J.P. Colinge, Tyndall) • Low-frequency Noise in SOI (Dr. E. Simoen, IMEC) • SOI Materials and Process (Dr. C. Girard, SOITEC) • SOI for High temperature Electronics: from Technology to Circuit Applications (Dr. Pierre Delatte, CISSOID) Available at http://www.eurosoi.org/tutorials.asp

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EUROSOI Tyndall, Ireland 23/01/2008 • The SOI MOSFET: from Single Gate to Multigate (Prof. Jean-Pierre Colinge, Tyndall) • Physics of the Multigate MOS System (Prof. Bogdan Majkusiak, Warsaw University of Technology) • Mobility in Multigate MOSFETs (Prof. Francisco Gamiz, University of Granada) • Multigate MOSFET Technology (Dr. Malgorzata Jurczak, IMEC) • Radiation Effects in Advanced Single- and Multi-Gate SOI MOSFETs (Dr. Véronique Ferlet-Cavrois, CEA) • Multigate MOSFET Circuit Design (Dr. Gerhard Knoblinger, Infineon) Available at http://www.eurosoi.org/tutorials.asp

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Tutorial “SOI for analog, digital and RF SOCs and Microsystems applications” IMEC Belgium; (15-16 May 2008) Course Contents: Silicon-on-Insulator (SOI) technology is no longer a lab curiosity for the future, but a mature industrial choice for present applications. Major semiconductor companies have already developed commercial successful SOI products and processes worldwide, in particular for the logic sector on one hand (i.e. the Cell microprocessor for gaming platforms) and for smart sensors or MEMS on the other hand. This two-day course will offer a large perspective on the opportunities which SOI opens in the field of low-voltage, low-power CMOS systems-on-chip, with an emphasis on analog and microwave functions, besides the widely demonstrated advantages of SOI for high-performance digital and memory applications. The SOI assets will both theoretically and experimentally be investigated, from basic technology and device levels to original circuit studies, demonstrating properties and performances significantly superior to those obtained on bulk CMOS, in a large span of processes, from submicron CMOS for pure analog to advanced multiple-gate decananometer CMOS for systems-on-chip design. Table of contents:

• General Introduction, Prof. D. Flandre, UCL • SOI MOSFET specific behaviours and performance assessment,

Prof. D. Flandre, UCL • Analog design and applications, Prof. D. Flandre, UCL • Bulk and surface micromachined SOI MEMS, Prof. J.P. Raskin, UCL • On-wafer wideband characterization of advanced MOS

technologies, Prof. J-P. Raskin, UCL • SOI FinFET integration and digital applications, Dr. N. Collaert, IMEC • The use of SOI FinFET devices in analog and RF circuits,

Dr.P. Wambacq, IMEC

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First FDSOI tutorial of the Thematic Network on SOI technology, devices and circuits. Grenoble, France, 17/11/2008 - 18/11/2008. • Variability Issues (Prof. Asen Asenov, Glasgow University) • Fully-Depleted SOI for Nanometer Subthreshold Circuits (D. Bol, D. Flandre, UCL) • Introduction of the First FDSOI Tutorial (Olivier Faynot, CEA-LETI) • Compact Modeling of Undoped FDSOI MOSFET (O. Rozeau, LETI) • EUROSOI+: European Platform for low-power applications on Silicon on Insulator Technology (Prof. F. Gámiz, UGR) • FDSOI Devices: Physics and Characterization (Prof. Sorin Cristoloveanu, IMEP) • FDSOI Circuit Design (Alexandre Valentian) • FDSOI: Technology and Electrical Results (F. Andrieu) Available at http://www.eurosoi.org/tutorials.asp

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EUROSOI Chalmers, Sweden 19/1/2009 • Modelling of ultra thin body SOI nano-transistors (Prof. Luca Selmi, University of Udine) • Strained channel materials for SOI transistors (Prof. Siegfried Mantl, Forschungszenter, Jülich) • SOI technology: an opportunity for RF designers (Jean-Pierre Raskin, Université Catholique de Louvain) • From MEMS to embedded NEMS (Dr. Julien Arcamone, CEA-LETI, Grenoble) • Ultimately thin carbon on insulators: Graphene (Dr. Max Lemme, Harvard University, Cambridge, Massachusetts) • SOI Circuits: Do you want Partially Depleted or Fully Depleted Devices? (Prof. Jean-Pierre Colinge, Tyndall National Institute, Cork) • Digital SOI design in the nanometer era - from high-performance to ultra-low-power circuits (David Bol, Université Catholique de Louvain) Available at http://www.eurosoi.org/tutorials.asp

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MIGAS '09 - 12th session SOI concepts: from materials to devices and applications 20th - 26th June 2009, AUTRANS-GRENOBLE, France 1) Introduction to SOI - What is SOI ?, J.P. Colinge, Tyndall - SOI zoo, J.P. Colinge, Tyndall 2) SOI Material - Smart-Cut and beyond, L. Clavelier -Technology modules, C. Fenouillet-Béranger, STMicroelectronics & LETI 3) SOI transistors : device physics - Mechanisms in PDSOI and FDSOI devices, O. Faynot, LETI - Transport in double-gate and nanowire MOSFET, T. Hiramoto, University of Tokyo (canceled) - Quantum and tunneling SOI devices, A. Zaslavsky,USA - Advanced simulation, F. Gamiz, UGR - Advanced modelling and ultimate scaling, T. Ernst, LETI 4) Electrical characterization and reliability - Advanced techniques for material and device characterization, S. Cristoloveanu,IMEP-LAHC - Radiation effect and reliability, R. Schrimpf, USA - How SOI can solve variability issues ?, A. Asenov, Glasgow University 5) Designing SOI circuits - SOI circuit design plateform, P. Flatresse,STMicroelectronics - SOI memories, B. De Salvo, LETI - Low power RF, J.-O. Plouchart, IBM, USA - Power devices, P. Wessels, Philips, Netherlands - MEMS, NEMS, sensors, D.Elata, Technion, Israel Available at http://www.eurosoi.org/tutorials.asp

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Workshop: "FD SOI architecture, technology platform for Low Power applications for 22nm and beyond", sponsored by the SOI Consortium and IMEC. October 2009, Leuven, Belgium The development of fully depleted SOI has gained strong momentum in recent years. Although initially FinFETs appeared to be a preferred FDSOI architecture, recent major advances in planar FDSOI devices are strongly positioning this technology towards an interception of the 22/20nm node for Low Power applications. From a design perspective, planar FDSOI is an evolutionary approach that is easier to implement than FinFETs. FDSOI CMOS has proved to reduce the Vt variability by 50-60%, makes possible the smallest SRAM cell operated at Vdd=0.5V with an excellent SNM, reduces Ioff by orders of magnitude and preserves a target performance at a cost per die that is comparable or lower than the equivalent bulk.

Presentations:

• FD-SOI for Low Power CMOS

• Hybrid SOI and Bulk Integration

• Planar FD-SOI technology

• Circuit Design with Planar and Vertical FD-SOI Transistors

• UTSOI and UTBOX wafer readiness

• FD-SOI Technology Benefits for SRAM at the 22nm Node

• Floating Body Cell for Embedded and Standalone DRAM

• Substrate Readiness for ETSOI

• Extremely Thin SOI (ETSOI) CMOS with Record Low Variability for Low Power System-on-Chip Applications Available at http://www.soiconsortium.org/resources/fully-depleted-soi-october-2009.php

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Workshop: "Fully Depleted SOI", sponsored by Soitec and the SOI Consortium December 2009 – Baltimore, USA Experts from around the world gather in Baltimore in December 2009 for a very lively debate on the progress and merits of Fully Depleted SOI. These are the experts' presentations: • ETSOI substrate readiness for FDSOI (Dr. B. Doris, IBM) • Models for FDSOI: BSIM, SPICE (Prof. C. Hu, Univ. California Berkeley) • FDSOI Benefits for SRAM at the 22nm Node (Prof. T.J. King, Univ. California Berkeley) • ARM 1176 implementation in SOI 45nm technology and silicon measurement and outlook towards FDSOI (Dr. Greg Yeric, ARM) Available at http://www.soiconsortium.org/resources/fully-depleted-soi-december-2009.php

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EUROSOI Grenoble, France 25/1/2010 • 3D integration (N. Sillon, CEA-LETI) • Electrical characterisation of SOI nanodevices (G. Ghibaudo, IMEP) • Piezoelectrical technology on SOI (RF Filter) (S. Ballandras, CNRS) • SOI technologies and circuits (J. Hoentschel, Global Foundries) • SOI substrate for RF? (Eric Desbonnet, SOITEC) Available at http://www.eurosoi.org/tutorials.asp

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Workshop: "Fully Depleted SOI", sponsored by Soitec, Tokyo University and the SOI Consortium September 2010 – University of Tokyo, Japan The University of Tokyo hosted a hugely successful one-day workshop on the FD SOI ecosystem’s readiness. The event took place on Saturday, the 25th of September 2010, at the University of Tokyo’s Komaba Research Campus, following the SSDM Conference. (SSDM is one of the most important international conferences held in Japan.) Turnout was excellent, with over 120 participants representing academia and most of the major IDM, foundry and fabless players in attendance. Following the success of the two earlier workshops on Planar Fully-Depleted  SOI Technology, the Tokyo edition was organized by Tokyo University, the SOI Consortium and Soitec. After opening remarks by Toshiro Hiramoto of Tokyo University, compelling presentations from high-profile experts in the industry covered several key aspects of the technology. Topics covered included:

• Transistor technology and integration approaches (talks by Bruce Doris of IBM; Nobuyuki Sugii of Renesas; and Carlo Reita of Leti)

• Application requirements and suitability of FD SOI (talks by Frédéric Bœuf of STMicroelectronics; and Koichiro Ishibashi of Renesas)

• SPICE model readiness (talks by Tsu-Jae King Liu of UC Berkeley and Shuhei Amakawa of Hiroshima University)

• Supporting the ecosystem (talks by Carlo Reita of Leti; Horacio Mendez of the SOI Consortium; and Olivier Bonnin of Soitec)

• FD benchmarking flows and results (talks by Frédéric Bœuf of STMicroelectronics and Mustafa Badaroglu of IMEC)

• Design flow (talk by Jean-Luc Pelloie of ARM) Compelling Results Presented On the technology side, the speakers emphasized that FD SOI solves variability and scalability issues in a cost-effective manner, with high-quality starting wafers available now. In terms of Power  /  Performance  /  Area benchmarking, ST had compelling results on projected FD performance and power advantage at 28nm and 20nm, both for logic and for SRAM. Furthermore, additional strain or design techniques that have not yet been taken into account could further widen the gap.

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UC Berkeley presented work on the VDDmin and yield of 20nm 6T SRAM arrays. They predict 30% larger bit cells on bulk to reach the same 6-sigma yield as on FD SOI – and this for a Vmin that is 200mV worse than what FD SOI can achieve. Jean-Luc Pelloie of ARM made it clear that there is basically no specificity to design on FD SOI: same tools, same flows, and easy porting of foundation IP. Kazunari Ishimaru of Toshiba concluded with an action item: it is time for the IC industry to start a pilot product. Available at http://www.soiconsortium.org/corners/fully-depleted-soi/september-2010/index.php

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Tutorial: “Silicon on Insulator: Materials to Circuit Design”, sponsored by EUROSOI, Tyndall National Institute and University of Granada September 2010, Seville, Spain

1. Smart-cut enabled materials Cindy Colinge (Tyndall)

2. Physics of SOI devices. Jean Pierre Colinge (Tyndall)

3. SOI MOSFET compact models. Benjamin Iñiguez (URV)

4. SOI Design: RF. Jean Pierre Raskin (UCL)

5. Analog SOI CMOS devices : figures of merit, design techniques and applications. Denis Flandre (UCL)

6. SOI design: logic circuits. Philippe. Flatresse (STM)

Available at http://www.eurosoi.org/tutorials.asp

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Workshop: "Fully Depleted SOI", sponsored by Soitec, CEA-LETI and the SOI Consortium December 2010 – San Francisco, USA The SOI Consortium, the CEA-Leti and Soitec organized an evening workshop at Hilton San Francisco Hotel (333 O’Farrell St) on the 8th of December 2010 following the IEDM Conference, focusing on the low power and high speed technology requirements for SOC applications, on design infrastructure and on the advantages for scaling: improved VT roll off, lowest VT variability, better subthreshold slope, better DIBL for the coming nodes, starting with 20nm. This workshop was co-organized by Dr. Horacio Mendez from the SOI Consortium, Dr. Carlos Mazure and Mrs. Bich-Yen Nguyen from Soitec, and Dr. Olivier Faynot from CEA-Leti. PRESENTATIONS:

• Opening remarks (Dr. Carlos Mazure – Soitec) • Random device variability benchmark for bulk and FDSOI with 4 sigma

data resolution (Prof. Toshiro Hiramoto – University of Tokyo, MIRAI – Selete)

• Design flow in FDSOI (Dr. Jean-Luc Pelloie – ARM) • Device Technology Requirement for Wireless Systems-On-Chip (Dr.

Geoffrey Yeap and Dr. Aaron Thean – Qualcomm) • Ultra low power 0.3V FDSOI device design (Dr. Jakub Kedzierski – MIT) • Device Requirements for GPU & SOC (Dr. Boon-khim Liew – nVidia) • FDSOI Supply Chain (Dr. Christophe Maleville – SOITEC) • Low Power and High Speed at Low Voltage for Mobile Applications (Dr.

Thomas Skotnicki – ST Microelectronics) Available at http://www.soiconsortium.org/corners/fully-depleted-soi/december-2010/index.php

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Tutorial “Silicon-on-Insulator Technologies for Future Electronics” EUROSOI Granada, Spain 17/01/2011

1. Silicon-on-Insulator technologies for future electronics. F.Gamiz, UGR, Spain

2. SOI solutions for next technological nodes Prof. Sigfried Mantl, FZJülich, Germany

3. ETSOI Technology Dr. Bruce Doris, IBM, USA

4. CMOS-SOI-MEMS Imagers Prof. Y. Nemirovsky, Technion, Israel

5. SOI Low-power applications Dr. N. Sugii, LEAP, Japan

6. Memories on SOI Dr.Malgorzata Jurczak, IMEC Belgium

7. SOI Photonics Dr. Jean Marc Fedeli, LETI, France

Available at http://www.eurosoi.org/tutorials.asp

EUROSOI+ FP7-216373 28 of 28 30/06/2010

Workshop: "Fully Depleted SOI", sponsored by Soitec, CEA-LETI and the SOI Consortium April 2011 – Hsinchu, Taiwan The SOI Industry Consortium, CEA-Leti and Soitec organized the 5th edition of the FDSOI Workshop at the Ambassador Hotel, in Hsinchu, Taiwan on April 28 following the VLSI-TSA and VLSI-DAT conferences (April 25-27, 2011). This workshop was co-organized by Dr. H. Mendez from the SOI Industry Consortium, Dr. O. Faynot from CEA-Leti and Dr. C. Mazure and Mrs. B.-Y. Nguyen from Soitec. As the industry is preparing for the 14nm node that many believe will require a fully depleted device architecture, planar FDSOI offers today an excellent value proposition with an evolutionary CMOS solution for 20nm for low power and high speed. Published data show VT variability reduction by 60%, and best Ion/Ioff ratios from VDD 1V down to 0.5V compared to bulk based processes. FDSOI technology enables low VDD operation for logic and high-density SRAM cells at sub-0.6V VDD regime with excellent SNM and minimum cell size. Using an ARM Cortex™-M0 core, a team of SOI Industry Consortium members demonstrated that planar FDSOI technology enables designers to continue to decrease the voltage to reduce the overall power, while maintaining system performance. PRESENTATIONS:

• Introduction (by Horacio Mendez) • FDSOI design migration from Bulk at 20nm node (by Xavier Cauchy) • SRAM analysis (by Changhwan Shin) • CMOS Technology for 20nm and beyond (by Ali Khakifirooz) • FDSOI Substrate readiness and supply chain (by Olivier Bonnin) • FDSOI - Manufacturability Perspective (by Tomasz Brozek) • BSIM models for SOI (by Sriramkumar Venugopalan) • Si calibrated FDSOI Modeling (by Olivier Faynot) • 0.4V Technology reliability and application (by Nobuyuki Sugii) • Device variability benchmark for bulk and FDSOI MOSFETs (by Toshiro

Hiramoto) Available at http://www.soiconsortium.org/corners/fully-depleted-soi/april-2011/index.php