Exceptions, Interrupts, and the OS

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Exceptions, Interrupts, and Exceptions, Interrupts, and the OS the OS

STOP!! Do this!!!STOP!! Do this!!!

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Interrupts Interrupts

•Have device tell OS/CPU it is readyHave device tell OS/CPU it is ready•Requires hardware to support.Requires hardware to support.•OS/CPU can then interrupt what it is OS/CPU can then interrupt what it is

doing to:doing to:•Determine what device wants Determine what device wants

serviceservice•Determine what service it wantsDetermine what service it wants•Perform or start the servicePerform or start the service•Go back to what OS/CPU was doingGo back to what OS/CPU was doing

““External condition related to IO devices”External condition related to IO devices”

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Examples of InterruptsExamples of Interrupts

• Disk drive at sector/track position Disk drive at sector/track position (old days)(old days)

• Mouse movedMouse moved• Keyboard key pressedKeyboard key pressed• Printer out of paperPrinter out of paper• Video card wants memory accessVideo card wants memory access• Modem sending or receivingModem sending or receiving• USB scanner has dataUSB scanner has data

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Interrupt PropertiesInterrupt Properties

•They arrive asynchronouslyThey arrive asynchronously•Can’t communicate with a running Can’t communicate with a running

program (no args or return values)program (no args or return values)•They are associated with various They are associated with various

prioritiespriorities•You want to handle them soon You want to handle them soon

(interrupt latency)(interrupt latency)•(usually) want to resume program(usually) want to resume program

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TrapTrap““Internal conditions related to instruction Internal conditions related to instruction

stream”stream”

Trap Examples:Trap Examples:

• “ “TRAP” instructionTRAP” instruction• Illegal instructionIllegal instruction• Arithmetic overflowArithmetic overflow• Divide by zeroDivide by zero• “ “LD” from illegal/protected memory LD” from illegal/protected memory addressaddress

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• They arrive synchronouslyThey arrive synchronously• Get trap in same place if you re-run programGet trap in same place if you re-run program• They are associated with various prioritiesThey are associated with various priorities• Must handle immediatelyMust handle immediately• Want to resume program Want to resume program (usually) (usually)

Trap PropertiesTrap Properties

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Exceptions Exceptions

““Mechanism used to handle both interruptsMechanism used to handle both interruptsand traps”and traps”

•HW handles initial reactionHW handles initial reaction•Then invokes SW called an “Exception Then invokes SW called an “Exception

Handler” to take care of the interrupt/trapHandler” to take care of the interrupt/trap

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HC11 ExceptionsHC11 Exceptions

• HC11 is real hardware and thus has HC11 is real hardware and thus has mechanisms to deal with both Traps and mechanisms to deal with both Traps and Interrupts.Interrupts.

• We will deal with interrupts only.We will deal with interrupts only.

• HC11 does things very similar to the LC-3.HC11 does things very similar to the LC-3.

• Uses an “Interrupt Vector” table to find Uses an “Interrupt Vector” table to find address of interrupt and goes straight to address of interrupt and goes straight to specific specific Interrupt Service RoutineInterrupt Service Routine (ISR). (ISR).

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HC11 Micro Kit Jump TableHC11 Micro Kit Jump Table

//// 1 1 unavailable to userunavailable to user SCISCIISR_JUMP2ISR_JUMP2 EQUEQU 0x7BC50x7BC5 //SPI//SPIISR_JUMP3ISR_JUMP3 EQUEQU 0x7BC80x7BC8 // Pulse Accumulator Input// Pulse Accumulator InputISR_JUMP4ISR_JUMP4 EQUEQU 0x7BCB0x7BCB // Pulse Accumulator Overflow// Pulse Accumulator Overflow//// 5 5 unavailable to userunavailable to user Timer OverflowTimer Overflow//// 6 6 unavailable to userunavailable to user Output Compare 5Output Compare 5ISR_JUMP7ISR_JUMP7 EQUEQU 0x7BD40x7BD4 // Output Compare 4// Output Compare 4ISR_JUMP8ISR_JUMP8 EQUEQU 0x7BD70x7BD7 // Output Compare 3// Output Compare 3ISR_JUMP9ISR_JUMP9 EQUEQU 0x7BDA0x7BDA // Output Compare 2// Output Compare 2ISR_JUMP10ISR_JUMP10 EQUEQU 0x7BDE0x7BDE // Output Compare 1// Output Compare 1ISR_JUMP11ISR_JUMP11 EQUEQU 0x7BE30x7BE3 // Input Capture 3// Input Capture 3ISR_JUMP12ISR_JUMP12 EQUEQU 0x7BE60x7BE6 // Input Capture 2// Input Capture 2ISR_JUMP13ISR_JUMP13 EQUEQU 0x7BE90x7BE9 // Input Capture 1// Input Capture 1//// 14 14 unavailable to userunavailable to user Real Time InterruptReal Time InterruptISR_JUMP15ISR_JUMP15 EQUEQU 0x7BEC0x7BEC // IRQ – Button on Kit// IRQ – Button on Kit//// 16 16 unavailable to userunavailable to user XIRQXIRQ//// 17 17 unavailable to userunavailable to user SWISWI//// 18 18 unavailable to userunavailable to user Illegal OpcodeIllegal OpcodeISR_JUMP19ISR_JUMP19 EQUEQU 0x7BF80x7BF8 // Cop fail// Cop failISR_JUMP20ISR_JUMP20 EQUEQU 0x7BFB0x7BFB // Cop clock fail// Cop clock fail//// 21 21 unavailable to userunavailable to user Reset (found at 0x8040)Reset (found at 0x8040)

See Motorola documentation for discussion of unavailable See Motorola documentation for discussion of unavailable vectorsvectors. .


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Configuring interrupts for the HC11 is pretty easy.Configuring interrupts for the HC11 is pretty easy.

What you need to do is:What you need to do is:

1) Make an ISR, it is just like a procedure but returns with RTI.1) Make an ISR, it is just like a procedure but returns with RTI.

2) Put the address of the ISR into the Jump Table.2) Put the address of the ISR into the Jump Table.

Example:Example:// initializes the ISR jump vectors to our interrupt service routines// initializes the ISR jump vectors to our interrupt service routines

// jump vectors are defined in v2_18g3.asm// jump vectors are defined in v2_18g3.asm

ldx #BUTTON_isrldx #BUTTON_isr

stx ISR_JUMP15stx ISR_JUMP15

BUTTON_isr:BUTTON_isr:

// Put your code in here. Do not do any I/O in an ISR// Put your code in here. Do not do any I/O in an ISR

……

// Use this to return from an interrupt// Use this to return from an interrupt

rtirti


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1.1. Wait for current instruction to completeWait for current instruction to complete2.2. Disable further interruptsDisable further interrupts3.3. Save all CPU registers and return Save all CPU registers and return

address on stackaddress on stack4.4. Access “interrupt vector table” Access “interrupt vector table”

according to sourceaccording to source5.5. Jump to where the interrupt routine is Jump to where the interrupt routine is

specified in tablespecified in table6.6. Use RTI to returnUse RTI to return

HC11 Hardware MechanismHC11 Hardware Mechanism

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LC-3 ExceptionsLC-3 Exceptions

• LC-3 only has the concept of IO LC-3 only has the concept of IO related exceptions, interrupts.related exceptions, interrupts.

• Does not have any mechanisms to Does not have any mechanisms to deal with illegal instructions, or deal with illegal instructions, or arithmetic overflow.arithmetic overflow.

• Remember the LC-3 is just a Remember the LC-3 is just a learning aid, not real hardware. learning aid, not real hardware.

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LC-3 Interrupt-Driven I/OLC-3 Interrupt-Driven I/O

External device can:External device can:(1)(1) Force currently executing program to stop;Force currently executing program to stop;

(2)(2) Have the processor satisfy the device’s needs; andHave the processor satisfy the device’s needs; and

(3)(3) Resume the stopped program as if nothing happened.Resume the stopped program as if nothing happened.

Why do interrupts?Why do interrupts?– Polling consumes a lot of cycles, especially for rare

events – these cycles can be used for more computation.– Example: Process previous input while collecting current

input. (See Example 8.1 in text.)

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LC-3LC-3 Interrupt-Driven I/O Interrupt-Driven I/O

To implement an interrupt mechanism, we need:To implement an interrupt mechanism, we need:

– A way for the I/O device to signal the CPU that aninteresting event has occurred.

– A way for the CPU to test whether the interrupt signal is set and whether its priority is higher than the current program.

Generating SignalGenerating Signal

– Software sets "interrupt enable" bit in device register.– When ready bit is set and IE bit is set, interrupt is

signaled.

ready bit KBSR1514 013

interrupt enable bit

interrupt signal to processor

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PriorityPriorityEvery instruction executes at a stated level of urgency.Every instruction executes at a stated level of urgency.

LC-3: 8 priority levels (PL0-PL7)LC-3: 8 priority levels (PL0-PL7)

– Example: • Payroll program runs at PL0.• Nuclear power correction program runs at PL7.

– It’s OK for PL6 device to interrupt PL0 program, but not the other way around.

Priority encoderPriority encoder selects highest-priority device, compares to selects highest-priority device, compares to current processor priority level, and generates interrupt current processor priority level, and generates interrupt signal if appropriate.signal if appropriate.


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Testing for Interrupt SignalTesting for Interrupt Signal•CPU looks at signal between STORE and FETCH phases.CPU looks at signal between STORE and FETCH phases.

•If not set, continues with next instruction.If not set, continues with next instruction.

•If set, transfers control to interrupt service routine.If set, transfers control to interrupt service routine.

EAEA

OPOP

EXEX

SS

FF

DD

interruptsignal?

Transfer toISR

Transfer toISR

NO

YES


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Full Implementation of LC-3 Memory-Full Implementation of LC-3 Memory-Mapped I/OMapped I/O

Because of interrupt enable bits, status registers (KBSR/DSR)Because of interrupt enable bits, status registers (KBSR/DSR)must now be written, as well as read.must now be written, as well as read.

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LC-3 Interrupts:LC-3 Interrupts:

1. External device signals need to be serviced.2. Processor saves state and starts service routine.3. When finished, processor restores state and

resumes program.

An interrupt is an unscripted subroutine call, triggered by an

external event.

LC-3 Handling of LC-3 Handling of interrupts interrupts

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Processor StateProcessor StateWhat state is needed to completely capture the state of a What state is needed to completely capture the state of a running process?running process?

Processor Status RegisterProcessor Status Register

– Privilege [15], Priority Level [10:8], Condition Codes [2:0]

Program CounterProgram Counter

– Pointer to next instruction to be executed.

RegistersRegisters

– All temporary state of the process that’s not stored in memory.

LC-3 Handling of interrupts LC-3 Handling of interrupts

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Where to Save Processor State?Where to Save Processor State?

Can’t use registers.Can’t use registers.

– Programmer doesn’t know when interrupt might occur, so she can’t prepare by saving critical registers.

– When resuming, need to restore state exactly as it was.

Memory allocated by service routine?Memory allocated by service routine?

– Must save state before invoking routine, so we wouldn’t know where.

– Also, interrupts may be nested – that is, an interrupt service routine might also get interrupted!

Use a stack!Use a stack!

– Location of stack “hard-wired”.– Push state to save, pop to restore.

LC-3 Handling of interrupts LC-3 Handling of interrupts

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Operating SystemsOperating Systems

• The “program” that runs the user The “program” that runs the user programs and deals with exceptions.programs and deals with exceptions.

• How does the operating system deal How does the operating system deal with such things as simultaneous with such things as simultaneous exceptions?exceptions?

• What happens on machines that What happens on machines that have many users “on” at once?have many users “on” at once?

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Multiple Exceptions Multiple Exceptions

Problem: How about multiple simultaneous exceptions?Problem: How about multiple simultaneous exceptions?

Solution: Have priorities in HW / SWSolution: Have priorities in HW / SW

• Handle highest-priority exception firstHandle highest-priority exception first• Equal priority exceptions handled arbitrarilyEqual priority exceptions handled arbitrarily• Give higher priorityGive higher priority

• more serious (e.g., power failing)more serious (e.g., power failing)• can’t wait long (e.g., rotating disk)can’t wait long (e.g., rotating disk)

Operating SystemsOperating Systems

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Operating Systems: Multiple Exceptions Operating Systems: Multiple Exceptions

How about exceptions during exception How about exceptions during exception handling?handling?

• Make it wait until done with first exceptionMake it wait until done with first exception• May be a bad idea for higher priority May be a bad idea for higher priority

exceptionexception

• Make exception handler re-entrantMake exception handler re-entrant• Make able to handle multiple active callsMake able to handle multiple active calls• Allow higher-priority exceptions to bypass Allow higher-priority exceptions to bypass

lower-priority exception currently being lower-priority exception currently being servicedserviced

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Implementing a Re-entrant exception Implementing a Re-entrant exception handlerhandler

• Initial exception disables all interruptsInitial exception disables all interrupts• Exception handler (EH) determines exception’s Exception handler (EH) determines exception’s

prioritypriority• EH saves any state that could be clobbered by EH saves any state that could be clobbered by

higher priority interrupts (e.g. EPC)higher priority interrupts (e.g. EPC)• EH re-enables higher-priority interruptsEH re-enables higher-priority interrupts• Higher-priority interrupts may or may nor occurHigher-priority interrupts may or may nor occur• This EH eventually finishesThis EH eventually finishes

Operating Systems: Multiple Exceptions Operating Systems: Multiple Exceptions

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Multiprogramming Multiprogramming

An active program is called a “An active program is called a “process”process” or or ““task”task”A process’ state is:A process’ state is:

• program counterprogram counter• registersregisters• memory locations being usedmemory locations being used• Some OS memorySome OS memory

The ability to run one or more programs The ability to run one or more programs “simultaneously” on one CPU.“simultaneously” on one CPU.

Operating Operating SystemsSystems

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Operating Systems: Multiprogramming Operating Systems: Multiprogramming

• OS has one exception handler called the “kernel”OS has one exception handler called the “kernel”• On an exception, CPU jumps into the kernelOn an exception, CPU jumps into the kernel• Kernel will eventually resume the user processKernel will eventually resume the user process

• If the user process needs I/O (disk read)If the user process needs I/O (disk read)• Kernel schedules itKernel schedules it• 20ms is ~ 2 million instructions20ms is ~ 2 million instructions• Start (or switch to) another task (multitasking)Start (or switch to) another task (multitasking)

• If user process does not need I/OIf user process does not need I/O• Kick it out (context switch) after some amount of timeKick it out (context switch) after some amount of time• Every X clock cycles interrupt and switch againEvery X clock cycles interrupt and switch again

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OS has several job queues - An entry is the OS has several job queues - An entry is the complete state of a processcomplete state of a process

Some queue examples:Some queue examples:

• A queue of ready jobs with priorityA queue of ready jobs with priority• A queues for I/O device(s)A queues for I/O device(s)• Jobs are moved to ready queue when I/O Jobs are moved to ready queue when I/O completecomplete• A queue of sleeping or halted jobsA queue of sleeping or halted jobs

OS picks jobs from the ready queue as appropriateOS picks jobs from the ready queue as appropriate

Operating Systems: Multiprogramming Operating Systems: Multiprogramming

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Generalized ExceptionsGeneralized Exceptions

1.1. User program runningUser program running2.2. Exception is generatedException is generated

• Internal/ExternalInternal/External• Trap/InterruptTrap/Interrupt

3.3. Determine source of exceptionDetermine source of exception• Requires a bus cycle for some peripheral busRequires a bus cycle for some peripheral bus

architectures. architectures. 4.4. Save return PC and any status registers modified Save return PC and any status registers modified

by hardwareby hardware• LC-3: PC, PSR, registers R0-R7LC-3: PC, PSR, registers R0-R7• HC11: PC, index registers, accumulatorsHC11: PC, index registers, accumulators

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Generalized Exceptions Generalized Exceptions

5.5. Jump to exception handlerJump to exception handler• LC-3: Uses a jump tableLC-3: Uses a jump table• HC11: Jump table starting at 0xFFD6HC11: Jump table starting at 0xFFD6• 68000: Jump to location specified by interrupt68000: Jump to location specified by interrupt

device – device – vectored interruptsvectored interrupts6.6. Save state used by exception handlerSave state used by exception handler7.7. Go to specific caseGo to specific case

• Check exception typeCheck exception type• Query deviceQuery device• Check syscall registerCheck syscall register

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Generalized Exceptions Generalized Exceptions

8.8. Process ExceptionProcess Exception• Enable higher-priority interrupts if possibleEnable higher-priority interrupts if possible• For interrupt, clear device’s interrupt flagFor interrupt, clear device’s interrupt flag• Check device for multiple conditionsCheck device for multiple conditions

9.9. Restore state used by exception handlerRestore state used by exception handler10.10.Return from exceptionReturn from exception

• Restore modeRestore mode• Restore hardware-saved stateRestore hardware-saved state• Jump back to user programJump back to user program

• or exception handleror exception handler

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Exceptions SummaryExceptions Summary

•Exceptions (interrupts and traps) are a Exceptions (interrupts and traps) are a combination of hardware and software.combination of hardware and software.

•The hardware detects the exception and The hardware detects the exception and then calls software (OS or service routines) then calls software (OS or service routines) to handle it.to handle it.

•Much more efficient than polling but Much more efficient than polling but requires specialized hardware.requires specialized hardware.

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Questions?Questions?

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Exceptions, Interrupts, and the OS