Exercise Solutions - nxp.com fileSMC1 base IDMA1base MCC2 SMC2 base IDMA2 base SPI base IDMA3 base Timers Rev_num D_ptr Rand I2C base IDMA4 base 8000 8400 8700 87FC 87FE 8800 88FC

14-1

Exercise Solutions

14-2

Solution - How to Locate the Internal Memory

DPRAM1

Reserved

DPRAM2

Reserved

DPRAM3

Reserved

Registers

Address of IMMIMMR

SCC1-4FCC1-3MCC1

SMC1 baseIDMA1base

MCC2SMC2 base

IDMA2 baseSPI base

IDMA3 baseTimers

Rev_numD_ptrRand

I2C baseIDMA4 base

80008400870087FC87FE880088FC88FE89FC89FE8AE08AF08AF28AF88AFC8AFE

4x2563x256 128 2 2 128 2 2 2 2 16 2 2 4 2 2

Page Address Peripheral size1-45-7 8

9

10

11

0x4000

0x8000

0x9000

0xB000

0xC000

0x10000

1. If IMMR = 0x96000102, then the internal memory map is located at the following address(see page 8-33 in UM): 0x96000000.

2. The register BCR is at the following address (see page 2-1 in UM): 0x96010024.

3. The MCC2 parameter block begins at the following address (see page 25-3 in UM):0x96008800.

4. The HDLC specific parameter RAM for FCC2 begins at the following address (see page 29-4 in UM): 0x96008540.

14-3

HDLC Solution (1 of 3)/* This is an example of transmitting on FCC1 in HDLC. A *//* frame of data is transmitted using two buffers. When the*//* second buffer has been sent, the LED counter on Port D *//* is incremented. */

void *const stdout = 0; /* STANDARD OUTPUT DEVICE */#define hdlcf1 /* FCC1 IS TO BE HDLC */#include “mpc8260.h” /* INTNL MEMORY MAP EQUATES */extern struct immbase *pimm; /* POINTER TO INTNL MEMORY MAP*/struct descs { txbdfh TxBD0; /* TRANSMIT BUFFER 0 */ txbdfh TxBD1; /* TRANSMIT BUFFER 1 */ };struct descs *pdsc; /* POINTER TO DESCRIPTOR */

main(){ clrdpr(); /* CLEAR DUAL PORT RAM */ pimm->PDATD = 0; /* CLEAR PORT D DATA REG */ pimm->PDIRD = 0xFF; /* MAKE PORT D24-31 OUTPUT*/

14-4

HDLC Solution (2 of 3) pimm->PPARB = 0x08000000; /* PB4 IS TxD */ pimm->BRGC7 = 1<<16 + 31<<1 + 1; /* 256Kbps AT 133 MHz */ pimm->CMXFCR = 0x2000000; /* ROUTE BRG7 TO FCC1 */ pimm->GFMR1 = 0x2000; /* FLAGS BETWEEN FRAMES */ pimm->FPSMR1 = 0x20000000; /* 2 FLAGS BETWEEN FRAMES*/ /* NO TIME STAMP, NOT */ /* NIBBLE MODE,16-BIT CRC*/ pimm->FCC1.TIPTR = 0xB000 + 32; /* INIT TEMP XMIT PNTR */ pimm->FCC1.TSTATE = 0x12<<24; /* BIG ENDIAN,BUFS LOCAL */ pimm->FCC1.TBASE = 0x200000; /* TxBDS AT 0x200000 */ pdsc = (struct descs *) 0x200000; /* INIT PNTR TO TxBD */ pdsc->TxBD0.txbdptr = 0x400000; /* Tx BUFFER0 AT 0x400000*/ pdsc->TxBD0.txbddl = 100; /* INIT DATA LNGTH TO 100*/ pdsc->TxBD0.txbdsac = 0x8000; /* INIT SAC READY */ pdsc->TxBD1.txbdptr = 0x400800; /* Tx BUFFER1 AT 0x400800*/ pdsc->TxBD1.txbddl = 100; /* INIT DATA LNGTH TO 100*/ pdsc->TxBD1.txbdsac = 0xBC00; /* INIT SAC READY,WRAP */ /* INTRPT,LAST,APPEND CRC*/ /* NO RECEIVE REQUIREMENT, THEREFORE NO RxBDS */ /* NO INTERRUPTS, THEREFORE FCCM1 IS NOT CHANGED */ /* DEFAULT PRIORITY ORDER OK, THEREFORE SCPRR_H NOT CHNGD*/

14-5

HDLC Solution (3 of 3)/* NO INTERRUPTS,THEREFORE SIMR_L IS NOT CHANGED */ pimm->CPCR = 0x12010002; /* INIT Tx PARAMETERS */ while (pimm->CPCR & (1<<16)) == 1<<16); /*WAIT FLAG CLEAR */ pimm->GFMR1 |= 1<<4; /* ENABLE TRANSMIT */ while ((pimm->FCCE1 & (2<<16)) == 0); /* WAIT FOR EVENT */ pimm->PDATD += 1; /* INCREMENT PORT D */}

clrdpr(){ UWORD *pint; /* integer pointer */

pint = (UWORD *)(UWORD) pimm; for (i = 0; i < 0x1000; i++) /* CLEAR DPRAM1 */ *pint++ = 0; pint = (UWORD *)((UWORD) pimm + 0x8000); for (i = 0; i < 0x400; i++) /* CLEAR DPRAM2 */ *pint++ = 0; pint = (UWORD *)((UWORD) pimm + 0xB000); for (i = 0; i < 0x400; i++) /* CLEAR DPRAM3 */ *pint++ = 0;}

14-6

Solution - FCC Parameter RAM

InitializeATM

ParameterRAM,FCC1

int *pint; /* integer pointer */

pint = (int *)(int)pimm;for (i = 0; i < 0x1000; i++) /* CLEAR DPRAM1 */ *pint++ = 0;pint = (int *)((int)pimm + 0x8000);for (i = 0; i < 0x400; i++) /* CLEAR DPRAM2 */ *pint++ = 0;pint = (int *)((int)pimm + 0xB000);for (i = 0; i < 0x400; i++) /* CLEAR DPRAM3 */ *pint++ = 0;pimm->FCC1.RCELL_TMP_BASE = 0xB000; /* Rx cell temp at 0xB000 */pimm->FCC1.TCELL_TMP_BASE = 0xB040; /* Tx cell temp next */pimm->FCC1.BD_BASE_EXT = 0x8C000000; /* BDs at 0x8C000000 */

1. The “for loops” initialize all of dual port RAM to zero.2. RCELL and TCELL_TMP_BASE are initialized to point at the DPRAM3area.

Description

__packed__(2,2) struct immbase { /*INTRNL MEMORY MAP */ . __packed__(2,2) struct { UWORD FCC1RES[16]; /* RESERVED */ . UHWORD RCELL_TMP_BASE; /* RX CELL TEMP ADDR */ UHWORD TCELL_TMP_BASE; /* TX CELL TEMP ADDR */ . UWORD BD_BASE_EXT; . } FCC1; .};

AssumedStructures

14-7

Solution 1 - Connection Table Memory ClearClear

ConnectionTables

pint = (UWORD *)((UWORD) pimm + pimm->FCC1.INT_RCT_BASE); /* INIT PNTR TO INT RCT */for (i = 0; i < 128*32/4; i++) /* CLEAR INT RCT */ *pint++ = 0;pint = (UWORD *)((UWORD) pimm + pimm->FCC1.INT_TCT_BASE); /* INIT PNTR TO INT TCT */for (i = 0; i < 128*32/4; i++) /* CLEAR INT TCT */ *pint++ = 0;pint = (UWORD *)((UWORD) pimm->FCC1.EXT_RCT_BASE + 8192); /* INIT PNTR TO EXT RCT */for (i = 256*32/4; i < 65536*32/4; i++) *pint++ = 0; /* CLEAR EXT RCT */pint = (UWORD *)((UWORD) pimm->FCC1.EXT_TCT_BASE + 8192); /* INIT PNTR TO INT TCT */for (i = 256*32/4; i < 65536*32/4; i++) *pint++ = 0; /* CLEAR EXT TCT */

Write a program to initialize connection tables with all zeroes.

1. The first two ‘for loops” clear the internal connection tables which shouldnormally have been cleared previously.2. The second two “for loops” clear the external connection tables.

Description

__packed__(2,2) struct immbase { /*INTERNAL MEMORY MAP */ . __packed__(2,2) struct { UWORD FCC1RES[16]; /*RESERVED */ . UHWORD INT_RCT_BASE; /*INTRNL RCT POINTER */ UHWORD INT_TCT_BASE; /*INTRNL TCT POINTER */ . UWORD EXT_RCT_BASE; /*EXTRNL RCT POINTER */ UWORD EXT_TCT_BASE; /*EXTRNL TCT POINTER */ . } FCC1; /*FCC1 PARAMETER RAM */ .};

AssumedStructures

14-8

Solution 2 - Connection Table Entry Initialization (1 of 2)

InitializeConnection

Table

/* INITIALIZE THE RCT */prct = (rct *)((UWORD)pimm + pimm->FCC1.INT_RCT_BASE + 3 * 32); /* INIT RCT PNTR TO CT3 */prct->rcntrl1 = 0x1302; /* INIT 1ST CNTRL FLD RCT*/prct->rcntrl2 = 2; /* AAL5 CHANNEL */prct->mrblr = 384; /* INIT MAX RECV BUF LNGT*/prct->rcntrl4 = 0; /* INIT RECV BD BASE PNTR*/prct->rbd_offset = 0; /* INIT RECV BD OFST PNTR*/

Write a program to initialize connection tables for channel 3 as follows:• AAL5• Big Endian• Data buffers and interrupt queue on local bus• Use interrupt queue 2• Maximum receive buffer length is 384• RxBDs at the start of the BD areas; TxBDs at 0x1000 from start.• Transmit header is to be 0x600

(Continued on next page)

typedef __packed__(2,2) struct { UHWORD rcntrl1; /*GBL,BO,DTB,BIB,BUFM,etc.*/ UHWORD rcntrl2; /*INF,ABRF,AAL */ UWORD rxbdptr; /* RxBDPTR */ UWORD celltimestamp; /* CELL TIME STAMP */ UHWORD rbd_offset; /* RBD_Offset */ UHWORD tml; /* TOTAL MESSAGE LENGTH */ UWORD rxcrc; /* CRC32 TEMP RESULT */ UHWORD rbdcnt; /* RXBD COUNT */ UHWORD rctreserved; /* RESERVED */ UHWORD rcntrl3; /* RXBM,RXFM,BPOOL */ UHWORD mrblr; /* MAX RECV BUFFER LENGTH */ UWORD rcntrl4; /* PMT,RBD_BASE,PM */} rct; /* RECEIVE CONNECTION TBL */ /* FOR AAL5 CHANNELS */

AssumedStructure

14-9

Solution 2 - Connection Table Entry Initialization (2 of 2)

ptct = (tct *)((UWORD)pimm + pimm->FCC1.INT_TCT_BASE + 3 * 32); /* INIT TCT PNTR TO CT3 */ptct->tcntrl1 = 0x1306; /* INIT 1ST CNTRL FLD TCT*/ptct->tcntrl2 = 2; /* AAL5 CHANNEL */ptct->tcntrl3 = 0x100<<4; /* INIT XMIT BD BASE PNTR*/ptct->tbd_offset = 0; /* INIT XMIT BD OFST PNTR*/ptct->atmch = 0x600; /* INIT TCT HEADER */

typedef __packed__(2,2) struct { UHWORD tcntrl1; /*GBL,BO,DTB,BIB,AVCF,etc.*/ UHWORD tcntrl2; /*INF,ABRF,AAL */ UWORD txbdptr; /* TxBDPTR */ UHWORD tbdcnt; /* XMIT BD COUNT */ UHWORD tbd_offset; /* TBD_Offset */ UBYTE raterem; /* RATE REMAINDER */ UBYTE pcrf; /* PCR FRACTION */ UHWORD pcr; /* PEAK CELL RATE */ UWORD txcrc; /* CRC32 TEMPORARY RESULT */ UHWORD tml; /* TOTAL MESSAGE LENGTH */ UHWORD apclc; /* APC LINKED CHANNEL */ UWORD atmch; /* ATM CELL HEADER */ UWORD tcntrl3; /* PMT,TBD_BASE,BNM,etc. */} tct; /* TRANSMIT CONNECTION TBL*/ /* FOR AAL5 CHANNELS */

AssumedStructure

14-10

Solution - Initializing the Address Compression Tables (1 of 8)Initialize the address compression tables for the following parameters:

PHY VPI VCICell Header Channel

Code2021

2223

2425

20x12

0x650xE4

0x1FF0x334

1

2

00

00

00

VP_MASK

3

VC_MASK

0xF6

0x3FF

VC_OFFSET

0

0x100

• VC_MASK1. For VPI=1, VC_MASK = 2 | 0x12 | 0xE4 = 0xF62. For VPI=2, VC_MASK = 0x65 | 0x1FF | 0x334 = 0x3FF

• VC_OFFSET1. For VPI=2, VC_OFFSET = length of VCtable for VPI=1 = (VCpointer max + 1) * 4 = (0x3F + 1) * 4 = 0x100

14-11

Solution - Initializing the Address Compression Tables (2 of 8)

VPtableVPT_BASE 1

VCtable

0x40 Entries

0x400 Entries

VC_MASK

VC_OFFSET

14-12

Solution - Initializing the Address Compression Tables (3 of 8)Init_AC_Tables(){ UHWORD i,j; /* temporary variables */ UWORD VptEntries; /* nmbr of Vptable entries */ UWORD *pvp,*pvc; /* VP,VC table entry pointers */

pimm->FCC1.GMODE |= 9; /* enable address compression */ /* and unallocated bit check */ pimm->FCC1.VP_MASK = 3; /* init VP_MASK */

/* initialize tables for no entries */ for (i=0,j=0; i<16; i++) /* determine numbr*/ { /* of ones in */ if (pimm->FCC1.VP_MASK & (1 << i)) /* VP_MASK */ j++; } VptEntries = 1<<j; /* determine table size */ pvp = (UWORD *)(pimm->FCC1.VPT_BASE); /* init Vptab pntr */ for (i=0; i<VptEntries; i++) /* clear entries */ *pvp++ = 0; pvc = (UWORD *)(pimm->FCC1.VCT_BASE); /* init Vctab pntr */ *pvc = 1<<31; /* init non-entry */

__packed__(2,2) struct immbase { /*INTRNL MEMORY MAP */ . __packed__(2,2) struct { UWORD FCC1RES[16]; /* RESERVED */ . UWORD VPT_BASE; /* VP TABLE BASE ADDR*/ UWORD VCT_BASE; /* VC TABLE BASE ADDR*/ . UHWORD VP_MASK; /* VP MASK */ . UHWORD GMODE; /* GLOBAL MODE ENTRY */ . } FCC1; .};

AssumedStructures

14-13

Solution - Initializing the Address Compression Tables (4 of 8) pw = (UWORD *)GetVPpointer(1); /*add PHY_VPI=1 to Vptable*/ *pw = 0xF6<<16 + 1; /*assign VCMASK/OFFSET for VPI=1*/ pvc = (UWORD *)(pimm->FCC1.VCT_BASE + 4); for (j=0; j=0x40; j++) /* init VC table to non-entry */ *pvc++ = 1<<31; pw = (UWORD *)GetVPpointer(2); /*add PHY_VPI=2 to Vptable*/ *pw = 0x3FF<<16 + 0x41; /*assign VCMASK/OFFSET for VPI=2*/ pvc = (UWORD *)(pimm->FCC1.VCT_BASE + 0x41 * 4); for (j=0; j=0x400; j++) /* init VC table to non-entry */ *pvc++ = 1<<31; /* Add the following VC entries */ /* VPI VCI Channel Code */ /* --- ------- ------------ */ /* 1 2 20 */ /* 1 0x12 21 */ /* 1 0xE4 22 */ /* 2 0x65 23 */ /* 2 0x1FF 24 */ /* 2 0x334 25 */

14-14

Solution - Initializing the Address Compression Tables (5 of 8) Add_VC(1,2,20); Add_VC(1,0x12,21); Add_VC(1,0xE4,22); Add_VC(2,0x65,23); Add_VC(2,0x1FF,24); Add_VC(2,0x334,25);}

14-15

Solution - Initializing the Address Compression Tables (6 of 8)UWORD GetVPpointer(PHY_VPI)UHWORD PHY_VPI;{ UHWORD j,k; /* temporary variables */ UWORD VPpointer; /* offset into Vptable */ UWORD *pvp; /* VP table entry pointer */

/* Calculate VPpointer for this PHY_VPI */ /* Algorithm: */ /* For each bit position, j, with a 1 in VP_MASK */ /* Anded with bit position j in PHY_VPI */ /* Put result into bit position k of VPpointer */ for (j=0,k=0; j<32; j++) if (pimm->FCC1.VP_MASK>>j & 1 == 1) /*if mask bit=1 */ { VPpointer |= (PHY_VPI>>j & 1)<<k; /*and-result to */ k++; /*VP pointer */ } pvp = (UWORD *)(pimm->FCC1.VPT_BASE + VPpointer*4); return(pvp);}


AssumedStructures

14-16

Solution - Initializing the Address Compression Tables (7 of 8)Add_VC(PHY_VPI,VCI,chno)UHWORD PHY_VPI,VCI,chno;{ UHWORD j,k; /* temporary variables */ UWORD VCpointer; /* offset into Vctable */ UWORD *pvp,*pvc; /* VP,VC table entry pointers */ UHWORD VC_MASK,VC_OFFSET; /* VC mask, VC offset */

pvp = (UWORD *)GetVPpointer(PHY_VPI); VC_MASK = *pvp>>16; VC_OFFSET = *pvp & 0xFFFF;/* Calculate VCpointer for this VCI */ /* Algorithm: */ /* For each bit position, j, with a 1 in VC_MASK */ /* Anded with bit position j in VCI */ /* Put result into bit position k of VCpointer */

14-17

Solution - Initializing the Address Compression Tables (8 of 8)

for (j=0,k=0; j<32; j++) if (VC_MASK>>j & 1 == 1) /* if the mask bit = 1 */ { VCpointer |= (VCI>>j & 1)<<k; /*and-result to */ k++; /*VC pointer */ } pvc = (UWORD *)(pimm->FCC1.VCT_BASE + VC_OFFSET*4 + VCpointer*4); /*init pointer to VC table entry */ *pvc = chno; /* assign channel number to VC entry*/}


AssumedStructures

14-18

Solution - Initialize for Peak and Sustain Rateptct = (tct *)((UWORD)pimm + pimm->FCC1.INT_TCT_BASE + 3 * 32); /* init pointer to tct */ptct->tcntrl1 |= 0x10; /* init for peak and sustain */ptct->pcr = 3; /* set peak cell rate to 3 */ptct->pcrf = 62; /* set fractional part to 62 */ptcte = (tcte *)((UWORD)pimm + pimm->FCC1.INT_TCTE_BASE + 3 * 32); /* init pointer to tcte */ptcte->scr = 9; /* set sustain cell rate to 9 */ptcte->scrf = 185; /* set fractional part to 185 */ptcte->bt = 6477; /* set burst tolerance to 6477*/ptcte->oobr = 20; /* set out of bufs resch to 20*/ptcte->srr = 0; /* clear sustain rate remaindr*/ptcte->vbr2 = 0x8000; /* resch CLP=1 cells PCR */

ExampleProgram

typedef __packed__(2,2) struct { UHWORD scr; /* SUSTAIN CELL RATE */ UHWORD bt; /* BURST TOLERANCE */ UHWORD oobr; /* OUT OF BUFFRS CELL RATE*/ UBYTE srr; /* SUSTAIN RATE REMAINDER */ UBYTE scrf; /* SUSTAIN CELL RATE FRACT*/ UWORD sr; /* USED BY CP */ UHWORD vbr2; /* VBR TYPE */ UHWORD vbrresrvd[9]; /* RESERVED, MUST BE 0 */} tcte; /* TRANSMIT CONNECTION TBL*/ /* EXTENDED VBR */

AssumedStructure

14-19

Solution - Handling a Channel Interrupt (1 of 3)In the exercise code below, fill in the blanks to complete a routine which handles an FCC1interrupt.UWORD *ptrtbl[4]; /* CPU pntrs to intprt queues */

/* FCC1 interrupt handler */fcc1esr(){ UHWORD er; /* temp FCCE1 register */ UWORD iqe; /* temp intrpt queue entry */ UHWORD iqno; /* temp variable */ WORD *pqpt,*piq; /* word pointers */ void intoesr(); /* intrpt overflow handler */ void busyesr(); /* handler for TIRU,GRLI,GBPB */ void chesr(); /* channel interrupt handler */

er = pimm->FCCE1; /* copy event register */ pimm->FCCE1 = er; /* clear known events */ if (er & 0xF != 0) /* if interrupt overflow queue */ intoesr(er); /* go to into handler */ if (er & 0xF00 != 0) /* if tx or global busy */ busyesr(er); /* go to busy handler */


14-20

Solution - Handling a Channel Interrupt (2 of 3)for (iqno=0; iqno<4; iqno++) /* for each of GINT bits */{ if ((er>>(iqno+4) & 1) == 0) /* if a GINT bit is 1 */ { piq = (WORD *)ptrtbl[iqno]; /*init pntr to int q entry*/ do /* for each valid entry */ { iqe = *piq; /* copy intrpt queue entry*/ *piq &= 0x7FFFFFFF; /* clear int que valid bit*/ chesr(iqe); /* handle channel intrpts */ if (iqe & 0x20000000 == 0) /* check if W=1 */ piq++; /* if not, increment pntr */ else /* if so, reinit pntr */ { pqpt = (WORD *) pimm->FCC1.INTT_BASE + iqno * 16); /* init pntr to int q param tbl */ piq = *pqpt; /*init pntr to INTQ_BASE */ } } while (*piq < 0); /* until an invalid entry */


__packed__(2,2) struct immbase { /*INTRNL MEMORY MAP */ . __packed__(2,2) struct { UWORD FCC1RES[16]; /* RESERVED */ . UWORD INTT_BASE; /*INT Q TBL BASE ADDR*/ . } FCC1; .};

AssumedStructures

14-21

Solution - Handling a Channel Interrupt (3 of 3) ptrtbl[iqno] = piq; /* update pntr table */ }}

14-22

Solution - How to Activate a Channel (2 of 2)

ActivationCode

Procedure 1. Initialize channel’s TCT (including TCT[VCON=1]) and buffer descriptors.2. Initialize COMM_INFO in parameter RAM3. Write the transmit command to the command register.

Write the code to activate channel 3 on PHY 2 for CBR and AAL5.Connection tables are on the local bus.pimm->FCC1.comm_info.chdata = 0x440;pimm->FCC1.comm_info.chcode = 3;pimm->CPCR = 0x11C1028A;

__packed__(2,2) struct immbase { /*INTRNL MEMORY MAP */ . __packed__(2,2) struct { UWORD FCC1RES[16]; /* RESERVED */ . __packed__(2,2) struct { UHWORD chdata; /*CTB,PHY#,ACT,PRI */ UHWORD chcode; /* CHANNEL NUMBER */ UHWORD bt; /* BURST TOLERANCE */ } comm_info; /* ATM XMIT COMMAND INFO */ . } FCC1; .};

AssumedStructures

14-23

Solution - UTOPIA ConfigurationProblem Configure FCC1 to operate with the following: 1) 8-bit master, 2) direct

polling (4 PHYs), and 3) fixed priority. Configuration is for both receive andtransmit.

Program /* Port registers are zero from reset */pimm->CMXFCR = 0x26000000; /* connect clocks */pimm->PSORC = 0x030f0000; /* init port registers*/pimm->PSORD = 0x01000004;pimm->PDIRA = 0x00003fcd;pimm->PDIRC = 0x030f0000;pimm->PDIRD = 0x0100b004;pimm->PPARA = 0x003fffff;pimm->PPARB = 0x00000000;pimm->PPARC = 0x030f0000;pimm->PPARD = 0x0100f004;pimm->CMXUAR |= 3<<(15-7); /* enbl FCC1 mastr pins*/pimm->FPSMR1 = 0x30638; /* enable UTOPIA modes*/

__packed__(2,2) struct immbase { /*INTRNL MEMORY MAP */ . UWORD FPSMR1; /* FCC1 PROTOCOL SPEC MODE */ . UWORD CMXFCR; /* FCC CLOCK ROUTE REG */ . UHWORD CMXUAR; /*UTOPIA ADDRESS REGISTER */ .};

AssumedStructures

14-24

Solution - Transmit OAM Cells Multi-PHY (1 of 2)In the exercise code below, fill in the blanks to complete a transmit an OAM cell tomultiple PHYs on FCC2./* Transmit an OAM cell to multiple PHYs */xmitoam(n1,n2)UHWORD n1,n2; /* first and last PHY numbers */{ struct descs { /* xmit buffer desc 0 */ txbdfa TxBD0; }; struct descs *pdsc; /* pointer to BD */

ptct = (tct *)((UWORD)pimm + pimm->FCC2.INT_TCT_BASE + 32); /* init tct pntr to tct1 */ pimm->FCC2.comm_info.chcode = 1; /* assign channel */ ptct->tcntrl1 |= 4; /* set VCON,AVCF already set */ pdsc = (descs *) (pimm->FCC2.BD_BASE_EXT + (ptct->tcntrl3) & 0x00FFFFF0); /* init pntr to descriptr*/ pdsc->TxBD0.txbdsac |= 0xA000; /* make BD ready,set wrap*/

14-25

Solution - Transmit OAM Cells Multi-PHY (2 of 2)In the exercise code below, fill in the blanks to complete a transmit an OAM cell tomultiple PHYs on FCC2.for (n = n1; n < n2; n++) { pimm->FCC2.comm_info.chdata = n<<5; pimm->CPCR = 0x15C1028A; /* FCC2 page,transmit */ while((pimm->CPCR & 1<<16) || (ptct->tcntrl1 & 1<<2)); /* wait for flag & VCON clr */ ptct->tcntrl1 |= 4; /* set VCON */ pdsc->TxBD0.txbdsac |= 0x8000; /* make BD ready */ }}

14-26

Solution -How to Locate a TDM’s SInRAM Entries (2 of 2)Exercise A system is to use TDMA1, B1, and D1, and TDMB2, and C2. No TDM,

transmit or receive will require more than 64 entries. Write the programto locate each TDM’s SInRAM entries.

pimm->SIA1MR |= 2<<(15-3);pimm->SIB1MR |= 4<<(15-3);pimm->SID1MR |= 6<<(15-3);pimm->SIB2MR |= 2<<(15-3);pimm->SIC2MR |= 4<<(15-3);

14-27

Solution - Allocate by TDMIntroduction In the exercise below, determine how MCCF1 and MCCF2 should be

programmed.

ExerciseAllocate the channels so that:

TDM Channels32-630-31

96-12764-95

192-223224-255128-159160-191

Channel Numbers

MCCF1MCCF2

pimm->MCCF1 = 0x4E;pimm->MCCF2 = 0xB1;

01 00 11 1010 11 00 01

128-159

160-191

192-223

224-255

1a1b1c1d2a2b2c2d

0001101100011011

0-31 32-63 64-95 96-127Gr 1 Gr 2 Gr 3 Gr 4

14-28

Solution - Programming SI_RAM for T1 (1 of 4)Introduction The example below shows how to program SI_RAM for T1 superchannels

for receive.

Example Program SI_RAM to receive a T1 frame on with the following routing:

1 0 0

1 0 0

1 0 0

1 0 0

1 0 0

1 24

1 2 3 4 5 4 4 4 6 4 2 19

SI

0

1

2

3

4

SI1RAM,Receive

7

TS

1

2

3

4

5

5 10

0 1 000 1

1 2 000 1

0 3 000 1

1 4 000 1

0 5 000 1

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

MCSEL CNT1 LOOP

SUP

BYT

LST

14-29

Solution - Programming SI_RAM for T1 (2 of 4)

1 0 0

1 0 0

1 0 0

1 0 0

1 0 0

SI

5

6

7

8

9

SI1RAM,Receive

1 0 0

1 0 010

11

1 0 012

1 0 022

1 0 123

TS

6

7

8

9

10

11

12

13

23

24

1 4 111 0

1 4 111 0

1 4 111 0

0 6 000 1

1 4 111 0

1 2 111 0

0 7 000 1

0 8 000 1

0 0x12 000 1

0 0x13 000 1

14-30


0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15MCSEL CNT1 LO

OPSUP

BYT

LST

SI1RAM,Transmit

1 0 00 1 2 1113

1 0 0

1 0 0

1 0 0

1 0 0

Superchannel Table

0

2

4

6

8

3 10

SI1RAM

SI

0

1

2

3

4

1 0 0

1 0 0 0xA

0xC

5

6

1 0 0

1 0 0 0xE

0x10

7

8

TS

1

2

3

4

5

6

7

8

9

0 1 000 1

1 2 000 1

0 3 000 1

1 4 000 1

0 5 000 1

1 20 111 0

1 21 111 0

1 22 111 0

0 6 000 1

-

-

2

-

4

-

-

-

-

14-31


SI1RAM,Transmit

1 0 00 1 2 1113

1 0 0

1 0 0

1 0 0

Superchannel Table

0x12

0x14

0x16

0x18

3 10

SI1RAM

SI

9

10

11

12

1 0 1

1 0 0 0x28

0x2A

20

21

TS

10

11

12

13

21

22

1 0 1

1 0 0 0x2C

0x2E

22

23

23

24

0x30

0x32

1 23 111 0

1 24 111 0

0 7 000 1

0 8 000 1

0 16 000 1

0 17 000 1

0 18 000 1

0 19 000 1

-

-

-

-

4

4

4

4

2

-

14-32

Solution - Initializing an MCC for Interrupts (1 of 2)Introduction In the exercise below, initialize MCC2 for the specified interrupts.

Exercise

pq = (qptr *) 0xA0000000; /* init xmit intrpt q*/for (j=0; j<20; j++) *pq++ = 0;*--pq = 1<<30;pimm->MCC2.TINTBASE = 0xA0000000; /*init xmit intrpt q base pntr */pimm->MCC2.TINTPTR = pimm->MCC2.TINTBASE; /*init xmit intrpt q actv pntr */pq = (qptr *) 0xA0000100; /* init recv intrpt q*/for (j=0; j<40; j++) *pq++ = 0;*--pq = 1<<30;pimm->MCC2.RINTBASE0 = 0xA0000100; /*init recv intrpt q base pntr */

Problem: Initialize MCC2 to respond to the following interrupts: globaloverrun and underrun, interrupt queue overrun for transmit and receivequeue 0, and transmit interrupt and receive queue 0 interrupt. Thetransmit queue is to be twenty entries long at 0xA0000000 and thereceive 0 queue, forty entries long at 0xA0000100.

14-33

Solution - Initializing an MCC for Interrupts (2 of 2)

pimm->MCC2.RINTPTR0 = pimm->MCC2.RINTBASE0; /*init recv intrpt q actv pntr */pimm->MCC2.GFRTHR = 5; /* init frame threshld*/pimm->MCC2.GFRCNT = pimm->MCC2.GFRTHR; /* init frame count */pimm->MCCM2 = 0xC00F; /*enbl glob,qov,xints*/

14-34

How to Enable Instruction Cache from Hard Reset

ExampleCode

From hard reset, the caches are invalidated and disabled. The instructioncache can be enabled using the following program:

mfspr r5,HID0 ;copy HID0 to gprori r5,r5,0x8800 ;set ICE and ICFIandi r6,r5,0xF7FF ;save ICFI offmtspr HID0,r5 ;invalidate and enableisyncsyncmtspr HID0,r6 ;clear flash invalidateisyncsync

14-35

Solution-Initialize MMU for BAT li r22,0 /* init gpr to zero */ mtspr IBAT0U,r22 /* invalidate IBAT0 */ mtspr IBAT1U,r22 /* invalidate IBAT1 */ mtspr IBAT2U,r22 /* invalidate IBAT2 */ mtspr IBAT3U,r22 /* invalidate IBAT3 */ mtspr DBAT0U,r22 /* invalidate DBAT0 */ mtspr DBAT1U,r22 /* invalidate DBAT1 */ mtspr DBAT2U,r22 /* invalidate DBAT2 */ mtspr DBAT3U,r22 /* invalidate DBAT3 */ lis r22,0xC800 /* init gpr for upper IBAT0L */ ori r22,r22,0x13 /* init gpr for lower IBAT0L */ mtspr IBAT0L,r22 /* init IBAT0L */ lis r22,0xC800 /* init gpr for upper IBAT0U */ ori r22,r22,0x7E /* init gpr for lower IBAT0U */ mtspr IBAT0U,r22 /* init IBAT0U */ lis r22,0xD248 /* init gpr for upper DBAT0L */ ori r22,r22,0x6A /* init gpr for lower DBAT0L */ mtspr DBAT0L,r22 /* init DBAT0L */ lis r22,0xE400 /* init gpr for upper DBAT0U */ ori r22,r22,0xF /* init gpr for lower DBAT0U */ mtspr DBAT0U,r22 /* init DBAT0U */ isync /* contaxt synchronize */

14-36

Solution - BAT Protection Example Three blocks are to be protected as follows: BAT0 is to be R/W:R/W, BAT1

is to be PT:R/O, and BAT2 is to be R/O:PT. Fill in the required protectionvalues in the table below.

Block VS VP PP

0 1 1 10

1 x1

2 x1

Exercise Two blocks are to be protected as follows: BAT0 is to be No access:PT, andBAT1 is to be R/W:R/W. Fill in the required protection values in the tablebelow.

0 1

1 0

Block VS VP PP

0 1 0 00

1 101 1

14-37

Solution - Page ProtectionExercise A segment is to have two valid pages as follows: page 1 is to be No

access:R/W, and page 2 is to be R/W:R/W. Fill in the required protectionvalues in the table below.

PageKS KP PP

11 0 00

2 10

14-38

Solution - Initializing a Page Table Entry (1 of 9)

/* THIS PROGRAM GENERATES A PAGE TABLE ENTRY AND THEN *//* ACCESSES THE PAGE TO CHECK THE RESULT. SINCE THE *//* SERVICE ROUTINE FOR A DATA MISS IS NOT INCLUDED, *//* WHEN A DATA MISS OCCURS, THE HASHX REGISTER IS *//* CHECKED TO VERIFY IT HAS THE SAME VALUE AS THE LO- *//* CATION OF THE PAGE ENTRY. */

struct PTE { int PTEU; /* FIRST WORD OF PTE */ int PTEL; /* SECOND WORD OF PTE */ };#define FALSE 0#define TRUE 1

14-39


main(){ int *pt; /* PT POINTER FOR CLEAR */ void invbat(); /* DECLARE INVBAT FUNCTION */ void invalidate(); /* DECLARE INVALIDATE FUNC */ int i; /* GENERAL VARIABLE */

invbat(); /* INVALIDATE BAT REGS */ asm(" lis r22,0"); /* INIT SR0 */ asm(" ori r22,r22,0x20"); /* TASK 2,SEG 0, NO PROT */ asm(" mtsr SR0,r22"); asm(" lis r22,0x3"); /* INIT SDR1 */ asm(" mtsdr1 r22"); /* LOCATE PT AT 0x30000 */ pt = (int *) 0x30000; /* INIT PNTR TO PAGE TABLE */ for(i = 0; i < 16384; i++) /* CLEAR PT */ *pt++ = 0; for(i = 0; i < 32; i++) invalidate(i<<12);

14-40


add_a_page(0x24000,0x80001000,0x00022082); /*ADD A PAGE,EA=0x24000, */ /*RA=0x22000,TASK 2,SEG 0 */ pt = (int *) 0x22100; /* CLEAR TEST LOCATION */ *pt = 0; asm(" mfmsr r22"); /* ENABLE DATA MMU */ asm(" ori r22,r22,0x10"); asm(" mtmsr r22"); asm(" isync"); pt = (int *) 0x24100; /* ACCESS PAGE */ *pt = 0x12345678; remove_a_page(0x24000,0x80001000,0x00022002); /* REMOVE PAGE */ *pt = 0x9ABCDEF0; /* ACCESS PAGE */}

14-41


void invbat(){ asm(" li r22,0"); /* INVALIDATE BAT REGS */ asm(" mtibatu 0,r22"); asm(" mtibatu 1,r22"); asm(" mtibatu 2,r22"); asm(" mtibatu 3,r22");// asm(" mtdbatu 0,r22"); asm(" mtdbatu 1,r22"); asm(" mtdbatu 2,r22"); asm(" mtdbatu 3,r22");}

void invalidate(i)int i;{ asm(" tlbie r3");}

14-42


add_a_page(ea,pteu,ptel)int ea,pteu,ptel;{ int hp,hs; /* PRIMARY AND SECONDARY HASH */ struct PTE *PTEGptr; /* POINTER TO PTEG GROUP */ int i; /* GENERAL VARIABLE */

hp = ((ea>>12) & 0xFFFF) ^ (getSR0() & 0x7FFFF); /* DETERMIN PRIMARY HASH VALUE*/ hs = ~hp; /* DETRMN SECONDARY HASH VALUE*/ PTEGptr = (struct PTE *) 0; /* INIT POINTER TO ZERO*/ PTEGptr = (struct PTE *)((getSDR1() & 0xFE000000) + (((hp>>10) & (getSDR1() & 0x1FF)) | (getSDR1() & (0x1FF<<16)) + ((hp & 0x3FF)<<6))); i = 0; while((PTEGptr->PTEU < 0) && (i++ < 8)) PTEGptr++;

14-43


if(PTEGptr->PTEU < 0) { pte0 |= 0x00000040; PTEGptr = (struct PTE *)((getSDR1() & 0xFE000000) + (((hs>>10) & (getSDR1() & 0x1FF)) | (getSDR1() & (0x1FF<<16)) + ((hs & 0x3FF)<<6))); i = 0; while((PTEGptr->PTEU < 0) && (i++ < 8)) PTEGptr++; } if(PTEGptr->PTEU >= 0) { PTEGptr->PTEU = pteu; PTEGptr->PTEL = ptel; return(0); } else return(1);}

14-44


remove_a_page(ea,pteu,ptel)int ea,pteu,ptel;{ int hp,hs; /* PRIMARY AND SECONDARY HASH */ struct PTE *PTEGptr; /* POINTER TO PTEG GROUP */ int i; /* GENERAL VARIABLE */ char found; /* BOOLEAN FLAG */

hp = ((ea>>12) & 0xFFFF) ^ (getSR0() & 0x7FFFF); /* DETERMIN PRIMARY HASH VALUE*/ hs = ~hp; /* DETRMN SECONDARY HASH VALUE*/ PTEGptr = (struct PTE *) 0; /* INIT POINTER TO ZERO*/ PTEGptr = (struct PTE *)((getSDR1() & 0xFE000000) + (((hp>>10) & (getSDR1() & 0x1FF)) | (getSDR1() & (0x1FF<<16)) + ((hp & 0x3FF)<<6))); i = 0; found = FALSE;

14-45


do if(PTEGptr->PTEU == pteu && PTEGptr->PTEL == ptel) found = TRUE; while (found == FALSE && i++ < 8); if(found == FALSE) { pte0 |= 0x00000040; PTEGptr = (struct PTE *)((getSDR1() & 0xFE000000) + (((hs>>10) & (getSDR1() & 0x1FF)) | (getSDR1() & (0x1FF<<16)) + ((hs & 0x3FF)<<6))); i = 0; do if(PTEGptr->PTEU == pteu && PTEGptr->PTEL == ptel) found = TRUE; while (found == FALSE && i++ < 8); }

14-46


if(found == TRUE) { PTEGptr->PTEL = 0; return(0); } else return(1);}

getSDR1(){ asm(" mfsdr1 r3");}

getSR0(){ asm(" mfsr r3,0");}

14-47

MCM6226B

Solution - Memory Controller GPCM PinsIn the diagram below, fill in the missing signal names to connect the two MCM6226Bsas a 128K by 16 memory. Properly terminate any unused signals. Add any additionallogic required.

A[0-31]D[0-63]

CS0*CS1*CS2*CS3*

PWE0*PWE1*PWE2*PWE3*PWE4*PWE5*PWE6*PWE7*

POE*PGTA*

A0A16DQ0DQ7E1*E2G*W*

A30A14D0D7

CS2*PULLUP

POE*PWE0*

MCM6226B

A0A16DQ0DQ7E1*E2G*W*

A30A14D8

D15CS2*

PULLUPPOE*

PWE1*MPC8260

14-48

DRAM

Solution - Memory Controller UPM PinsIn the diagram below, fill in the missing signal names to connect the two DRAMs as a1Mbyte by 16 memory to the local bus. Properly terminate any unused signals. Add anyadditional logic required.

L_A[14-31]LCL_D[0-31]

CS0*CS1*CS2*CS3*

LBS0*LBS1*LBS2*LBS3*LGPL0LGPL1

A0A9DQ0DQ7RAS*CAS*W*

L_A30L_A21

LCL_D0LCL_D7

CS3*LBS0*

LGPL1

DRAM

A0A9DQ0DQ7RAS*CAS*W*

L_A30L_A21

LCL_D8LCL_D15

CS3*LBS1*

LGPL1MPC8260

LGPL2LGPL3LGPL4LGPL5

14-49

What is the MODE-SET Command? (with Solution)Definition The mode-set command initializes the mode register in the SDRAM. The

value to go into the mode register is asserted on the address bus.

BlockDiagram

MODE Register in SDRAM P. 10-450 1 2 3 4 5 6 7 8 9 10 11

CL BLBT

Burst Length = 2,3, or 4

CAS Latency = 1,2, or 3

Write the code to initialize the x16 SDRAM Mode Register for CL = 2, BT= 0 and BL = 4. Assume the BR2, OR2, PSDMR have been setuppreviously (except PSDMR[OP]).

pimm->PSDMR &= 0xC7FFFFFF; /* clear OP bits */pimm->PSDMR |= 0x18000000; /* write MRS command */psdram = pimm->BR2 & 0xFFFF8000 + 0x24<<1; /* init pointer to SDRAM for MRS */*psdram = 0; /* write to SDRAM */pimm->PSDMR &= 0xC7FFFFFF; /* set normal operation */

Exercise

Burst Type = Sequential or Interleave

14-50

Solution - Determine the Address Configuration Parameter Values (1 of 4)Introduction The xDSMR and ORx contain a number of address configuration parameters

which can determined as shown below.

Procedure

Example

Step Action Results in values for...ORx[BPD]ORx[ROWST]ORx[NUMR]

Determine address bus partition1

256K x 16SDRAM

CLKCKECS*

RAS*CAS*WE*

A0-A8A9-BA

DQM

• 4 devices organized as 256K x 8 bytes• 2 banks• A9 and BA (bank address) are the same pin• A8 is the precharge pin

Determine the address configurationparameters for this memory.

xSDMR[SDAM]xSDMR[BSMA]xSDMR[SDA10]

Determine address bus during ACTIVATE2

14-51

Solution - Determine the Address Configuration Parameter Values (2 of 4)

Example(cont’d)

Size No. of Address Bits

Step 1: Determine Address Partition

2M 21

MSBs BS LSBsRow Address Column AddressA[0-10] A11 A[29-31]A[12-20] A[21-28]

Therefore:ORx[BPD] = 0 2 banksORx[ROWST] = 6 row starts at A12ORx[NUMR] = 0 9 row lines

Step 2: Determine Address Bus during ACTIVATEAddress bits A11 A[13-20]

MPC8260 pins A19 A[21-28]Memory pins A9 A[7-0]

Therefore:xSDMR[SDAM] = 0 Bit A20 - Pin 28xSDMR[BSMA] = 5 BS mux’d over to pin A19xSDMR[SDA10] = 0 Command address bit is A12

1 39 8Size

A12A20A8

14-52


Example(cont’d)

Address bits A11 A[21-28]MPC8260 pins A19 A[21-28]Memory pins BA A[7-0]

---

APSDA10

A8

MSBs BS LSBsRow Address Column AddressA[0-10] A11 A[29-31]A[12-20] A[21-28]

14-53


AddressConnections

A[0-7]

A8A9

256Kx16

A[21-28]

SDA10A19

A[0-7]

A8A9

256Kx16

A[21-28]

SDA10A19

A[0-7]

A8A9

256Kx16

A[21-28]

SDA10A19

A[0-7]

A8A9

256Kx16

A[21-28]

SDA10A19

14-54

Solution-How to Relatively Prioritize the SIU Interrupt SourcesExample Initialize for a priority so that IRQ1-5 are higher priority than the other SIU

sources.

PriorityMatrix

XS2PXS1P XS4PXS3P 0000 XS6PXS5P XS8PXS7P 0000TMCNT

PITPCI

IRQ1IRQ2IRQ3IRQ4IRQ5

011100

101110

111

000001

010

000001010011100101110111

011 100 101 110 0000 111 000 001 010 00007 2 E 0 E 0 A 0

BinaryHex

SIPPR

pimm->SIPPR = 0x72E0E0A0;

14-55

Solution - How to Spread the Priority

SpreadPriority

Lvl XSIU2 1

10 2

19 3

28 4

42 5

53 6

61 7

71 8

Lvl YCC

32 1

36 2

43 3

46 4

54 5

59 6

67 7

72 8

SICR[GSIU]=1 SICR[SPS]=1

Exercise Determine the correct value to write to the SICR if: 1) the SIU devices are tobe grouped, 2) the YCCs are to be spread, 3) the SDMA interrupt is to be thehighest priority interrupt (see p. 8-14)

pimm->SICR = 0xA01;

14-56

Solutions - Interrupts1. Complete the following initialization routine for interrupts from IRQ3 (assume resetconditions):

pimm->SICR += 0x1500; /* make irq3 highest priorty*/pimm->SIEXR |= 0x1000; /* make irq3 edge sensitive */pimm->SIMR_H |= 0x1000; /* enable irq3 intrpts */asm(“ mfmsr r3”); /* enable ppc extrnl intrpts */asm(“ ori r3,r3,0x8002”);asm(“ mtmsr r3”);

2. Complete the following service routine for interrupts from IRQ3:#pragma interrupt intbrnvoid intbrn(){ switch((pimm->SIVEC)>>(31-5) & 0x3F); /* process interrupt code */ { case 21: pimm->SIPNR_H |= 0x1000; /* clear irq3 pend bit */ /* do irq3 service */ break; default; } }

14-57

Solution - Handling a Port C, Pin 8 Interrupt (1 of 3)/* (PC8.C) */

#include "mpc8260.h" /* INTNL MEM MAP EQUATES */struct immbase *pimm; /* PNTR TO INTNL MEM MAP */static UWORD maskstack[10]; /* STACK BUFER FOR SIMASK*/static UWORD sp = 0; /* STACK BUFFER POINTER */

main(){ void isr(); /* EXCEPTION SERVICE RTN */ UWORD *ptrs,*ptrd; /* SOURCE & DEST POINTERS*/ pimm = (struct immbase *) (getimmr() & 0xFFFF0000); /* INIT PNTR TO IMMBASE */ ptrs = (int *) isr; /* INIT SOURCE POINTER */ ptrd = (int *)(getevt() + 0x500); /* INIT DEST POINTER */ do /* MOVE ESR TO EVT */ *ptrd++ = *ptrs; /* MOVE UNTIL */ while (*ptrs++ != 0x4c000064); /* RFI INSTRUCTION */ pimm->SICR = 0x30<<8; /* PC15 HIGHEST PRIORITY */ pimm->PDATD = 0; /* CLEAR PORT D DATA REG */ pimm->PDIRD = 0xff; /*MAKE PORT D24-31 OUTPUT*/ pimm->SIEXR |= 1<<(31-8); /* CONFIG PC8 INTRPT EDGE*/ pimm->SIMR_H |= 1<<(31-8); /* ENABLE PORT C,8 INTRPT*/

14-58

Solution - Handling a Port C, Pin 8 Interrupt (1 of 3) asm(" mfmsr r3"); /* ENABLE INTERRUPTS */ asm(“ ori r3,r3,0x8002”); asm(“ mtmsr r3”); while (1==1);}

#pragma interrupt isrvoid isr(){ /* save interrupt mask registers */ maskstack[sp++] = pimm->SIMR_H; maskstack[sp++] = pimm->SIMR_L; /* get interrupt code */ vecno = ((pimm->SIVEC)>>(31-5)) & 0x3F;

14-59

Solution - Handling a Port C, Pin 8 Interrupt (2 of 3) /* clear the source of the interrupt and mask */ /* priority interrupts */ switch (vecno) /*PROCESS INTERRUPT CODE*/ { case 0x37: pimm->SIPNR_H = 1<<(31-8); /*CLEAR PENDING BIT */ pimm->SIMR_H &= 0x00FFFCFF; /* MASK PC0-7,IRQ6-7 */ pimm->SIMR_L &= 0xFFFFA678; /* MASK IDMA3-4,TIMER3-4*/ /* SPI & SMC1-2 */ break; default; } /* save SRR0 and SRR1 on the stack */ asm(“ stwu r9,-12(r1)”); asm(“ mfspr r9,26”); asm(“ stw r9,4(r1)”); asm(“ mfspr r9,27”); asm(“ stw r9,8(r1)”); /* enable external interrupts and recoverable mode */ asm(“ mfmsr r9”); asm(“ ori r9,r9,0x8002”); asm(“ mtmsr r9”);

14-60

Solution - Handling a Port C, Pin 8 Interrupt (3 of 3) /* service interrupt */ switch (vecno) /*PROCESS INTERRUPT CODE*/ { case 0x37: pimm->PDATD += 1; /* INCREMENT LED COUNTER */ break; default; } /*disable external interrupts and recoverable mode*/ asm(“ mfmsr r9”); asm(“ andi r9,r9,0x7FFD”); asm(“ mtmsr r9”); /* restore SRR0 and SRR1 from the stack */ asm(“ lwz r9,8(r1)”); asm(“ mtspr 27,r9”); asm(“ lwz r9,4(r1)”); asm(“ mtspr 26,r9”); asm(“ lwz r9,0(r1)”); asm(“ addi r1,r1,12”); /* restore interrupt mask registers */ pimm->SIMR_L = maskstack[--sp]; pimm->SIMR_H = maskstack[--sp];}

14-61

Solutions - 60x Bus Exercises

AACK*ABB*ARTRY*BG*BR*DBB*DBG*DVAL*TA*TS*

The following questions assume that the 8260 is the arbiter.1. This pin is asserted by another bus master to request the bus: BR*2. This pin indicates to an external master that is has the bus on a qualified basis: BG*3. This pin indicates that a master has the address bus: ABB*4. This pin indicates that start of a new address tenure: TS*5. This pin is asserted by the slave to indicate the completion of the address tenure: AACK*6. This signal indicates that the bus transaction should be retried by the 60x bus master: ARTRY*7. This pin indicates that a master has the data bus: DBB*8. This pin indicates that a data beat is valid on the bus: DVAL*9. This pin indicates that an operand is complete on the data bus: TA*

Provide the answers to these questions... … from this list...

Documents

Exercise Solutions - nxp.com fileSMC1 base IDMA1base MCC2 SMC2 base IDMA2 base SPI base IDMA3 base Timers Rev_num D_ptr Rand I2C base IDMA4 base 8000 8400 8700 87FC 87FE 8800 88FC