Expected Performance Centering for Analog Designs

8/12/2019 Expected Performance Centering for Analog Designs

1/22

Expected Performance Centering forAnalog Designs

Expected Performance Centering forAnalog Designs

Bao Liu and Andrew Kahng

UC San Diego

http://vlsicad.ucsd.edu/~bliu


2/22

OutlineOutline

Existing Robust Analog Design Techniques

Expected Performance Centering

Statistical Computation Techniques

Experiments

Conclusion


3/22

VLSI VariabilityVLSI Variability

Increased variability in nanometer VLSI designs

Process:

OPC Lgate

CMP thickness

Doping Vth

Environment:

Supply voltage transistor performance Temperature carrier mobility and Vth

These (PVT) variations result in circuit performance

variation

p1

p2

PVT ParameterDistributions

d1

d2

Gate/net DelayDistribution


4/22

Analog Design Parametric Yield

Optimization

Analog Design Parametric Yield

Optimization Analog design

Complex metrics

Strong sensitivity to process variations

1. Robust programming

2. Stochastic programming

3. (explicit parametric yield optimization)

4. Design centering5. Performance centering

6. Taguchis quality loss function


5/22

Robust ProgrammingRobust Programming

Bound design and process parameter variations inpolyhedrons or ellipsoids

If the objective and the constraints are allposynomials, this is a geometric programming

Maximize f x

Subject to f x i m

g x i p

x i n

x u

x u i

i

i

sup ( )

sup ( ) , ,...

( ) , ,...

, ,...

=

= =

> =

0

1 1

1 1

0 1


6/22

Stochastic ProgrammingStochastic Programming

Explicit parametric yield maximization

Y = parametric yield

y = design metrics

U = design specifications

R = acceptability region

Maximize Y

Subject to Y y U x dx D x dx

D x x

R R

= < = =

=

Pr( ) Pr( ) ( )

( ) Pr( )


7/22

Design CenteringDesign Centering

Explicit parametric yield maximization

Yield gradient based greedy optimization

Recursive partition of ellipsoids

Recursive partition of polytopes

Maximum parameter distance (to boundaries of an

acceptability region in the design parameter space) Maximum parameter distance

maximum parametric yielde.g. 15% Lgate variation

Max distanceMax yield


8/22

Performance CenteringPerformance Centering

Maximum distance to the boundaries of theperformance acceptability region in the

performance space

Performance targeting yield maximization

Performance centering

Design centering

U

y=f(x)


9/22

Taguchis Quality Loss FunctionTaguchis Quality Loss Function

Increases as the circuit performance deviates fromthe target performance

Reducing performance variability as a means forbothparametric yield maximization andperformance targeting

What is the domain of the qual ity loss func t ion?

Taguchi chooses minimum quality loss

Target performance

U

y=f(x)


10/22

OutlineOutline


Expected Performance Centering Statistical Computation Techniques

Experiments

Conclusion


11/22

Expected Performance MarginExpected Performance Margin

Expected performance margin in the presence of

design parameter variation P(x) is given by

x = design parameters

= variations y = design metrics

U = performance constraints

R = acceptability region

= performance margin

( ) ( ) Pr( ) ( ( )) Pr( )x x x d U y x x dR

i i i

R

= + + = + +


12/22

Expected Performance MarginExpected Performance Margin

For extremely small variabilities, e.g., P(x+)=()

expected performance margin = performance margin For extremely small performance margin (x) =

Expected performance margin = parametric yield Expected performance margin Taguchis quality

loss function

( ) ( ) ( ) ( )x x d xR

= + =

( ) Pr( )x x d YR

= + =


13/22

Expected Performance CenteringExpected Performance Centering

Given

Design parameters x

Design parameter variabilities Pr(x+)Performance constraints y < U

Find design parameters x* such that the expected

performance margin is maximized

Maximize x x x d

Subject to x U y xy x U x R i

x

R

i i i

i i

( ) ( ) Pr( )

( ) ( ( ))( ) , ,

= + +

+ = ++ +

0


14/22

Expected Performance CenteringExpected Performance Centering

Inp ut: x Pr(x+), y < U Outpu t: x* s.t. f(x*) is maxim ized

1. Cons t ruct a performance macromodel y = f (x)

2. Find acceptabi l i ty region boundar ies y = f(x) = U

3. Compu te per formance margin (x)

4. Compu ter expected per formance margin (x )5. Find maximum expected per formance margin (x*)


15/22

Expected Performance Margin

Computation

Expected Performance Margin

Computation Sampling

posynomial geometric programming Gaussian integral

if y = f(x) is polynomial, Pr(x) is Gaussian

Surface integral

sampling i i i ii

N

N

U y x a= + ==

1

1

( ( ))

1

2

1

2 2

2

22

0

e d erf

zz =

( )

( )

( ) ( ( )) Pr( ) ( ( )) ( )

( ) Pr( )

x U y x x d U y x D x d

D x x

i i i

R

i i i

R

= + + = + +

=


16/22

OutlineOutline




Experiments

Conclusion


17/22

Experimental SetupExperimental Setup

Three-inverter ring oscillator

Synopsys HSpiceRF simulator

70nm Berkeley Predictive Technology Model

Performance metrics:

Oscillation frequency f0 > 1GHz

Phase noise N < 40dB

Power consumption P < 1mW

Delay parameters

Transistor channel width and length


18/22

Experimental ResultsExperimental Results

Acceptability region and performance contours

Design Center

Expected Perf. Center

Perf. Center


19/22

ExperimentsExperiments

I. Design centering

II. Performance centering

III. Expected performance centering

= performance margin = expected performance margin

3.00

3.04

2.91

L

79.76

80.33

75.37

67.12128.0II

III

I

128.0

128.0

W

67.53

65.42


20/22

OutlineOutline




Experiments

Conclusion


21/22

SummarySummary

We propose maximum expected performance

margin as a new analog design objective

performance targeting in the presence of smallprocess variations

parametric yield maximization (design centering)for small performance margin

Taguchis quality loss function

Expected performance margin computation andmaximization methods


22/22

Thank you !Thank you !

Documents

Expected Performance Centering for Analog Designs