Gunma University Kobayashi Lab 1

Sept. 17, 2014 19th IEEE IMS3TW, Porto Alegre, Brazil

Experimental Verification of a Timing

Measurement Circuit With Self-Calibration

Kateshi Chujyo, Daiki Hirabayashi, Kentaroh Katoh

Conbing Li, Yutaroh Kobayashi, Koshi Sato

Haruo Kobayashi

Gunma University, Tsuruoka National College of Tech

Hikari Science

Supported by STARC

Outline

• Research Background

• ＴＤＣ Circuit and Problems

• Histogram Method Self-Calibration

• Analog FPGA Implementation

• Measurement Results

• Conclusions

2

Outline

• Research Background

• ＴＤＣ Circuit and Problems

• Histogram Method Self-Calibration

• Analog FPGA Implementation

• Measurement Results

• Conclusions

3

Research Background

Advanced CMOS VLSI

● Low power-supply voltages

● Fast switching speeds

Voltage domain

Fine CMOS

Time domain

time

Fine CMOS time

A Time-to-Digital Converter (TDC) provides a digital output

proportional to the time between two clock transitions.

The TDC is a key component in time-domain analog circuits,

（e.g. Sensor Interfaces, All-Digital PLLs, ADCs, .. ）

4

Supply

voltage

Research Objective

Validate TDC linearity self-calibration

with histogram method

All-digital implementation

Suitable for fine CMOS

Experimentally validate design with FPGA

5

Outline

• Research Background

• ＴＤＣ Circuit and Problems

• Histogram Method Self-Calibration

• Analog FPGA Implementation

• Measurement Results

• Conclusions

6

Flash-type TDC

T

START

STOP

τ

τ

τ

τ τ τ

T

𝑫𝟎 = 𝟏

𝑫𝟏 = 𝟏

𝑫𝟐 = 𝟎

𝑫𝟑 = 𝟎

7

● Digital output (Dout)

proportional to time difference

between rising edges (T)

● Time resolution τ

Dout=2

Dout=1

Delay Cell Variation Inside TDC Circuit

Delay cell variation Δτk

(a) Without delay variation (ｂ) With delay variation

T T

t t

D Q

t t t

D Q D Q D Q

D1 D2 D3 D4

+Dt1 +Dt2 +Dt3 +Dt4 +Dt5

TDC nonlinearity

8

Random Variation among Delay Cells

• Delay τ variation

Relative variation

TDC nonlinearity

Absolute（average value) variation

TDC input range & time resolution

• Focus on Relative variation here.

9

Outline

• Research Background

• ＴＤＣ Circuit and Problems

• Histogram Method Self-Calibration

• Analog FPGA Implementation

• Measurement Results

• Conclusions

10

Research Objective (revisited)

Dout(0)=1

Dout(1)=3

Dout(2)=5

Dout(3)=8

・

・

Dout(0)=0.3

Dout(1)=2.8

Dout(2)=4.5

Dout(3)=7.3

・

・

Calibration Corrected

based on

delay

variation

evaluation

• TDC linearity self-calibration with histogram

• Analog FPGA（PSoC） implementation, evaluation

11

TDC with Self-Calibration

Test mode

“0” or “1”

t1 t2

D Q

t3 t4

D Q D Q D Q D Q D Q

M U X START

STOP

D Q

Encoder

t23 t24

24

Histogram Engine

12 To histogram database

Dout

Normal Operation Mode

t1 t2

D Q

t3 t4

D Q D Q D Q D Q D Q

M U X START

STOP

Test mode

“0” or “1” D Q

Encoder

t23 t24

Dout

13

Self-Calibration Mode

t1 t2

D Q

t3 t4

D Q D Q D Q D Q D Q

M U X START

STOP

Test mode

“0” or “1” D Q

Encoder

t23 t24

f2

f1 Ring oscillator

Histogram Engine

External clock

14 To histogram database

Self-Calibration

Self-calibration mode

START, STOP signals

are NOT synchronized

# o

f “

1” o

utp

ut

Code

22 20 18 16 22 20 18 16 20 18 16

0

500

1000

1500

2000

2500

3000

Histogram data in all bins will be equal,

after collection of a sufficiently large number of data,

if the TDC has perfect linearity

15

t1 t2

D Q

t3 t4

D Q D Q D Q D Q D Q

M U X START

STOP

Test mode

“0” or “1”

D Q

t23 t24

• Probability of digital code for large delay is high.

• Probability of digital code for small delay is low.

• START (ring oscillator) and STOP signals are asynchronous.

f1

Principle of TDC Linearity Calibration

16

Self-Calibration

Histogram

TDC digital output

2tD

t

3tD

4tD

5tD

1tt D2tt D 3tt D

4tt D

TDC is non-linear delay

D Q D Q D Q

17

Each bin of histogram

Varies with

corresponding

delay value

Principle of Self-Calibration

T

n)(TfDout

Histogram

TDC digital output

Histogram of ideally

Histogram

TDC digital output

Nonlinear TDC

① ②

③ ④

Linearized by inverse function

T

n

Linear TDC

INL calculation

18

0 2 4 6 8 10 12 14 16 18 20 220

0.5

1

1.5

2

2.5x 10

6

Simulation Result of Self-Calibration

before calibration

code

Sampling points 28,848,432

ps69601 ～tns102 t

0 2 4 6 8 10 12 14 16 18 20 220

0.5

1

1.5

2

2.5x 10

6

after calibration

code

MATLAB

Histogram for each bin is the same

when the TDC is linear.

# o

f “

1” o

utp

ut

# o

f “

1” o

utp

ut

19

Outline

• Research Background

• ＴＤＣ Circuit and Problems

• Histogram Method Self-Calibration

• Analog FPGA Implementation

• Measurement Results

• Conclusions

20

Implementation of TDC with Self-Calibration

Variable capacitor

array for individual

cell delays

Capacitor and

var. resistor for

loop (ring) delay

Programmable System-on-Chip (PSoC) 5LP

and external components

21

TDC Control Circuit in PSoC

Reference clock

Generation of

START, STOP signals

for test purpose

PWM for

self-calibration

stop signal

Control register

for control mode change

22

START, STOP Generation for TDC Evaluation

48MHz reference clock inside PSoC

START

STOP

Program control

・ Divide reference clock

・ Timing difference of N x 20.8ns

Use for TDC linearity evaluation

CLKref

48MHz Reference Clock

Precise timing signal generation

N x 20.8ns

(48/N) MHz

Divided clock

START STOP

ＴＤC and Ring Oscillator Circuit

To encoder

5.6kΩ 0～120pF

24

Each

delay To encoder

To

encoder

Encoder Circuit

Thermometer code to binary code

25

Thermometer

code

Detection of

transition

from 1 to 0

Encode to binary code

Data Processing Software

• C♯ program

• Data were transferred via USB to a PC and

processed there.

26

Outline

• Research Background

• ＴＤＣ Circuit and Problem

• Histogram Method Self-Calibration

• Analog FPGA Implementation

• Measurement Results

• Conclusions

27

Histogram in Calibration Mode

• Total number of data: 40934

• Average number of data for each bin: 1700

0

500

1,000

1,500

2,000

2,500

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Histogram data for experiment

28

Bin

Histogram

Sample #1

0

5

10

15

20

25

30

0 2,000 4,000 6,000 8,000 10,000 12,000 14,000 16,000

系列1

TDC Measurement Without Calibration

Non-linearity

29

Sample #1

START, STOP Rising Edge Timing Difference [ns]

TDC

Digital

Output

Actual Delay Data by Direct Measurement

0

100

200

300

400

500

600

700

800

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

30

Sample #1

Delay Cell

Delay

Value

[ns]

Correlation Between Histogram and Delay

0

200

400

600

800

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Delay Cell

Histogram and Delay Measurement Results

-15

-10

-5

0

5

10

15

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24誤差（％）

Delay Cell

Error between Delay and Histogram (%)

13%

31

Histogram

Delay

TDC Characteristics Before and After Calibration

32

[ns]

Digital

output

Time difference between two clock rising edges

Sample #1

INL Before and After Calibration (1)

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

0 5 10 15 20 25

16.4%

57.5%

33

Sample #1

INL

before

calibration

INL

after

calibration

INL

TDC digital

output code

INL Before and After Calibration (2)

34

Sample #5 Sample #4

Sample #3 Sample #2

Outline

• Research Background

• ＴＤＣ Circuit and Problem

• Histogram Method Self-Calibration

• Analog FPGA Implementation

• Measurement Results

• Conclusions

35

Conclusion

• A TDC with self-calibration was implemented

using an analog FPGA.

• Measurement results showed

Linearity improved by self-calibration.

• All-digital implementation is possible.

Suitable for fine CMOS

BOST for timing signal test

36

Altera FPGA (Full digital Implementation)

37

TDC with histogram method self-calibration

Delay cell array was implemented with a CMOS inverter chain.

INL Before and After Self-Calibration

38

-0.1000

-0.0500

0.0000

0.0500

0.1000

0.1500

1 2 3 4 5 6 7

INL

TDC digital

output code

Measurement results

Before

calibration

After

calibration

Gunma University Kobayashi Lab 39

Sept. 17, 2014 19th IEEE IMS3TW, Porto Alegre, Brazil

Thank you for kind attention

We are analog design & test researchers,

but we appreciate digital technology.

Time continues indefinitely.