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Exploiting Device Cache Hit Behavior in IO Scheduling
Taeho Hwang O Jongmin Kim Youjip Won
Depart. of Electronics Computer Engineering, Hanyang University
.
.
.
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1.
.
. RAID [1]
PCIe SSD (Solid State Drive)[2]
512MB 16GB
DRAM .
NAND
.
.
NAND , Phase Change RAM[3], STT-MRAM[4]
.
.
.
.
2.
. ,
.
.
.
.
.
.
. (i)
. (ii)
. (iii)
.
2.1.
. 1 Fusion IO SSD 4KB
.
Core i7 930 CPU, DDR3 8G ,
2.6.32 .
.
2011 Vol.38, No.1(B)
TSC (Time Stamp Counter) . TSC
85ns
. 1
.
.
. 28us
46us . 28us
, 46us
.
.
40KB 4KB .
.
1.
: FusionIO [5]
2.2.
.
.
.
2.3.
.
.
. ,
.
LRU
.
.
.
LRU
3.
. FusionIO SSD
.
.
4. Acknowledgements
2010 ( )
( NRL) (No.
2010-0018893).
1. INTEL,
.
2. Josephson, W.K., et al.,
ACM Transactions on
Storage (TOS), 2010. 6(3): p. 1-25.
3. Moinuddin, K.Q., S. Vijayalakshmi, and A.R.
Jude.
. in
. 2009. Austin, TX, USA: ACM.
4. Li, J., et al.
. in
. 2008:
ACM.
5. FUSIONIO,
2011 Vol.38, No.1(B)
