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Exploiting Free LUT Entries to Mitigate Soft Errors in SRAM-based FPGAs. Gengxin Hua, Hongjin Liu, Bo Liu Beijing Institute of Control Engineering. Keheng Huang, Yu Hu, Xiaowei Li Institute of Computing Technology Chinese Academy of Sciences. 2011-11-23. Purpose. - PowerPoint PPT Presentation
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ATS
Exploiting Free LUT Entries to Mitigate Soft Errors in SRAM-
based FPGAs
Keheng Huang, Yu Hu, Xiaowei Li
Institute of Computing Technology
Chinese Academy of Sciences
Gengxin Hua, Hongjin Liu, Bo Liu
Beijing Institute of Control
Engineering
2011-11-23
Purpose
• Soft error mitigation scheme .
• SRAM-based FPGAs
• Utilize logic masking effect
• During logic synthesis
• Without additional area overhead
Outline
• Background .
• Motivation
• FEC-based soft error mitigation scheme
• Experimental results
• Conclusions
Outline
• Background .
• Motivation
• FEC-based soft error mitigation scheme
• Experimental results
• Conclusions
Background
• Architecture of SRAM-based FPGAs .
S Wire segment
CLB CLB
CLB
CLB Configurable Logic Block
(a) Architecture of SRAM-based FPGAs
CLB
S Switch box
Background
• Architecture of SRAM-based FPGAs .
.
.
.
MUXsANDFFs Output
LUT
entry0: CBentry1: CB
entry14: CBentry15: CB
(b) Configurable Logic Block
S Wire segment
CLB CLB
CLB
CLB Configurable Logic Block
(a) Architecture of SRAM-based FPGAs
CLB
S Switch box
Background
• Architecture of SRAM-based FPGAs .
W1
Wi
E1
Ei
S1 Sj
N1 Nj
.
.
.
CB
CB
CB
CB
CB
CB
CB
CB
CB
CB
.
.
.
CB
CB
. . .
. . .
(c) Switch box
.
.
.
MUXsANDFFs Output
LUT
entry0: CBentry1: CB
entry14: CBentry15: CB
(b) Configurable Logic Block
S Wire segment
CLB CLB
CLB
CLB Configurable Logic Block
(a) Architecture of SRAM-based FPGAs
CLB
S Switch box
Background
• Architecture of SRAM-based FPGAs .
.
.
.
MUXsANDFFs Output
LUT
entry0: CBentry1: CB
entry14: CBentry15: CB
(b) Configurable Logic Block
W1
Wi
E1
Ei
S1 Sj
N1 Nj
.
.
.
CB
CB
CB
CB
CB
CB
CB
CB
CB
CB
.
.
.
CB
CB
. . .
. . .
(c) Switch box
S Wire segment
CLB CLB
CLB
CLB Configurable Logic Block
(a) Architecture of SRAM-based FPGAs
CLB
S Switch box
SRAM bits97% 3%
Background
• Architecture of SRAM-based FPGAs .
S Wire segment
CLB CLB
CLB
CLB Configurable Logic Block
(a) Architecture of SRAM-based FPGAs
CLB
S Switch box
.
.
.
MUXsANDFFs Output
LUT
entry0: CBentry1: CB
entry14: CBentry15: CB
(b) Configurable Logic Block
W1
Wi
E1
Ei
S1 Sj
N1 Nj
.
.
.
CB
CB
CB
CB
CB
CB
CB
CB
CB
CB
.
.
.
CB
CB
. . .
. . .
(c) Switch box
70%
The reliability of routing resources is of great importance, and needs to be seriously considered
SRAM bits97% 3%
Background
• FPGA EDA flow .
Design specification
Gate-level netlist
Bit Stream
Synthesis and mapping
Placement and routing
Background
• FPGA EDA flow .
Design specification
Gate-level netlist
Bit Stream
Synthesis and mapping
Placement and routing
ROSE[Hu, ICCAD’08], IPR[Feng, ICCAD’09], R2[Jose, DAC’10] Boolean matching High computational complexity
Dual-output resynthesis[Lee, ASP-DAC’10] LUT Dual-output encoding Relies on dual-output feature of FPGAs
Outline
• Background .
• Motivation
• FEC-based soft error mitigation scheme
• Experimental results
• Conclusions
Motivation
• There are a lot of free LUT entries (all 6 LUT
inputs are used%=43.71%), which can be
used to mitigate soft errors
0
10
20
30
40
50
60
70
80
90
100
53.80%
Circuit name
LUT6 LUT3 LUT5 LUT2 LUT4 LUT1
Perc
enta
ge o
f L
UT
s
43.71%
.
.
.
entry0: CBentry1: CB
entry62: CBentry63: CB
Outline
• Background .
• Motivation
• FEC-based soft error mitigation scheme
• Experimental results
• Conclusions
FEC-based soft error mitigation
• Logic masking effect .
(a) Logic masking effect in logic gate
(b) Logic masking effect in LUT
0
0
In0
In1
0 1Out
0entry0 00 0
entry1 01 0
entry2 10 0
entry3 11 10 1
0
In0
In1Out
entry addr CB
FEC-based soft error mitigation
• Address Hamming Distance .
– The Hamming Distance between the
addresses of two LUT entries
• If (H[addr(entry0, entry2)]=H[00,10]=1) &&
the configuration bits are the
same
Then, the fault at corresponding inputs will be
logic masked0
entry0 0
entry1 0
entry2 0
entry3 10 1
0
In0
In1Out
FEC-based soft error mitigation
• Flowchart of the
design .
Logic synthesis and technology mapping
Placement and routing
FPGA implementation
Baseline Flow
Cube-based reliability analysis
Are there any notfully-occupied LUTs
New Flow
FEC-based soft error mitigation
Circuit
FEC replacement EstablishingFEC model
FEC-based soft error mitigation
• Establishing FEC models .
(a) Original LUT
(b) FEC 1.0 model (F0>F1)
entry0 00 0 entry1 01 1
addr CBentry
In0
Out
No. of fault effect propagation vectors=F0+F1
In0 SA0: F0SA1: F1
entry2 10 0 entry3 11 1
entry2 10 0 entry3 11 1
entry0 00 0 entry1 01 0
addr CBentry
In0
In1 In0 SA0: F0SA1: 0
In1 SA0: F0SA1: 0
No. of fault effectpropagation vectors=F0+F0
∆F=F1-F0
Out
(c) FEC 1.1 model (F1>F0)
entry2 10 1 entry3 11 1
entry0 00 0 entry1 01 1
addr CBentry
In0
In1In0 SA0: 0
SA1: F1
In1 SA0: 0SA1: F1
No. of fault effect propagation vectors=F1+F1
∆F=F0-F1
Out
FEC-based soft error mitigation
• Establishing FEC models .
(a) Original LUT
entry0 00 0 entry1 01 1
addr CBentry
In0
Out
No. of fault effect propagation vectors=F0+F1
In0 SA0: F0SA1: F1
entry2 10 0 entry3 11 1
entry6 110 1 entry7 111 1
entry4 100 0 entry5 101 1
entry2 010 0 entry3 011 1
entry0 000 0 entry1 001 0
addr CBentry
In0
In1
In2
In0 SA0: 0SA1: 0
In1 SA0: 0SA1: 0
In2 SA0: 0SA1: 0
No. of fault effect propagation vectors=0
∆F=F1+F0
Out
(d) FEC 2 model
FEC-based soft error mitigation
• Cube-based reliability analysis .
– Evaluate the reliability of each LUT input
• FEC replacement with most reliability improvement– One free LUT input
• FEC 1.x:
– Two free LUT inputs• FEC 2:
– More than two LUT inputs• Combination of FEC 1.x and FEC 2
∆F=MAX|F0-F1|
∆F=MAX|F0+F1|
Keheng Huang, Yu Hu, Xiaowei Li, “Cross-layer Optimized Placement and Routing for FPGA Soft Error Mitigation,” in Proc. of DATE, 2011. pp.58-63
Outline
• Background .
• Motivation
• FEC-based soft error mitigation scheme
• Experimental results
• Conclusions
Experimental results
MCNC benchmark set
Synthesis andmapping : Berkeley ABC mapper
Gate-level netlist
SRAM bits
Architecture of FPGA: 4 6-input LUTs/CLB Virtex like routing
Hardware: Xeon 6GB Workstation Software: Java
Placement andRouting : VPR toolset
Experimental results
• Area .– # of LUTs
• Soft Error Rate (SER)– Cube-based reliability analysis
• Critical-path delay
– Reported by VPR
• Computational complexity– Runtime
Experimental results
• Area .– # of LUTs– No area
overhead
• SER : reduced by 21.72% .
ROSE:25%IPR:49%Dual-output
27%
Experimental results
nets
nets
0
prop
0 inputs
*
( * )*
N
i ii
N
ii
SER NER EPP
Nr NCB
N
resynthesis:
• Critical-path delay .– Reported
by VPR– Increased by
4.25%
Experimental results
• Computational
complexity .– Runtime : 28.83ms
ROSE:184.2sIPR:5.58sDual output
6s
Experimental results
resynthesis:
Outline
• Background .
• Motivation
• FEC-based soft error mitigation scheme
• Experimental results
• Conclusions
Conclusions
• FEC-based soft error mitigation .
– Mitigate Soft Errors in FPGA
• Reduce SER by 21%
– Small performance overhead• Critical-path delay increase: 4.25%
– No area overhead (exploiting free LUT entries)
– Does not rely on specific FPGA devices• Suitable for all LUT based FPGAs
• Q & A