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Exploring a CPLD/FPGA-based Triggering System for LCLS. Matthew T. Brown Office of Science, Science Undergraduate Laboratory Internship Program Advisor: Ron Akre. CPLD/FPGA Basics. Gates Macrocells LUTs JTAG Programmer Xilinx ISE. Xilinx Cool Runner XPLA XCR3064XL. - PowerPoint PPT Presentation
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Exploring a CPLD/FPGA-based Triggering System for LCLS
Matthew T. BrownOffice of Science, Science Undergraduate Laboratory Internship Program
Advisor: Ron Akre
CPLD/FPGA Basics
Gates Macrocells LUTs JTAG Programmer Xilinx ISE
Xilinx Cool Runner XPLA XCR3064XL
Xilinx Spartan 3 XC3S200PQ208-5
The Task at Hand
360Hz fiducial signal Set delays Triggering requirements
– Delay– Pulse length– Jitter
How It’s Done
24-bit counter Comparators Flip flops Design entry
– Schematic – Text (VHDL code written for 8 channels)
Simple Timing Diagram
Schematic Example
CPLD Results
Not good enough!
FPGA Results
FPGA Results Strike Back
Jitter measured to be below 2 picoseconds
Return of the FPGA Results
Onboard Arcturus Coldfire Processor
Four DCMs on the chip allow for sub-clock cycle phase adjusting for the triggers
Conclusion and Possible Future Work
CPLD = No
FPGA = Yes
Need to:– Build a board with all 8 channels on it– Complete the computer-FPGA interface
Acknowledgements
Thanks to Ron Akre, Jeff Olsen, Bo Hong, and Anatoly Krasnykh for help on this project.
Thanks to Steve Rock, Susan Schultz, and Farah Rahbar for managing us kids and the SULI program at SLAC.
Questions?
Sources:– http://supercomputing.fnal.gov/slac_logo.jpg– http://images.amazon.com/images/P/6305428387.01.LZZZZZZZ.jpg– http://therawfeed.com/pix/this_is_sparta.jpg