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Exploring the Rogue Wave Phenomenon in 3D Power Distribution Networks. Xiang Hu 1 , Peng Du 2 , Chung-Kuan Cheng 2 1 ECE Dept., 2 CSE Dept. University of California, San Diego 10/25/2010. Agenda. Introduction System-level 3D PDN analysis Chip-level 3D PDN analysis - PowerPoint PPT Presentation
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Exploring the Rogue Wave Phenomenon in 3D PowerDistribution Networks
Xiang Hu1, Peng Du2, Chung-Kuan Cheng2
1ECE Dept., 2CSE Dept.
University of California, San Diego
10/25/2010
Page 2
Agenda
Introduction
System-level 3D PDN analysis
Chip-level 3D PDN analysis
– Detailed 3D power grid model
– Frequency-domain analysis
– Time-domain analysis
Conclusions
Page 3
Introduction
Power delivery issues in 3D ICs
– Total currents flowing through off-chip components increase with the number of stacked tiers
– 3D-related components (i.e., TSV, µbump) add more impedance to on-chip power grids
Previous power grid models for on-chip noise analysis are relatively simple
– Missed detailed metal layer information
– Not suitable for 3D PDN analysis
Detailed 3D PDN analysis has not been done
– Frequency domain: resonance behavior
– Time domain: worst-case noise
Page 4
System-Level 3D PDN model
Power delivery system including VRM, board and package
Multiple input current sources
Zext
Page 5
Impedance Profiles in System-Level 3D PDN Model
Common resonant peaks at VRM-board, board-package, and package-T1 interfaces.
No high-frequency peak for Z11.
High-frequency peak for Z22 due to T1-T2 resonance.
Small high-frequency bumps for Z12 and Z21 due to T1-T2 resonance.
105
1010
0
5
10
15
Frequency (Hz)
Impe
danc
e (m
)
Z11
Z22
Z12
or Z21
VRM-brdbrd-pkg
pkg-T1
T1-T2
Page 6
Chip-Level 3D Power Grid Model
Power grid
– structure: M1, M3, M7, RDL
– Extracted in Q3D
TSV: RLC model
Package: distributed RLC model
Page 7
2D PDN 3D PDN
Package inductance (Lp) 52.5pH 52.5pH
Total on-chip cap (Cc) 7.92nF 7.92nF
246.9MHz 246.9MHz
Current Source @ T1, Output Voltage @ T1
Measured on-chip impedance on device layer, i.e., M1
2D PDN
– Large impedance at low frequencies due to high resistive M1
– Only one resonance peak at package-die interface
3D PDN
– Small impedance at low frequencies due to low resistive RDL on T2
– Mid-frequency resonance peak at package-die interface
– Large high-frequency resonance peak around T2T location
105
106
107
108
109
1010
1011
0
0.5
1
1.5
2
2.5
3
Frequency (Hz)
Vol
tage
(V
)
3D case (Two tiers)2D case (Tier 1 only)
2D PDN vs. 3D PDN
241.73MHz
243.59MHz
_ 1/ (2 )res pc p cf L C
Estimated package-die resonant frequency
Page 8
Current Source @ T1, Output Voltage @ T1
High-frequency resonance peak
– Caused by the inductance of T2T connection and the local decoupling capacitance around it.
– Highly-localized: beyond 40um the peak disappears (bypassed by other decaps around the current source)
23.62GHz
Single TSV inductance: 34pHLocal capacitance on M1: 1.159pFEstimated resonant frequency: 25.4GHz
Page 9
Current Source @ T1, Output Voltage @ T2
Small low-frequency impedance
Global mid-frequency resonance peak at package-T1 interface
Global high-frequency resonance peak at T1-T2 interface
105
106
107
108
109
1010
1011
0
0.1
0.2
0.3
0.4
0.5
0.6
Frequency (Hz)
Imp
ed
an
ce (
) Same (x,y) coordinatesas the T1 current source
At the corners of T2((250m, 250m) to
the T1 current sourcein (x,y) directions)
Effective TSV inductance: 2.83pHTotal capacitance on T2: 25.96pFEstimated resonant frequency: 18.56GHzT1-T2: 20.26GHz
pkg-T1: 245.5MHz
Page 10
Current Source @ T2, Output Voltage @ T2
Large impedance at current source location due to high-resistive M1
Global mid-frequency resonance peak at package-T1 interface
– Caused by the anti-resonance between package inductance and total on-chip capacitance
Global high-frequency resonance peak at T1-T2 interface
– Caused by the anti-resonance between T2T inductance and T2 total capacitance
105
106
107
108
109
1010
1011
0
1
2
3
4
5
6
7
8
Frequency (Hz)
Vo
ltag
e (
V) Further awayfrom the
current source
16.8m to the current sourcein x direction
8.4m to the current sourcein x direction
Current source location
Page 11
Current Source @ T2, Output Voltage @ T1
Large impedance at T2T locations
– T2 current concentrates on the limited number of T2T locations
Local high-frequency resonance peak at T2T locations
Global mid-frequency resonance peak at package-T1 interface
105
106
107
108
109
1010
1011
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Frequency (Hz)
Imp
ed
an
ce (
)
T2T locations on T1
Other locations on T1
(8.4m,47.9m) tothe current sourcein (x,y) directions
(176.4m,153.7m) to the current sourcein (x,y) directions
Page 12
On-Chip Worst-Case PDN Noise Prediction Algorithm
Motivation
– Local current on M1 is tiny consider the distributed current effect
– Obtain worst-case noise at multiple on-chip locations
Single-input worst-case PDN noise prediction algorithm [1]
– Basic idea: dynamic programming
Multi-input worst-case PDN noise prediction algorithm
– Extension of the single-input algorithm
– Based on noise superimposition of the linear PDN model
[1] P. Du, X. Hu, S. H. Weng, A. Shayan, X. Chen, A. E. Engin, and C.K Cheng. “Worst-Case Noise Prediction With Non-Zero Current Transition Times for Early Power Distribution System Verification,” In IEEE International Symposium on Quality Electronic Design, 2010
Page 13
On-Chip Worst-Case PDN Noise Flow
Current source locations
Simulate impulse responses
All current sources traversed?
Select an output node
Calculate the worst-case noise
More output nodes?
Current constraints
PDN netlist
Pick one current source
Worst-case noise map
Page 14
Worst-Case Noise Experiment Setting
Two-tier 3D PDN
9 uniformly distributed current sources on each tier
Same (x,y) current source locations on two tiers
First and last columns of the current sources locate at the same (x,y) coordinates as T2T connections
Current constraints
– Maximum amplitude: 0.1mA
– Minimum transition time: 10ps
Page 15
Worst-Case Noise Map on T1
Currents from T2 cause large noise around T2T interface.
Currents at T2T locations on T1 cause local high-frequency resonance peaks, making the noise worse.
0100
200300
400500
600
0
100
200
300
400
500
6000.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Y (m)
X (m)
Wo
rst-
case
no
ise
(m
V)
peak value
Page 16
Worst-Case Noise Map on T2
Uniform worst-case noise peak at nine current source locations
T2T distribution has no impact on the worst-case noise peak distributions on T2
Worst-case noise on T2 is 20 times of that on T1
peak value
0100
200300
400500
600
0
100
200
300
400
500
6009
10
11
12
13
14
15
16
17
18
Y (m)
X (m)
Wo
rst-
case
no
ise
(m
V)
Page 17
Rogue Waves: Time-Domain Worst-Case Noise Waveforms
Three output locations:
– Blue: T2T location on T1
– Red: Away from T2T locations on T1
– Black: T2
Worst-case noise response: low-frequency oscillations followed by high-frequency oscillations Rogue Wave
Worst-case noise response is dependent on the resonance behaviors of the output nodes and the spatial distribution of current sources
– Output nodes on T2 (black): high-frequency oscillation followed by low-frequency oscillation due to global high-frequency resonance
– Output nodes on T1
• T2T location (blue): high-frequency oscillation followed by low-frequency oscillation due to local high-frequency resonance
• Away from T2T (red): no high-frequency oscillation
Page 18
Worst-Case Noise Flow Run Time
Node # Impulse response simulation time
Worst-case noise calculation time
Total run time
75815 1.55 hr/current 115 sec/node 1.55 hr*N+115 sec*M
N: number of current sourcesM: number of output nodes
Page 19
Conclusions
System-level analysis reveals the global resonance effects for 3D PDNs
Proposed on-chip 3D power grid model with detailed metal layer
Local resonance phenomenon due to T2T connection inductance and local capacitance is discovered with the detailed 3D power grid model
Worst-case noise calculation algorithm is extended to multiple input multiple output system
Worst-case noise map shows the spatial distribution of the worst-case noise in 3D PDNs
The “rogue wave” of worst-case noise response reflects the resonance behaviors at different locations of the 3D PDN
Page 20
Thank You!Q & A