Fabrication and Doping of Silicon Micropillar Arrays for Solar Light Harvesting Rick Elbersen

Rick Elbersen Fabrication and Doping of Silicon M

icropillar Arrays for Solar Light Harvesting 2015

Fabrication and Doping of Silicon Micropillar Arrays for

Solar Light Harvesting

Invitation

I cordially invite you to attend the public defense of my PhD thesis entitled:

Fabrication and Doping of Silicon Micropillar

Arrays for Solar Light Harvesting

on Friday,4th of December, 2015

at 16:45 hWaaier zaal 4

University of TwenteEnschede

Prior to the defense, I will give a short introduction to my thesis at 16:30 h

Rick [email protected]

Paranymphs:

Jasper van [email protected]

Wouter [email protected]

Rick Elbersen

FABRICATION AND DOPING OF

SILICON MICROPILLAR ARRAYS FOR

SOLAR LIGHT HARVESTING

Rick Elbersen

Promotiecommissie:

Prof. dr. ir. Hans Hilgenkamp (voorzitter) Universiteit Twente

Prof. dr. ir. Jurriaan Huskens (promotor) Universiteit Twente

Prof. dr. Han Gardeniers (promotor) Universiteit Twente

Prof. dr. Marlies van Bael Universiteit Hasselt

Prof. dr. Ernst Sudhölter Technische Universiteit Delft

Prof. dr. ir. Wilfred van der Wiel Universiteit Twente

Prof. dr. Guido Mul Universiteit Twente

Dr. ir. Mark Huijben Universiteit Twente

This work is part of the research programme of the Foundation for

Fundamental Research on Matter (FOM, project 115-10TBSC07-2), which is

part of the Netherlands Organization for Scientific Research (NWO). It was

carried out within the framework of the national program on BioSolar Cells,

co-financed by the Dutch Ministry of Economic Affairs, Agriculture, and

Innovation.

Fabrication and doping of silicon micropillar arrays for solar light harvesting

ISBN: 978-90-365-4007-0

DOI: 10.3990/1.9789036540070

Cover art: Martin Binnema

Printed by: Gildeprint – The Netherlands

© Copyright 2015 Rick Elbersen

FABRICATION AND DOPING OF

SILICON MICROPILLAR ARRAYS FOR

SOLAR LIGHT HARVESTING

PROEFSCHRIFT

ter verkrijging van

de graad van doctor aan de Universiteit Twente,

op gezag van de rector magnificus,

prof. dr. H. Brinksma,

volgens besluit van het College voor Promoties

in het openbaar te verdedigen

op vrijdag 4 december 2015 om 16.45 uur

door

Rick Elbersen

geboren op 6 januari 1987

te Deurne, Nederland

Dit proefschrift is goedgekeurd door de promotoren:

Prof. dr. ir. Jurriaan Huskens (promotor)

Prof. dr. Han Gardeniers (promotor)

Table of Contents

Solar Energy Applications of Silicon ........................................... 9 Chapter 1

1.1. Introduction ............................................................................................. 9

1.2. Aims of the research............................................................................. 13

1.3. References ........................................................................................... 15

Fabrication and Doping Methods for Silicon Nano- and Chapter 2

Micropillar Arrays for Solar Light Harvesting: A Review .......................... 17

2.1. Introduction ........................................................................................... 18

2.2. Optimized micro/nanopillar designs for solar-to-fuel conversion ......... 18

2.3. Fabrication of silicon nano/micropillars ................................................ 22

2.4. Doping of silicon ................................................................................... 30

2.5. Junction analysis .................................................................................. 36

2.6. Optical and electrical characterization ................................................. 41

2.7. Conclusions .......................................................................................... 46

2.8. References ........................................................................................... 47

Controlled Doping Methods for Radial p/n Junctions in Silicon Chapter 3

Micropillars .................................................................................................... 51

3.1. Introduction ........................................................................................... 52

3.2. Materials and methods ......................................................................... 53

3.3. Results and discussion ......................................................................... 59

3.4. Conclusions .......................................................................................... 69

3.5. References ........................................................................................... 71

Effects of Pillar Height and Junction Depth on the Performance Chapter 4

of Radially Doped Silicon Pillar Arrays for Solar Energy Applications ... 73

4.1. Introduction ........................................................................................... 74



4.4. Conclusions .......................................................................................... 84

4.5. References ........................................................................................... 85

Electrical Characterization of Silicon Micropillars with Radial Chapter 5

p/n Junctions Containing Passivation and Anti-Reflection Coatings ...... 87

5.1. Introduction ........................................................................................... 88



5.4. Conclusions ........................................................................................ 104

5.5. References ......................................................................................... 106

Spatioselective Electrochemical and Photoelectrochemical Chapter 6

Functionalization of Silicon Microwires with Axial p/n Junctions ......... 107

6.1. Introduction ......................................................................................... 108

6.2. Materials and methods ....................................................................... 110

6.3. Results and discussion ....................................................................... 113

6.4. Conclusions ........................................................................................ 121

6.5. References ......................................................................................... 123

Summary and Outlook ................................................................................ 125

Samenvatting en Visie................................................................................. 127

Appendix A ................................................................................................... 131

A.1. Process flow radial junctions .............................................................. 131

A.2. Process flow axial junctions ............................................................... 139

Dankwoord ................................................................................................... 145

Curriculum Vitae .......................................................................................... 149

Publications ................................................................................................. 150

9

Chapter 1

Solar Energy Applications of Silicon

1.1. Introduction

One of the world‟s major challenges currently is to switch from an oil-based

economy to a more sustainable alternative energy economy. Many different

types of renewable energy, such as wind energy, biomass, blue energy and

solar energy, are gaining interest and start to compete with fossil fuels. For

example, the electrical power generated by the use of solar energy in the

Netherlands increased twelve-fold between 2005 and 2013.[1]

In addition,

under the 2009 EU Renewable Energy Directive, The Netherlands has

committed to provide at least 14% of their total energy consumption from

renewable energy in 2020.[2]

To achieve this goal, a great effort in both

research and business is required to make renewable energy sources more

attractive, and this is a trend that is visible worldwide.

One of the possible sustainable alternatives is the photovoltaic (PV) cell, which

has already been under investigation since the first p/n junction was fabricated

in 1954 in the Bell laboratories.[3]

In a PV cell, light is converted into electricity

in three stages. First, the light is absorbed, generating an electron/hole pair.

Secondly, the electron/hole pair is separated, and finally the charge carriers

are extracted from the PV cell by an external circuit. PV cells can use the light

of the sun as an energy source, meaning that there is basically an unlimited

source of energy available. PV cells can be made from a variety of materials,

for example crystalline silicon, gallium arsenide and organic materials. All of

these different materials have already been subjected to intensive research, as

shown by the National Renewable Energy Laboratory (NREL, based in the

US). Since 1975, they have been keeping track of best research-cell

efficiencies, as shown in Figure 1.1.[4]

Chapter 1

10

Figure 1.1: Overview of the best performing solar cells (in terms of efficiency) for various

materials and setups.[4]

The efficiencies shown in Figure 1.1 are based on research-scale devices, and

the figure provides no information about the ease of fabrication or the total cost

per area unit or per kWh, meaning that the highest efficiency is not always the

most practical option. From a commercial point of view, silicon is by far the

most used material for PV cells, as it accounts for about 90% of the total

production, as of 2013.[5]

Silicon has several advantageous properties, for

example, it is abundant, non-toxic, low cost and widely known in the

nano/micro-fabrication world. The availability of different fabrication and

deposition techniques to modify silicon surfaces offers many possibilities to

enhance the PV characteristics of silicon.[6-8]

Unfortunately, the production of solar electricity rarely matches to the actual

demand. On a sunny afternoon, there is a surplus of energy, whereas during

the night there is a shortage, as there is no electricity generated. This

imbalance between production and demand is schematically shown in

Figure 1.2. To prevent loss of a large excess of solar power, the surplus

electricity can be stored in batteries or used to generate a fuel, for example, by

coupling a solar cell to an electrolyzer.


11

Figure 1.2: Expected solar energy production and demand over a day, on an average

sunny day.[9]

Another solution would be to make an integrated device that captures light to

split water into oxygen and hydrogen as the fuel. The latter is known as a

solar-to-fuel (S2F) device, and it already has been proven to function in lab-

scale.[10,11]

S2F devices could provide the solution to the gap between energy

generation and demand, as the chemical energy of a fuel is the most

condensed form of energy and can be transported and stored for later use. A

general S2F device requires the coupling of various processes, i.e. light

harvesting, charge separation and charge carrier transport to different

catalysts, for the oxidation of water and reduction of protons. In theory, the

splitting of water would require a photovoltage of more than 1.23 V, but

practically at least 0.6 V extra is required, to drive the water oxidation and

reduction at normal current densities obtained from 1 sun (15-25 mA/cm2).

[12]

There are two possible options for a S2F device, a single semiconductor

absorber or a tandem device, where two semiconductors are connected. The

energy scheme for both options is shown in Figure 1.3. In the case of a single

semiconductor, a fairly large (>2.0 V) bandgap material is required, and this

leaves out much of the solar spectrum. This results in a lower overall

Chapter 1

12

efficiency, estimated at about 10% in literature.[12,13]

For a tandem device,

where two semiconductors are used, two (smaller) bandgaps result in a larger

photon collection, at the cost of recombination, as the quantum yield is

reduced. For a tandem device with one smaller (~1.2 eV) and larger (~1.9 eV),

the maximum practical water splitting efficiency can reach up to 15%.[12,13]

Silicon has a bandgap of 1.1 eV, which makes it an interesting candidate for

the lower bandgap material.

Figure 1.3: Energy scheme for both a single absorber (left) and a tandem system (right)

for photocatalytic water splitting. In addition to the required bandgap width, the bandgap

position should also match the required potentials for the water oxidation and the

hydrogen reduction steps. A single absorber would require a band gap of 2.0 eV, whereas

the tandem system can use two lower bandgap materials instead, but the process requires

2 photons for the generation of 1 electron/hole pair. Reproduced with permission.[11]

Copyright 2011, Cambridge University Press.


13

1.2. Aims of the research

In this thesis, we aim to gain knowledge on and improve the fabrication of

silicon solar energy devices, in terms of the micro/nano-structuring and doping

of silicon as a semiconductor material. In addition, we explore options to

further improve the properties and functionalities of PV cells, keeping in mind

that these can possibly be used as a platform for S2F devices as well.

The thesis has been structured as follows:

Chapter 2 gives a state-of-the-art literature overview of the fabrication and

doping of structured silicon PV cells. Emphasis is placed on the fabrication

limitations of common techniques and the analysis of different doping

techniques for 3D silicon structures.

In Chapter 3, the fabrication of radially doped p/n junctions in silicon

micropillars is described. The doping was performed by several methods, such

as low-pressure chemical vapor deposition (LPCVD), solid source dotation

(SSD) and plasma-enhanced chemical vapor deposition (PECVD). In addition,

the formation of the silicon p/n junctions was simulated by finite element

modeling, and experimentally analyzed on both flat and 3D structures. Finally,

the electrical properties of flat and pillar array substrates were compared, for

both p/n and n/p junctions.

The optimization of these radially doped silicon micropillars, in terms of pillar

height and junction depth, is reported in Chapter 4. First, the height of the

pillars was varied between 0 and 60 µm, using fabrication and doping methods

as described in Chapter 3. Secondly, by adjusting the doping time and

temperature, the junction depth was varied between shallow (140 nm) and

large (1640 nm) depths. The effects of both pillar height and junction depth

were analyzed subsequently by electrical measurements.

Chapter 5 continues with the optimization of the silicon micropillar arrays, by

the use of a passivation and anti-reflection coating. The reflectivities of thin

films of various materials (Al2O3, SiO2 and SiNx) were simulated to predict the

Chapter 1

14

optimal thickness for light trapping. Subsequently these layers were grown on

flat silicon wafers, using atomic layer deposition and low-pressure chemical

vapor deposition, to verify the simulations. Similar deposition experiments

were performed on silicon micropillars, followed by a detailed study by

high-resolution scanning electron microscopy to investigate the 3D deposition

characteristics. Finally, the electrical properties were measured and compared

to bare samples, to identify and quantify the improvement of the performance

achieved by the passivation layers.

In Chapter 6, the possibility to functionalize silicon with metal nanoparticles

has been explored, by using the electrodeposition of platinum and silver.

Unlike the previous chapters, where silicon micropillars with radial junctions

were used, this chapter made use of axial junctions. The selective

functionalization of both the p- and n-type parts was proven, where first

platinum was deposited on the bottom p-type part, followed by the silver

deposition on the top n-type part, without the use of any masking step.

Finally, the main conclusions of the work presented in this thesis are briefly

described, followed by an outlook for future research.


15

1.3. References

[1] Renewable energy; capacity, domestic production and use, 1990-2013

(http://statline.cbs.nl/StatWeb/publication/?DM=SLEN&PA=71457ENG), Accessed 16th

of June, 2015.

[2] Promotion of the use of energy from renewable sources (http://eur-lex.europa.eu/legal-

content/EN/TXT/?qid=1434448431833&uri=URISERV:en0009), Accessed 16th of June,

2015.

[3] D. M. Chapin, C. S. Fuller, G. L. Pearson, J. Appl. Phys., 1954, 25, 676-677.

[4] Best Research-Cell Efficiencies (http://www.nrel.gov/ncpv/images/efficiency_chart.jpg),

Accessed 16th of June, 2015.

[5] Photovoltaics Report Fraunhofer Institute

(http://www.ise.fraunhofer.de/de/downloads/pdf-files/aktuelles/photovoltaics-report-in-

englischer-sprache.pdf), Accessed 16th of June, 2015.

[6] B. Tian, X. Zheng, T. J. Kempa, Y. Fang, N. Yu, G. Yu, J. Huang, C. M. Lieber, Nature,

2007, 449, 885-889.

[7] S. Pillai, K. R. Catchpole, T. Trupke, M. A. Green, J. Appl. Phys., 2007, 101, 093105

[8] E. Garnett, P. Yang, Nano Lett., 2010, 10, 1082-1087.

[9] Solar power: Generation and own power consumption (http://bosch-solar-

storage.com/independence/self-reliance/), Accessed 17th of June, 2015.

[10] S. Y. Reece, J. A. Hamel, K. Sung, T. D. Jarvi, A. J. Esswein, J. J. H. Pijpers, D. G.

Nocera, Science, 2011, 334, 645-648.

[11] G. Mul, C. Schacht, W. P. M. van Swaaij, J. A. Moulijn, Chemical Engineering and

Processing: Process Intensification, 2012, 51, 137-149.

[12] F. E. Osterloh, B. A. Parkinson, MRS Bulletin, 2011, 36, 17-22.

[13] M. F. Weber, M. J. Dignam, Int. J. Hydrogen Energy, 1986, 11, 225-232.

16

This chapter has been adapted from: R. Elbersen, W.J.C. Vijselaar, R.M.

Tiggelaar, J.G.E. Gardeniers, J. Huskens, Adv. Mater., 2015, doi:

10.1002/adma.201502632

17

Chapter 2

Fabrication and Doping Methods for

Silicon Nano- and Micropillar Arrays for

Solar Light Harvesting: A Review

Silicon is one of the main components of commercial solar cells and is used in

many other solar light harvesting devices. The overall efficiency of these

devices can be increased by the use of structured surfaces that contain

nanometer to micrometer sized pillars with radial p/n junctions. High densities

of such structures greatly enhance the light absorbing properties of the device,

whereas the 3D p/n junction geometry shortens the diffusion length of minority

carriers and diminishes recombination. Due to the vast silicon nano- and

microfabrication toolbox that exists nowadays, many versatile methods for the

preparation of such highly structured samples are available. Furthermore, the

formation of p/n junctions on structured surfaces is possible by a variety of

doping techniques, in large part transferred from microelectronic circuit

technology. The right choice of doping method, to achieve good control of

junction depth and doping level, can attribute to an improvement of the overall

efficiency that can be obtained in devices for energy applications. This paper

presents a review of the state-of-the-art of the fabrication and doping of silicon

micro and nanopillars, as well as of the analysis of the properties and

geometry of thus formed 3D structured p/n junctions.

Chapter 2

18

2.1. Introduction

Since the 1970s, silicon has been under investigation for the use in solar cell

applications. Lately, this research has been expanded to the area of solar

fuels, where a higher efficiency of the light absorber has a large impact on the

total efficiency of the solar-to-fuel device. In this review, we summarize the

state-of-the-art of fabrication and doping methods for nano- and micro-sized

silicon pillar arrays. A discussion is provided of the optimal design parameters

for such devices, based on computational modeling work. This is followed by

an overview of techniques used to fabricate arrays of silicon nano- and/or

micropillars. Finally, an evaluation is given of the different doping methods that

exist for the creation of p/n junctions in silicon micro or nanostructures and of

the techniques available to analyze such junctions, with a focus on doping of

3D structures.

2.2. Optimized micro/nanopillar designs for solar-to-fuel

conversion

Recently, pillar arrays of silicon have gained attention for solar energy

applications because of their increased light harvesting properties, compared

to flat surfaces. This is due to their higher surface area and efficient light

trapping by multiple interactions of the light within the gaps between the pillars,

even at relatively small pillar aspect ratios. Furthermore, if the pillars have a

radial junction, the effective junction area is increased, which leads to

enhanced charge carrier generation and separation. Finally and perhaps most

importantly, the radial junction decouples the charge transport and light

incidence direction, reducing the chance of recombination.[1-3]

In order to

obtain the best possible solar cell/solar-to-fuel devices, many parameters need

to be optimized, such as the emitter (introduced doping layer) and base wafer

doping levels, junction depth and profile, as well as the dimensions of the

pillars, in terms of height, pitch and diameter. A typical design consists of

Fabrication and Doping Methods for Silicon: a Review

19

arrays of nano- or micro-sized pillars, with contacts to measure or extract the

current and to control the voltage.

2.2.1. P/n junctions in silicon

The use of a radial junction in silicon pillars is the most efficient junction

orientation, as was elaborated theoretically by Kayes et al. in 2005,[4]

and is

therefore the main geometry considered in this review. Simulations of the

effect of junction depth on the efficiency of solar cells were performed in 1991,

in the work of Durán, where a flat silicon solar cell was simulated in order to

predict the optimum junction depth at a given surface dopant concentration.[5]

Although the difference between the best and least performing junction depths

(0.4 µm vs 1.0 µm, respectively) is small (18.6% vs 18.3%), their data shows a

trend that thinner junctions perform slightly better. In more recent publications

on simulations of junctions depths, this trend is confirmed: smaller junction

depths result in higher currents, and thus higher overall efficiencies.[6-8]

Figure 2.1 shows an overview of the influence of the emitter doping level, the

junction depth and minority carrier diffusion length, on the open circuit voltage

(VOC) and short-circuit current density (JSC) for a textured solar cell.[6]

The

authors suggested an optimized emitter doping of 1x1020

cm-3

, as a trade-off

between a higher VOC and efficiency on the one hand and the manufacturing

feasibility of such high doping levels on the other hand. In addition to a high

doping concentration, a shallow junction depth should be used, however, no

numerical limitation was proposed.[6]

Overall, simulations indicate that a thin

junction, combined with a high surface doping level, is most efficient.[6]

A high

dopant concentration in the junction ensures better charge separation and

therewith a higher open circuit voltage. However, a high doping level also

reduces the minority carrier diffusion path length and enhances the amount of

recombination sites, and the thicker the junction the stronger this effect will be.

Chapter 2

20

Figure 2.1: Simulations of various parameters of a textured silicon solar cell. (a) JSC and

overall efficiency as a function of the emitter doping level, (b) JV characteristics for varying

emitter widths (junction depths) and (c) VOC and JSC plotted for a range of minority carrier

diffusion lengths. Reproduced with permission.[3]

Copyright 2011, American Institute of

Physics.

2.2.2. Pillar designs for optimal light absorption

Already by the human eye, it is visible that arrays of silicon micropillars absorb

more light than a flat sample, because the reflectivity decreases significantly.

Most of the research in the direction of optimized pillar arrays has been

performed on pillars with feature sizes in the range of the wavelength of light,

because such pillars have long optical paths for efficient light absorption and

short carrier transit times. For these nanopillars, the effects of pillar

morphology[9]

and dimensions such as diameter, length[8,10,11]

and pitch[12]

on

the absorption properties have been investigated. For example, arrays of

amorphous silicon nanopillars and -cones were simulated and their reflectivity

was compared with a flat thin film of amorphous silicon.[13]

The nanopillars and

cones had a diameter of 300 nm, where the cones had a gradual decrease in

diameter toward their tops, down to 20 nm. Such pillars and cones were also

fabricated and comparison of experimental with the simulated data showed

that the reflectivity of the thin film is significantly higher than that of the

nanopillar samples and the difference is even stronger for the nanocones.

One of the most important factors to decrease reflectivity is the ratio between

the diameter (D) and the pitch (P) of the pillars.[6,14,15]

For any given height of a

pillar, it is claimed that the D/P ratio should be between 0.5 and 0.8, where the

latter shows the highest efficiency.[14,15]

The overall efficiency can be increased

by increasing the height of the pillars, in which case the feasibility of fabrication

of such long pillars seems to be the main limiting factor.


21

Furthermore, for a given D/P ratio, a thinner diameter – within a range of

270 to 380 nm – and smaller pitch is expected to result in a higher

efficiency.[14]

This trend was not in agreement with other simulations, in which

an optimum of 2 micron for the pillar diameter was found.[15]

In all studies discussed above, symmetry was always present in the design of

the array of pillars, i.e. one set of pillar dimensions was used and the pillars

were placed in ordered arrays (hexagonal, triangular, square etc.). However,

order is not necessarily the optimal configuration.[16]

By reducing the diameter

of half of the pillars, the authors were able to increase the absorbance of

arrays with two different pillar radii. In another example, it was proposed that

random, non-ordered pillar arrays have advantages over ordered structures,

such as enhanced absorption for arrays with low areal packing fractions.[17]

Summarizing, although many simulation studies aim at the prediction of the

effect of individual device design variables, such as pillar diameter and height,

array packing density, doping profile and junction depth, there is no overall and

consistent picture of the optimal device design for photovoltaic conversion. It

would be beneficial to the field to have a generalized framework of simulation,

with a fixed set of parameters, to be used for validation of pillar-based designs

and prediction of possible limitations of such designs. Since the performance

of silicon pillar arrays depends in a highly convoluted manner on design

aspects such as pillar dimensions, pitch, doping level and junction depth,

simulations of the combined effects of these parameters could help predict

which systems are of potential interest for practical application. In addition,

such efforts could reveal if there is a clear relationship between the different

design parameters, for example, whether the pillar shape would influence the

optimal configuration of a pillar array. At the moment, there is no clear

indication whether the nano or micron scale is more suited, neither for solar

cells nor for solar-to-fuel applications, and sometimes research involves a

combination of both micro- and nanoscale structures.[18,19]

In addition, it is not

yet clear what is the effect of the many different fabrication and doping

methods. This can potentially cause differences in terms of the quality of the

Chapter 2

22

silicon, resulting in differences in, for example, charge carrier density, diffusion

lengths and defect levels.

2.3. Fabrication of silicon nano/micropillars

There are many ways to produce arrays of nano- and micro-sized silicon

pillars, and in this section, an overview is given of the main techniques that

have been employed, namely dry etching, wet etching, and vapor-liquid-solid

growth.

2.3.1. Dry etching

In general, prior to dry etching, a pattern with the desired dimensions is

created in a protective layer on the silicon substrate, which acts as an etch

mask. Most commonly, standard UV photolithography is used to transfer the

desired mask pattern into a layer of photoresist, mostly followed by a post-

bake of the photoresist.[20-24]

Dry etching of the mask pattern in silicon, by a

combination of bombarding its surface with reactive ions and the chemical

etching of reactive species (i.e. radicals), leads to the desired structures. The

most common form of dry etching is (deep) reactive ion etching (D)RIE, which

uses chemically reactive plasmas (e.g. SF6, O2, C4F8) in a vacuum chamber as

a source to dissolve exposed silicon. This can be done either in a continuous

flow of reactive gases (cryogenic etching) or with alternating etching and

passivation gases (Bosch process, shown in Figure 2.2).[25]

Figure 2.2: Typical deep reactive ion etching scheme for the Bosch process. (A) After

definition of a mask on the silicon surface, etching and passivating gasses are introduced

alternatingly. (B) These processes are cycled until the desired height has been achieved,

after which the patterned mask and fluorocarbon contamination are removed. (C) Zoom-in

of the pillars, showing the typical sidewall scalloping, resulting from the cyclic Bosch

process.


23

Although dry etching is a well-known technique, various factors (e.g. aspect

ratio, total area to be etched and RIE lag) affect the realization of high aspect

ratio structures, as described in a review by Rangelow et al.[26]

If the DRIE

process has been tuned correctly, almost no under-etch of the mask will occur,

and the pillar cross-section will be the same as the pattern in the etching

mask. The structures etched into silicon typically have a diameter of at least a

few microns in the case of UV lithography, whereas the heights can go up to

several tens of microns.[27]

The method also allows pillars with sub-micron

diameters, the limiting factor being the scalloping due to the cyclic steps in the

Bosch process. For sub-micron features, deep-UV lithography (Figure 2.3) (or

another method described below) is needed.[28]

Figure 2.3: Side view scanning electron microscopy (SEM) image of silicon micropillars

etched with DRIE, using a mask made with deep UV lithography. Scallops are visible at

the top of the pillar, which is an artifact from the Bosch process. Reproduced with

permission.[28]

Copyright 2012, Elsevier.

Instead of photoresist, other materials can also function as masking layer,

such as a "hard mask" of silicon nitride or silicon oxide, into which a pattern is

created by photolithography and etching, before the sample is exposed to

DRIE.[29]

The use of a hard mask avoids the problem of flowing of the resist,

Chapter 2

24

which can occur at longer process times or higher process temperatures,

conditions needed to obtain higher aspect ratios. Alumina is an excellent

alternative hard mask layer, which exhibits a high etch selectivity, allowing

longer etching times and thereby longer pillars, with heights above 150 µm.[30]

In order to fabricate silicon pillars with diameters in the range of nanometers,

other lithography techniques have to be applied, such as laser interference

lithography (LIL)[31]

or nanosphere lithography (NSL).[32,33]

For example, a

close-packed monolayer of polystyrene spheres drop-casted on a layer of SiO2

followed by DRIE enabled the fabrication of nanopillars.[32,33]

The size of the

polystyrene particles was adjusted by oxygen plasma, such that a non-close-

packed monolayer became available for etching (Figure 2.4). Another example

of the use of particles as a mask employs the self-assembly of cesium chloride

particles.[34]

After a film of these particles was deposited on the silicon

substrate and the temperature was lowered, the particles self-assembled by

absorbing water from the air environment. A wide variety of pillar diameters

was obtained (50 nm – 1 µm), however, the pillar height was limited by the

etch selectivity between the particles and silicon, resulting in rather low aspect

ratios of 2-6.

Figure 2.4: Side view SEM images of nanospheres used as an etch mask using DRIE of

silicon, after different times of oxygen plasma exposure prior to etching to reduce the size

of the nanospheres. Left image is not exposed to oxygen plasma, followed by 30, 60, 90

and 120s (right) of oxygen plasma. Scale bars represent 750 nm. Reproduced with

permission.[33]

Copyright 2006, IOP Publishing.

To fabricate wafer scale arrays of pillars, nanoimprint lithography is a

promising technique for the formation of the mask layer.[35]

In short, a

thermoplastic or a photocurable polymer is patterned on a substrate by an

imprint mold, and this layer can act as a mask during DRIE. The feature sizes


25

that can be obtained with this technique reach the sub-10 nanometer range.[36]

Using the combination of NIL and DRIE, silicon pillars with an aspect ratio of

60 and a diameter of 50 nm have been made on wafer scale.[35]

Another method to create large areas of silicon pillars is maskless etching,

which uses a technique called black silicon etching.[37,38]

By tuning the settings

of the etch process, small contaminations on the wafer, i.e. deliberately

created by-products or reaction intermediates from the etch process, can act

as nanomasks on the silicon surface, resulting in the formation of spikes.[38]

As

the technique does not require a mask, wafer scale etching is easily achieved,

and the fabrication of silicon pillars with diameters between 50-80 nm, with

heights up to 1600 nm, has been shown.[37]

Note that these structures are

randomly positioned, and pillar diameter and pitch cannot be defined by

design. Note also that by the nature of the black silicon process, the pillars will

have a small but notable taper.

2.3.2. Wet etching

In contrast to dry etching, wet etching does not require a reaction chamber

under vacuum, but is instead performed at atmospheric pressure in a liquid.

This increases the possible throughput significantly, as several wafers can be

etched at the same time, without any preloading requirement. Two types of

wet etching methods are frequently applied for the fabrication of silicon pillars,

namely electrochemical wet etching and metal-assisted chemical etching

(MACE). Both methods are schematically illustrated in Figure 2.5.

Chapter 2

26

Figure 2.5: Schematic representation of typical electrochemical etching (A) and MACE (B)

processes. (A1) A hard mask (e.g. SiO2 or SiNx) is patterned on the silicon surface, and

the substrate is placed in an HF solution, connected between two electrodes. (A2) An

anodic bias is applied and the exposed silicon is etched down. (A3) The sample is

removed from the solution, followed by removal of the resist mask. (B1) A metal mask

(typically silver) is patterned on the surface and placed in an HF solution. (B2) The metal

film is etched into the silicon surface, leaving the non-patterned silicon untouched.

(B3) The silicon sample is removed from the solution and the metal masked is stripped.

During the process of electrochemical etching, an electrolyte, in combination

with an anode and cathode, creates a charged double layer near the surface

of the silicon, which results in the creation of nanostructures.[39]

The shapes of

these structures can either be defined by the shape of a physical object that is

brought in close proximity of the substrate, or by using a masking layer, which

can be deposited by various methods.[39,40]

Using this technique, many

complex shapes have been created, when the proper masking steps were

used.[41,42]

For example, in an comprehensive study on electrochemical

etching, Bassu et al. were able to fabricate a MEMS device, with high-aspect

ratio (100) comb fingers suspended by high-aspect ratio folded springs.[43]

Metal assisted chemical etching (MACE) is a process that starts with the

deposition of metallic nanoparticles (usually silver) on the surface of silicon,

followed by the electroless etching in an aqueous mixture of H2O2 and HF.[44,45]

It is proposed that the silver particles sink into the silicon, thus etching the

silicon under the silver nanoparticles, whereas the uncovered silicon remains

intact. For a more detailed discussion about the possible mechanism for


27

MACE, see the article by Geyer et al.[46]

Typically, the process results in the

formation of silicon nanopillars with diameters from <10 nm up to a few

hundred nm, and with heights depending on the etching time, ranging from a

few µm up to 20 µm.[2,47-49]

Peng et al. investigated the etching direction of

both gold and silver particles, and concluded that this direction is highly

uniform, does not depend on the dopant type and level of the substrate, and

preferentially occurs along the (100) orientation of crystalline silicon

(Figure 2.6).[50]

Instead of electroless deposition of metal particles, it is also

possible to deposit a thin metal film, which is patterned or annealed to create

nanoparticles. An example can be found in the work of Huang et al.,[51]

where

the previously described masking method using polystyrene beads was

applied to control the silver nanoparticle size before MACE.

Figure 2.6: Cross section SEM images of silicon substrates coated with Ag particles,

followed by 30 min MACE process in HF/H2O2 on: (a) p-type silicon (100), (b) p-type

silicon (111), (c) p-type silicon (110) and (d) n-type silicon (113) substrates. Reproduced

with permission.[50]

Copyright 2008, Wiley-VCH.

2.3.3. Vapor-liquid-solid growth

The most popular bottom-up method for the growth of silicon pillars is the

so-called vapor-liquid-solid (VLS) growth, which is schematically shown in

Chapter 2

28

Figure 2.7. Already in 1964, this technique was discovered and a process was

reported in which a small gold particle was used to grow a single silicon pillar

from the vapor phase.[52]

This particle was heated up to 950 °C, forming a

gold-silicon alloy, and by supplying hydrogen and silicon tetrachloride, the

liquid alloy acted as a sink for the silicon atoms. Increase of the reaction time

led to saturation of the alloy, and silicon froze out below the liquid particle. The

here described process uses chemical vapor deposition (CVD) to supply

silicon for the growth, but many other techniques can also be used, such as

laser ablation, electron beam evaporation, and physical transport as described

in a review of Barth et al.[53]

Figure 2.7: Schematic illustration of a typical VLS silicon pillar growth process. (A) After a

metal pattern is defined, a silicon gas is introduced and dissolved in the metal particle,

which initiates pillar growth. (B) The time and flow of the gas is used to control the height

of the pillars. (C) After the process, the metal particles are removed from the top of the

pillars.

In the last decade, many improvements of the VLS process were reported. For

example, the possibility to grow small arrays of pillars, instead of single pillars,

was shown by the use of electron beam lithography and metal lift-off.[54]

For

this method surface migration of the metal catalyst (gold in this case)

determines the height, shape and sidewall properties of the silicon pillars.[55]

To circumvent this issue and to obtain smooth and arbitrarily long pillars in a

large array, the gold diffusion has to be controlled. As a result, templates were

used to control the catalyst diffusion and pillar growth, and this resulted in

large arrays of VLS grown pillars.[56]

The group of Atwater introduced a 300 nm

buffer oxide layer as a barrier between individual metal particles, to avoid the

use of a template and to prevent agglomeration of the particles at the same

time.[57,58]

By doing this, they were able to fabricate large areas (>1 cm2) of

silicon pillar arrays without the use of a template (Figure 2.8).


29

Figure 2.8: Tilted SEM image of a large-scale (>1 cm2) Cu-catalyzed VLS grown silicon

micropillar array. Inset shows a zoom in of several pillars (scale bar is 10 µm).

Reproduced with permission.[57]

Copyright 2007, American Institute of Physics.

2.3.4. Comparison of fabrication techniques

As a summary, Table 2.1 gives a selective overview of the reported possible

pillar dimensions. The numbers given should not be seen as a real limitation of

the fabrication methods, but as an indication in which range the technique is

commonly used.

Table 2.1: Overview of different fabrication techniques, used for the fabrication of silicon

nano- and micropillars.

Etch technique Etch

type

Height

(µm)

Diameter

(nm)

Wall-to-wall

distance (nm)

DRIE & UV lithography[20-23,25]

Dry etch 1-150 >1000 >1000

DRIE & Deep-UV lithography[28,59]

Dry etch 1-150 >250 >250

DRIE & Nanosphere lithography[32-34]

Dry etch <10 50-500 50-500

DRIE & Nanoimprint lithography[35,36]

Dry etch <5 10-100 >100

Electrochemical wet etching[40,41]

Wet etch <25 500-2000 >1000

Metal assisted chemical etching[49,50,60]

Wet etch <20 100 <10

Vapor-liquid-solid growth[54-58]

Growth 1-100 50-1500 50-5000

Chapter 2

30

2.4. Doping of silicon

Silicon can be doped using several techniques yielding greatly varying surface

concentrations, junction depths and doping profiles. This section describes

processes utilized for the p- and n-type doping of silicon, on either flat or

structured surfaces. We will discuss whether the techniques have been, or

potentially could be used for doping of micro/nanopillars. Although there are

several elements (B, P, Sb, As, Ga) that can be used for the introduction of

p- and n-type dopants in silicon, only boron and phosphorus will be discussed

here as they are most commonly used. The standard process for any doping

method is divided into two steps: first the dopant atoms are introduced at the

surface of the silicon substrate via the formation of a layer (usually an oxide

layer), followed by a drive-in step during which dopant diffusion into silicon

takes place. Exceptions are ion implantation, where the dopant is injected into

the silicon substrate (see 2.4.1), and epitaxial growth, where doping is

performed in-situ during silicon layer deposition.[61]

The temperature and time

control during the drive-in step is important for the final doping profile. When

the deposition temperature of the dopant-containing layer is higher than

800 °C, the formation of such layer and the dopant diffusion into silicon occur

simultaneously.

2.4.1. Ion implantation

During ion implantation, ions are accelerated towards the silicon target, which

results in doping.[62]

Although recent research shows good reproducibility with

respect to the doping dose and profile, this technique requires a thermal

annealing step after the doping, to ensure defect healing and dopant

activation, because of the damage to the silicon crystal lattice generated by

the energetic ions.[63]

The directionality of this technique makes ion

implantation less suited for radial doping of silicon micro/nanopillars, but it may

be an option for the generation of a dopant gradient along the axial direction of

pillars. In the latter case, it would be preferred to use implantation in

combination with DRIE, in which case the ion implantation can be performed


31

before etching the pillars. DRIE of silicon has shown little dependence on the

doping level, for moderate dopant levels.[64,65]

2.4.2. Chemical vapor deposition

Chemical vapor deposition (CVD) is a widely used technique to form layers of

dopant oxides on silicon surfaces, which are subsequently used as diffusion

sources. In CVD at atmospheric-pressure (APCVD)[3,66,67]

high flow rates

(1500-3000 sccm) of reactive gases (e.g. PH3 and B2H5) are supplied, and a

conformal layer is formed at elevated temperatures (usually above 900 °C). By

controlling the ratio between the oxide and dopant flow, the dopant

concentration in the oxide layer can be controlled, which in turn determines,

along with the anneal time and temperature, the characteristics (junction depth

and dopant level and profile) of the doped silicon layer. After the dopant layer

has been deposited, the temperature is further increased to the desired drive-

in temperature to increase the dopant diffusion rate. Owing to the atmospheric

pressure condition, this technique can be easily scaled up to large batches of

wafers, as shown by Rothhardt et al.[66]

In case of doping 150 wafers in an

industrial scale furnace, there was no difference in sheet resistance between

the wafer positioned near the gas inlet and at the end of the wafer boat.

In order to obtain similar layers as described for APCVD, but at lower

temperatures, plasma-enhanced CVD (PECVD) is a suitable option.[68,69]

During PECVD, electrons rapidly gain energy through a radio frequency (RF)

field and, combined with a reagent gas (e.g. PH3), they form highly reactive

chemical species that produce the desired layer, already at a temperature of

300 °C.[70]

PECVD can also be used to deposit in-situ doped silicon, by means

of which the drive-in step can be omitted, but it yields an amorphous or

poly-crystalline layer.[71,72]

Hot-wire chemical vapor deposition (HWCVD), also referred to as catalytic

CVD, is used for the deposition of mainly inorganic thin films.[73,74]

During the

deposition under vacuum, a precursor source is heated by a metallic filament

to obtain conformal thin films on various substrates, for example

Chapter 2

32

nanostructured silicon.[75]

By combining the precursor with the desired dopant

molecules, shallow junctions can be formed, as shown by several different

research groups.[76-78]

As the dopant layer is deposited on silicon, no additional

drive-in step is required. The main advantage of HWCVD is the absence of a

plasma, thus obviating the risk of damaging the silicon substrate by

bombardment with energetic ions.

Another method to deposit boron or phosphorus containing layers, is

low-pressure CVD (LCPVD). The layer thickness and dopant concentration of

the grown layer are controlled by the pressure and the gas inlets. For this

process, a pressure of typically a few hundred mTorr is often used,

corresponding to gas flows that are significantly lower than in the case of

APCVD, (i.e. 100-500 sccm).[79,80]

Depending on the application different gas

mixtures are supplied, for example, PH3 and SiH4 for in situ phosphorus

doping of polycrystalline silicon films, yielding a phosphorus doped layer.[81]

The LPCVD technique is mainly used to grow in-situ doped polysilicon, which

is characterized by the absence of mechanical stress and a low electrical

resistivity, however, it can also be used as a dopant source for the doping of

single-crystalline silicon, by depositing a dopant containing oxide layer.

2.4.3. Solid source dotation

In the case of solid source dotation (SSD), solid wafers of either boron nitride

(for p-type doping) or cesium phosphate (for n-type doping) are used to supply

the dopant species to the silicon surface. The dopant atoms are transferred by

evaporation from the solid source, diffuse to the silicon surface, and are

incorporated in-situ in a growing oxide layer. In the case of boron doping, the

deposited layer consists of boron oxide, grown during the exposure of boron

nitride wafers at elevated temperatures under an oxygen flow.[82]

By varying

the deposition time, the layer thickness can be varied, however, the maximum

solubility of boron in silicon (approximately 1020

atoms/cm3, depending on the

drive-in temperature[83]

) is already achieved after a 30 min growth step.


33

This means that the junction depth is primarily controlled by the time and

temperature of the anneal step. Directly after this step, the temperature is

further increased for the drive-in step. Using this technique, it is possible to

form junctions ranging from a few hundreds of nanometers to several

microns.[84]

The same procedure can be followed for n-type doping of silicon

with phosphorus, by using solid cesium phosphate wafers.[85,86]

2.4.4. Monolayer doping

Monolayer doping (MLD) uses hydrosilylation to chemically attach either boron

or phosphorus containing molecules to a hydrogen-terminated silicon surface,

that is formed by the wet etching of the native oxide by aqueous fluoride.[87]

After the attachment of the molecules, a silicon dioxide capping layer is

deposited onto the monolayer, and subsequently a rapid thermal annealing

(RTA) step is performed to drive in the dopant molecules into the silicon. The

final junction depth depends on the amount of dopant atoms in the monolayer,

and the RTA time and temperature. In 2011, a variation of this method was

published achieving the local doping of areas of a silicon substrate.[88]

By combining MLD with nanoimprint lithography and reactive ion etching, a

pattern was made in the dopant layer on the silicon, which was then analyzed

with SIMS to evidence the method and function. Monolayer doping has many

advantages, such as the variety of reactions and molecules that can be used

to form the monolayer on silicon and the possibility to form ultra-shallow

junctions, in the range of a few nanometers.[89-91]

As shown in Figure 2.9, the

group of Javey managed to scale-up the MLD technique to wafer scale,

enabling the possibility of large-volume production.[92]

Chapter 2

34

Figure 2.9: Schematic representation of a full wafer scale MLD process for either boron or

phosphorus doping. Reproduced with permission.[92]

Copyright 2009, American Chemical

Society.

2.4.5. Spin-on dopant

Doped silicon layers can also be fabricated by using a spin-on-dopant (SOD).

With this method, a spin-on-glass (SOG) solution containing either boron of

phosphorus, is spin-coated on a silicon substrate. After a short

low-temperature drying step, the coated wafer is heated up to the drive-in

temperature, usually in the range of 850-1100 °C, at which dopant diffusion

into silicon occurs.[93,94]

Different concentrations of dopants in SOG solutions

can be obtained and used to tune the doping profile and junction depth.

Afterwards, the glassy layer is removed with a buffered hydrogen fluoride

solution. Since no vacuum is required to form the SOD layer and the spinning

of the SOD layer only takes about 30 s, the technique has a large advantage

in terms of high-throughput fabrication of p/n junctions. The technique is

suitable for both ultra-shallow (12 nm) and deep junctions (several

micrometers), and is a relatively easy and fast alternative to the previously

described doping methods.[18,93]

The versatility of SOD is evidenced by

literature examples, in which SOG is used in combination with SODs to

selectivity dope certain areas on a silicon wafer, or where organic polymers

are used (instead of inorganic) that are burnt away during the diffusion

step.[27,95]


35

In another example, an axial p/n junction was created by filling the areas

between silicon pillars in an array with SOG, followed by an RIE step to access

the top part of these pillars, and subsequent deposition of an SOD layer for the

diffusion of dopants in the top part.[96]

2.4.6. Proximity doping

To enhance the control over silicon doping, already in 1994 proximity doping

was introduced in combination with SOD.[97]

The idea behind proximity doping

is the use of a dummy wafer, onto which a finite SOD layer is previously

applied, that is brought in close proximity (~400 µm) of the target wafer. By

controlling the distance between dummy and target wafer during the drive-in

step, the doping characteristics of the target wafer can be altered in a

controlled way. The junction depth is determined by the concentration of the

dopant on the dummy wafer, and the time and temperature used during the

transfer step. More recently, the combination of SOD with proximity doping has

been used to dope silicon pillars to ensure a homogeneous distribution over

the height over the pillar, and control over the surface concentration between

1018

-1020

atoms/cm3 has been shown.

[18,98] The use of proximity doping is not

limited to SOD samples, as any substrate with a dopant layer can be used.

The proximity principle has been shown to work as well in combination with

MLD, by forming a dopant containing monolayer on a donor substrate and

using an RTA step to dope both the target and donor substrate.[99,100]

By repeating this procedure multiple times, higher doping concentrations were

achieved for the target substrates, as well as deeper (>100 nm) junctions.

2.4.7. Comparison of methods for doping silicon

An overview of all doping techniques is given in Table 2.2. Besides the

requirements of a vacuum for the method and necessity of a drive-in step, it is

indicated whether the method is suited for structured surfaces and which

junction depth can be realized. The junction depth range only gives an

indication, other values may be possible by tuning of the doping technique.

Chapter 2

36

Table 2.2: Overview of different doping techniques, used for the fabrication of silicon p/n

junction (boron and phosphorus).

Doping technique Vacuum? Drive-in

step?

Junction

depth (nm)

Radial

junction?

Ion implantation[62,63,101,102]

Yes No1 <1000 No

Atmospheric-pressure CVD[3,66,103]

No Yes 100-3000 Yes

Plasma-enhanced CVD[68,70,72]

Yes Yes 100-3000 Yes

Hot-wire CVD[77,78]

Yes No <1002 Yes

Low-pressure CVD[79,80]

Yes Yes 100-1000 Yes

Solid source dotation[82,85,86]

No Yes 100-3000 Yes

Monolayer doping[87,88,91]

No Yes <100 Yes

Spin-on dopant[27,93-95]

No Yes 10-3000 Yes

Proximity doping[97-99]

No Yes 10-1000 Yes

1) Although a drive-in step is not necessary for silicon doping, a high-temperature annealing step is

needed to repair crystal damage. 2) The junction is realized as a layer, meaning that the junction depth is limited to the layer

thickness that can be deposited.

2.5. Junction analysis

In this section, the analysis of the formed p/n junction in silicon is discussed. It

gives an overview of the analysis on flat and structured surfaces, as well as

JV measurements on silicon p/n junctions.

2.5.1. Flat surfaces

To verify the presence of the introduced dopants, several methods can be

used. The most common technique is secondary ion mass spectrometry

(SIMS). By sputtering off the top of the doped silicon layer by layer with an ion

beam, and measuring the mass and charge of the ions coming off the surface,

detailed information about the elemental composition can be obtained as a

function of the depth. By comparing the obtained values to a standard, the

information is translated into quantities and thus concentration. This technique

is suitable for both deep and ultra-shallow junctions, making it useful for almost

all doping techniques.[103,104]

For example, several groups used SIMS to

confirm the formation of an ultra-shallow junction with MLD with a junction

depth of about 5 nm (Figure 2.10).[89,92]


37

Figure 2.10: SIMS measurements on silicon samples doped with phosphorus using the

MLD technique, at various spike anneal temperatures. Reproduced with permission.[92]

Copyright 2009, American Chemical Society.

Although SIMS gives information about the surface concentration and the

doping profile, the data does not give an exact value for the junction depth

itself. This is due to the limitation of SIMS, which can only detect positive or

negative ions in a single measurement. Furthermore, the detection limit of

SIMS is often in the range of the order of the base dopant concentration of the

silicon, meaning that only trends in the doping profile are visible, but an

accurate value for the junction depth cannot be determined.

Junction depths can be accurately determined by spreading resistance

profiling (SRP), in which the resistivity of doped samples is analyzed as a

function of the depth, by measuring on a beveled surface (+/- 3°) with

two probes.[105]

With this technique, it is possible to quantify thin junctions in

silicon, for example a 100 nm junction formed by MLD on a p-type wafer.[106]

A simple method to analyze the junction depth is ball grooving and staining.[107]

This method consists of the formation of a groove in the doped flat silicon

substrate by milling for a few seconds with a diamond-slurry stainless steel

ball. This creates a very shallow groove, the depth of which should be larger

than the junction depth. Once both the doped layer and the base silicon wafer

are exposed, a staining solution is applied to create a contrast difference

between the two areas. Suitable staining solutions are aqueous hydrofluoric

Chapter 2

38

acid with a few droplets of nitric acid, or aqueous chromium trioxide diluted

with hydrofluoric acid.[107,108]

A clear contrast is visible after staining because

the silicon etching rate depends on the dopant type and concentration. By

measuring the radius of the two differently colored areas, combined with the

radius of the ball used for grooving, the junction depth can be expressed

as:[107]

(2.1)

Where xj is the junction depth, R is the radius of the ball, a is the radius of

outer ring and b is the radius of the inner ring. On its own, ball grooving only

gives a value for the junction depth, and no information regarding the doping

concentration and profile. However, when combined with, for example sheet

resistance measurements or SRP, it can function as a quick verification of the

junction depth and doping level.

The sheet resistance is directly related to the surface concentration of the p/n

junction, and is expressed in Ω/sq. A typical sheet resistance measurement

involves the use of a four-point probe, where a fixed current is applied to two

probes and the potential between the other two probes is measured. In case

the doping level is uniform over the whole doping thickness, the resistivity of

the wafer can be directly calculated using the junction depth. Unfortunately,

this is not the case for most doping techniques, as these result in layers doped

in a gradient fashion, meaning that the dopant concentration decreases from

the surface to the junction. Yet, the measurement can still provide useful

information, especially when comparing different doping settings of the same

technique, as the sheet resistance will decrease with increasing surface

concentration.[63,68]

Similar to ball grooving and staining, the combination of

sheet resistance measurements with SIMS results in a good method for

verification of the process settings. For example, Hoex et al. showed a set of

sheet resistance measurements, verified with SIMS (Figure 2.11), to calibrate

their doping settings of the PECVD technique.[109]


39

Figure 2.11: Sheet resistance measurements of various boron doped silicon wafers, and

their corresponding SIMS profiles; samples were doped at temperatures in the range of

895 – 1010 °C. Reproduced with permission.[109]

Copyright 2007, American Institute of

Physics.

2.5.2. Structured surfaces

Although the techniques described in section 2.5.1 (or their combination) will

result in a good estimation of the junction depth, they can only be performed

on flat surfaces. For determining the presence of a junction in a pillar,

characterization may be carried out on flat dummy wafers added in the same

doping run as the pillared substrates, or better even on a doped flat area

adjacent to the pillar array on the same substrate. This however does not give

information about the homogeneity of the doping along the pillar height, and in

fact, actual junction analysis on structured surfaces is quite rare. For instance,

Guo et al. used SIMS measurements to analyze substrates doped with SOD,

on both flat and on micro-sized pillar structures (4 µm height, 3 µm diameter,

Figure 2.12).[22]

These SIMS data show an increase of the total doping dose of

the structured sample, but do not give an indication whether the doping is

homogeneously distributed along the pillar height.

Chapter 2

40

Figure 2.12: (A) SIMS measurements on both flat and structured solar cells, showing an

increase in doping on structured surfaces. (B, C) Schematic illustration of SIMS

measurements on flat and structured (C) silicon. Reproduced with permission.[22]

Copyright

2012, Springer.

In another example, Jin-Young et al. managed to visualize the radial doping

profile in silicon micropillars using low-voltage SEM (Figure 2.13).[18]

Both

nano- and micropillar arrays were fabricated using MACE, thereby obtaining a

patterned micropillar array with random nanopillars in between (Figure 2.13d),

which were doped using the proximity method. To observe the radial junction,

cross-sectional faces were polished after filling the spacing between pillars

with crystal wax (to preserve the pillars during polishing). Using decreased

acceleration voltages for SEM, a contrast between the highly doped n-type

and base p-type zones became visible along the vertical axis of the micropillar.

The junction depth agreed with the SIMS measurements done on flat samples.

Although the radial junction is visible, only the lowest 4 µm of the pillar

(height of 10 µm) was still present during the analysis, and it is unclear

whether this is due to partial breaking of the micropillars before or after

proximity doping.


41

Figure 2.13: (a) Low voltage SEM cross section (2 µm scale bar). (b) False colored image

of (a), where lighter and darker parts were colored to red and blue, respectively. Green

indicates unconverted areas. (c) Contrast intensity along the yellow line in (a), linked to the

SIMS profile. (d) Schematic illustration of the different array configurations. Reproduced

with permission.[18]

Copyright 2010, IOP Publishing.

2.6. Optical and electrical characterization

Besides fabrication and characterization of the pillar arrays and the

p/n junctions therein, it is equally important to analyze the optoelectronic

properties of the resulting pillar arrays, in terms of the reflectivity, transmission

and light absorption, and the current density-voltage (JV) characteristics, in

order to quantify the improvement of the pillar arrays compared to flat

surfaces.

2.6.1. Absorption and reflection

Pillar arrays provide a significant improvement for the generation of charge

carriers, since the light is effectively trapped inside the array, an effect that can

be quantified as a reduction of the reflectivity. This advantage, in combination

with the decoupling of the directions of light incidence and charge transport

processes, results in large improvements of the photocurrent produced by

pillar arrays compared to flat surfaces. As described in section 2.2, a lot of

Chapter 2

42

research has been performed on simulations of absorption, reflectance and

transmission of silicon pillar arrays, of which the common conclusion is that the

pillar arrays always outperform flat surfaces. For reflectivity/transmission

measurements of such highly light-scattering samples, a so-called integrating

sphere is required, to be able to capture all the light.[110]

For most silicon solar

cells investigated in the literature, the absorption can be directly calculated

from the reflection because a thin layer (>10 nm) of silicon is already sufficient

to prevent any transmission below a wavelength of 900 nm.[3]

The same trend as found with simulations – i.e. a large decrease of

reflectance in case of the presence of nano/micron-sized pillars – has also

been measured experimentally for silicon pillar arrays composed of different

pillar dimensions that were made with various fabrication techniques, such as

RIE,[111]

MACE[112]

and VLS growth.[17]

For all pillar configurations, the

reflectivity was below 20% (down to <1%) for most of the visible light

wavelength range (measured for a zero degree incident angle) compared to

roughly 40% for flat silicon. The angular behavior of samples with pillar arrays

showed that such structured surfaces consistently outperform flat silicon

surfaces, independent of the angle of light incidence or measurement

angle.[113-115]

For example, DRIE nanopillars showed a 1% reflection at a

40° incident angle, whereas a flat surface reflected 45% of the light.[114]

In

addition, various parameters have been proven to positively affect the

reflectivity, such as the diameter,[116]

tapering,[113,117]

and height of the pillars.

Especially the tapering of pillars, giving silicon cones with a diameter

decreasing from bottom to top, significantly improves the absorption, as the flat

top of a cylindrical pillar will still reflect light, an effect that is stronger at larger

incident angles.[113]

Figure 2.14 shows the improvement in absorption for

nanowires (pillars with a flat top, no tapering) and more specifically nanocones

with a sharp tip. Although a tapered (top section of a) pillar is beneficial for

light absorption, a disadvantage is that a (partially) tapered pillar has less area

with a properly functioning radial junction, compared to a pillar with

perfectly vertical sidewalls, which results in less collected photocurrent.


43

The decrease in junction area evidently depends on the level of tapering and

the junction depth.

Figure 2.14: Absorption measurements on a thin film, a nanowire array and a nanocones

array. (A) Absorption scanned over a wavelength range of 400-800 nm for all samples. (B)

Angular dependency absorption measurements. Reproduced with permission.[113]

Copyright 2009, American Chemical Society

In order to obtain extremely low reflectivities, Cho et al. realized a complex

light trapping pillar array, using sub-wavelength dimensions and the

incorporation of extra structuring on the pillars (in the range of 30 nm).[118]

Nanosized pillars were made by DRIE, and substructures on the outside of

these pillars were made by a dilute polymerization and a capillary

self-assembly process. This method yielded an average reflection of <0.01%,

and down to even 0.0031% for wavelengths in the visible light. Doping of these

nano-pillars to obtain radial p/n junctions seems to be difficult, since the pillars

tend to bend/cluster together during the solvent evaporation step.

In the case of pillars of a larger scale, with micrometer-sized diameters and

heights, it is possible to further decrease the reflectivity by using anti-reflection

coatings, as shown by Kelzenberg et al.[17]

To study the effect of an

anti-reflective coating on wire arrays, independently of the substrate onto

which the pillars were grown (by VLS), they embedded the pillars in a layer of

PDMS, and transferred the PDMS-embedded arrays onto a quartz slide. The

angular dependency of the absorption was measured for different

anti-reflective coatings: i) an SiNx coating containing aluminum oxide

nanoparticles, ii) a silver back reflector on the quartz carrier, and iii) a

Chapter 2

44

combination of both. Figure 2.15 gives an overview of the coating options, and

the improvement in absorption for each coating is clearly visible. In fact, for the

combined option, they achieved an absorbance of 97% for nearly the complete

visible light wavelength range, and attributed the 3% loss to absorption by the

PDMS. These anti-reflective coatings provide possible solutions for

improvement of the absorbance of pillar arrays after fabrication of the arrays.

Figure 2.15: 3D absorption plots for different sets of pillar arrays, for wavelength and

angular dependency. (A) Silicon pillars embedded in a PDMS layer, on top of a quartz

slide. (B) Addition of an SiNx anti-reflective coating with Al2O3 particles. (C) Addition of a

silver back reflector on top of the quartz slide, below the PDMS layer. (D) Combination of

the two effects described in B and C. Reproduced with permission.[119]

Copyright 2010,

Nature Publishing Group.

2.6.2. JV measurements

The presence of a p/n junction can be verified electrically by measuring the

current as a function of potential. This can also be done under illumination, as

the silicon will absorb certain parts of the visible light spectrum and the p/n

junction will direct the resulting flow of charge carriers. By determining the

short circuit current density (JSC) and the open circuit potential (VOC), the

typical diode (in the dark) or solar cell (under illumination) characteristics and

performance of doped pillar arrays can be determined. The improved

performance of pillared surfaces over planar surfaces has been shown in

numerous studies, for both solar cells[21,29,120]

and photoelectrochemical (PEC)

experiments.[1,2,20]

In some cases, pillared surfaces have shown up to double


45

the amount of current.[29]

Table 2.3 gives an overview of JV properties of

silicon cells, fabricated and doped with different techniques.

Table 2.3: Overview of JV measurements on silicon solar cells, using different fabrication

and doping methods on flat and structured samples.

Doping method Fabrication

method

JSC Flat

(mA/cm2)

JSC Pillars

(mA/cm2)

η Pillars

(%)

Junction

depth (nm)

APCVD, phosphorus[29]

DRIE 9.6 20.0 8.7 300

SSD, phosphorus[86]

VLS 13.0 23.02 9.0

2 100

Spin coating,

PEDOT/PSS[119]

MACE 22.3 30.9 12.0 -

PECVD1, boron

[21] DRIE 23.9 31.1 12.2 10

APCVD, phosphorus[120]

RIE 30.2 38.4 15.4 300

1 Doped amorphous silicon was grown in this example.

2 JV measurements were done a single pillar.

The JV measurements give an average and global picture of the quality of the

junction, but they do not give information about the homogeneity of the doped

layer inside the silicon pillars or the doping profile. Due to this, it is very difficult

to compare the performance of devices reported in literature, since their cell

size, structural dimensions, and base doping level often vary, as well as the

fabrication and doping techniques (see Table 2.3). For example, it is not

possible to determine the optimal junction depth by comparing results found in

literature, as too many different factors influence the JV data. In addition to

these dopant level and geometrical variations in pillar arrays, also anti-

reflective coatings and passivation layers have been introduced to improve

solar cells, as well as for chemical passivation of solar-to-fuel devices.[121,122]

For the fundamental understanding of a junction (i.e. recombination,

resistance, junction depth) it is beneficial to compare simulation results with

experiments, as shown by Christesen et al.[123]

By simulating the JV data, they

were able to extrapolate the limitations of their solar cell, such as the surface

recombination velocity. For the understanding and comparison of different

doping techniques, it is required to perform such simulations and experimental

measurements for different doping settings (both on flat and

nano/microstructured surfaces), to be able to make a fair estimation of optimal

Chapter 2

46

pillar and junction properties. However, to date, this is not performed

frequently, nor part of the design phase of solar cells and solar-to-fuel devices.

2.7. Conclusions

Nano- and micropillars on silicon provide the possibility to increase the

efficiency of many solar energy applications such as solar cells and solar-to-

fuel devices. By means of simulations of the properties of a p/n junction as well

as the dimensions of doped single pillars and arrays of doped pillars, the

understanding of these devices is enhanced. However, experimental and

modeling results are still hardly being combined.

For the fabrication of arrays of silicon nano- and micropillars, there are many

options such as DRIE, VLS and MACE, all having pros and cons for making

pillar arrays with certain dimensions for the pillar diameter, height and pitch.

Another important step in the fabrication of solar energy devices is the

formation of the required radial p/n junction in such pillars, which can be done

with a range of different techniques, ranging from bulk CVD processes, to

sophisticated MLD on silicon with junction depths varying from 5 nm to several

micrometers.

The analysis of the p/n junctions is mostly restricted to planar surfaces. This is

problematic since it is not yet experimentally verified whether all doping

techniques are able to form a homogeneous doping profile over the full height

of a pillar, especially in the case of high aspect ratio pillars or closely packed

arrays. Although the presence and functionality of junctions can be proven by

means of JV measurements, it is still difficult to reliably select the proper

design settings for solar energy devices, due to the numerous variations in

literature with respect to fabrication methods, the doping profile and technique

as well as pillar (diameter, height, pitch) and array (order) dimensions. Future

developments will bring new insights on how to enhance the understanding,

the fabrication and the performance of silicon micro/nanopillar-based solar

devices.


47

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Lett., 2012, 12, 6024-6029.

This chapter has been published as: R. Elbersen, R.M. Tiggelaar, A. Milbrat,

G. Mul, J.G.E. Gardeniers, J. Huskens, Adv. Energy Mater., 2015, 5, 1401745

51

Chapter 3

Controlled Doping Methods for Radial

p/n Junctions in Silicon Micropillars

P/n and n/p junctions with depths of 200 nm to several microns have been

created in flat silicon substrates as well as on 3D microstructures by means of

a variety of methods, including solid source dotation (SSD), low-pressure

chemical vapor deposition (LPCVD), atmospheric-pressure chemical vapor

deposition (APCVD) and plasma-enhanced chemical vapor deposition

(PECVD). Radial junctions in silicon micropillars were inspected by optical and

scanning electron microscopies, using a CrO3 based staining solution, which

enabled visualization of the junction depth. When applying identical doping

parameters to flat substrates, ball grooving, followed by staining and optical

microscopy, yielded similar junction depth values as HR-SEM imaging on

stained cross-sections and SIMS depth profilometry. For the investigated 3D

microstructures, doping based on SSD and LPCVD gave uniform and

conformal junctions. Junctions made with SSD-boron doping and

CVD-phosphorus doping could be accurately predicted with a model based on

Fick’s diffusion law. 3D microstructured silicon pillar arrays showed an

increased efficiency for sunlight capturing. The functionality of micropillar

arrays with radial junctions was evidenced by improved short-circuit current

densities and photovoltaic efficiencies compared to flat surfaces, for both

n- and p-type wafers (pillar arrays efficiencies of 9.4% and 11%, respectively).

Chapter 3

52

3.1. Introduction

In the field of solar energy technology, (sub)micron p/n junctions in crystalline

silicon are used for achieving charge separation at the surface of a solar

cell.[1,2]

To increase the efficiency of light capturing of solar cells, research has

focused on nano/micro structures, e.g. wires, with shallow junctions.[3,4]

Such

structures have advantages over thin film and bulk silicon surfaces, such as

higher surface areas and improved light-trapping capabilities.[5-8]

Although both

nano- and microstructures can be utilized, nanostructures put lower demands

on the silicon quality due to shorter minority carrier diffusion lengths,[9]

whereas

micron-sized features can be created with more commonly used fabrication

methods.

Silicon micropillars, with diameters of a few micrometers and heights of tens of

micrometers containing radial p/n junctions, have also received increased

attention, not only for solar cells, but also for solar-to-fuel applications, as they

can be functionalized in a controlled manner with various catalysts.[10-13]

Using

radial junctions, increased efficiencies over flat surfaces can be obtained, due

to greatly enhanced carrier collection in nano/micropillars.[7,13]

In addition, the

radial junction attributes to a lower surface recombination rate for the overall

device.[14,15]

Here, we investigate different doping methods applied to silicon micropillars, in

order to obtain optimal geometry control of the pillars and p/n junctions therein,

as well as ease of utilization for further applications. Silicon-based p/n

junctions can be realized by various doping methods. Standard doping

techniques reported in literature include ion implantation,[16]

solid source

dotation (SSD),[17]

monolayer doping,[18]

spin-on dopant,[19]

as well as regular

(CVD), low-pressure (LPCVD), plasma-enhanced (PECVD) and

atmospheric-pressure (APCVD) chemical vapor deposition.[20]

Not all

techniques are suited for 3D structures, for example, ion implantation is limited

to flat surfaces because of its directionality, while PECVD, in contrast to

Controlled Doping Methods for Radial p/n Junctions in Silicon Micropillars

53

LPCVD, does not give conformal step coverages, except for highly tuned

process conditions.[21]

Furthermore, high-density pillar arrays with small pillar

spacing and/or large aspect ratios can suffer from non-uniform doping of the

3D structures, in particular across the height of the structures.[22,23]

Thorough

investigations of whether common doping techniques lead to a controlled

junction depth in doped micro- and/or nanopillars have not been reported.

Here, we present different doping methods for both n-type (phosphorus, P)

and p-type (boron, B) doping of 3D crystalline silicon microstructures. We used

SSD in the case of boron doping, and several CVD techniques (LPCVD,

APCVD and PECVD) for phosphorous doping. For comparison, junction depth

analysis after doping with these techniques is done also on flat surfaces, using

ball grooving and chemical staining. Junctions in ridges and micropillars were

analyzed by cross sectional imaging using high resolution scanning electron

microscopy (HR-SEM). Secondary ion mass spectrometry (SIMS) was applied

to flat samples to verify junction depths and surface concentrations. JV

measurements were performed under the standardized AM (air mass) 1.5G

(global) illumination. The experimental results were compared with finite

element calculations of the dopant diffusion processes in flat and pillar

structures. This combination of experimental analysis and numerical

simulations forms a route to determine the optimal settings for structured solar

cells and solar-to-fuel devices.

3.2. Materials and methods

3.2.1. Fabrication of microstructure arrays

On p- and n-type silicon substrates ((100)-oriented, resistivity 5-10 Ω cm

(p-type) and 1-10 Ω cm (n-type), 100 mm diameter, thickness 525 μm (p-type)

and 375 μm (n-type), single side polished, Okmetic Finland), arrays of silicon

microstructures were fabricated. Prior to processing, the substrates were

cleaned by immersion in 100% nitric acid (HNO3) (2x 5 min), and in fuming

69% nitric acid (15 min), which was followed by quick dump rinsing in

de-mineralized (DI) water, immersion in 1% aqueous hydrofluoric acid (HF) to

Chapter 3

54

remove the native oxide prior to silicon nitride deposition and another quick

dump rinsing cycle. After spin drying (6000 rpm) of the wafers, 100 nm thick

silicon-rich silicon nitride (SiRN) was deposited using low-pressure chemical

vapor deposition (LPCVD), to prevent doping the backside of the wafer. With

reactive ion etching (RIE; Adixen AMS100DE; octafluorocyclobutane (C4F8)

and methane (CH4)) the SiRN layer on the front side of the wafer was

removed, followed by an oxygen plasma treatment and piranha (mixture of

sulfuric acid and 30% aqueous hydrogen peroxide, 3:1 (v/v), 20 min) cleaning

to remove any contamination. For use as a hard mask during etching, a layer

of 2 μm silicon dioxide (SiO2) was grown using wet oxidation (1150 °C). By

means of standard UV-lithography (on wafer-scale) for each 2 x 2 cm2 sample,

a centered 0.5 x 0.5 cm2 area with an array of micropillars (diameter 4 μm,

spacing 2 μm, hexagonally stacked with a packing density of 35%) or ridges

(width 100 µm, spacing 100 µm, height 30 µm) was defined in photoresist (Olin

907-17), and post-baked for 10 min at 120 °C after development. The

photoresist pattern was transferred into the SiO2 layer by means of RIE

(Adixen AMS100DE; C4F8, CH4). The photoresist, in combination with the

SiO2, acted as a mask layer during deep reactive ion etching (DRIE; Adixen

AMS100SE) of silicon using the Bosch process, i.e. a cyclic process

employing sulfur hexafluoride (SF6) for etching silicon and C4F8 to create a

passivation layer on the sidewalls. The height of the pillars was determined by

the etch duration, and was set to 20 min, resulting in pillar heights of

approximately 60 μm. After etching, the photoresist mask was stripped with

oxygen plasma, followed by piranha cleaning (20 min). Subsequently, the SiO2

layer was removed with 50% aqueous HF. The substrate was cleaned from

the remaining fluorocarbons in the DRIE process by oxidizing the surface at

800 °C (30 min), immersion in 1% aqueous HF (10 min), rinsing in DI water

and drying.


55

3.2.2. Doping methods

Doping of the arrays of silicon micropillars was done using various techniques,

i.e. SSD, LPCVD, APCVD and PECVD. In all cases, a dopant-containing oxide

layer was formed on the silicon surface, which was followed by a thermal

drive-in step to transfer the dopant into the silicon. In this work, the drive-in

temperature ranged from 900 – 1050 °C and the drive-in time was in the range

of 15 – 120 min. Prior to processing, all wafers were immersed in 1% aqueous

hydrofluoric acid (10 min), rinsing in DI water and drying, to expose a

H-terminated silicon surface. To remove the dopant oxide layer after the

doping process, wafers were immersed in buffered hydrogen fluoride

(1:7, BHF, 10 min), oxidized at 800 °C for 15 min and etched in 1% HF

(15 min), rinsed and dried. Below for each doping method details are given on

the formation of the dopant containing oxide layer.

Solid source dotation

In the case of solid source dotation (SSD) of boron, n-type silicon wafers were

placed in-between boron nitride wafers and a thin layer (~200 nm) of boron

oxide (B2O5) was formed on the surface of the silicon wafers under a

continuous oxygen flow (6000 sccm) at 800 °C.

Chemical vapor deposition

For chemical vapor deposition (CVD), three different processes were used; an

atmospheric-pressure CVD (APCVD), a low-pressure CVD (LPCVD), and a

plasma-enhanced CVD (PECVD). For the APCVD of phosphorus on p-type Si,

gas phase deposition was used to create a dopant oxide layer: at 950 °C, a

mixture of 4500 sccm phosphine (PH3) and 1200 sccm O2 was flushed through

the furnace for 30 min. In the LPCVD process, wafers were loaded in a boat

filled with dummy wafers, for optimal growth conditions on wafers. For a

deposition time of 30 min at 650 °C, a gas flow of 330 sccm PH3 and 150 sccm

O2 was used to grow the phosphorus oxide (at a pressure of 350 mTorr).

PECVD was utilized to deposit a phosphorus glass layer on flat p-Si wafers. At

Chapter 3

56

300 °C and 1050 mTorr, a gas flow of PH3 (100 sccm) was flushed through the

chamber for 15 min, in combination with 200 sccm N2O and 700 sccm N2.

A DC voltage of 50 W was used.

3.2.3. Analysis methods

Ball grooving and staining

To analyze the p/n junctions on flat surfaces, a stainless steel ball (60 mm

diameter) was used to expose the junction, by grooving the surface.[24]

To

improve the grooving rate, diamond paste was applied to the ball. Typically

only a few seconds were required to grind sufficiently deep (i.e. through the

junction) to a depth of 2-3 μm. After grooving, the samples were cleaned with

ethanol.

Revealing the depth of a p/n junction was done using an etching solution for

delineation along the p/n junction region, following the procedure as described

in a patent by Roman and Wilson.[22]

Chromium trioxide (CrO3) was mixed with

DI water in a ratio of 1 to 3 (w/w), subsequently a 50% aqueous HF solution

(10 v% of the starting solution) was added to the CrO3 solution. Samples were

placed in the resulting solution for 25 s, and subsequently rinsed with DI water

and dried with a stream of nitrogen. After this staining reaction, a contrast

difference is visible under a normal light microscope, in which the p-type

silicon area becomes darker than the n-type silicon. Figure 3.1 shows

schematic cross-sectional and top views of a stained groove. The same is

possible for n-type doping in a p-type wafer. Although the contrast is less

pronounced in this case, the contrast circle is still clearly visible.


57

Figure 3.1: Schematic cross section (left) and top view (right) of a stained groove on a flat

silicon surface. The dark-gray area indicates the boron-doped silicon layer, whereas the

white part is the bulk n-type silicon.

To calculate the junction depth (xj) after staining of the groove, the diameters

(a, b) of the two formed circles were determined. Then xj (µm) was calculated

as:

(3.1)

where a is the outer diameter of the circle (μm), b the inner diameter (μm) and

R the radius of the stainless steel ball (μm). A light microscope (Olympus

BHMJL, 5x magnification, Analysis® software) was used to measure a and b.

High-resolution scanning electron microscopy

To analyze the junctions, HR-SEM images of cross-sections of doped ridges

and micropillars were taken on an Analysis Zeiss-Merlin HR-SEM system with

an InLens detector. For ridges, samples were broken with a diamond pen

perpendicular to the length of the ridges. Focused ion beam (FIB) and reactive

ion etching were used to open up and image the micropillars. FIB structures

and images were made with a Nova 600 DualBeam – SEM/FIB setup.

A Ga+

liquid metal ion source was used to mill away enough of a pillar to be

a

b

b

a

xj

Chapter 3

58

able to accurately determine the junction location, with a beam current of

0.92 nA and 10 kV extraction voltage.

Secondary ion mass spectrometry measurements

Secondary ion mass spectrometry (SIMS) depth profiles of doped flat samples

were recorded using a Cameca ims6f using 7.5 keV O2+ primary ions in

positive mode. Secondary ions (31

P+ or

11B

+) and

28Si

28Si

+ as a reference were

detected. Quantification and depth calibration was based on reference

implants. Depth scale calibration was based on final crater depth

measurements using optical profilometry. For each dopant setting, only one

measurement was performed.

Electrical characterization

To investigate the electrical properties of the formed junctions, front and

backside contacts were made by sputtering 1 µm aluminum/silicon alloy

(99% aluminum, 1% silicon). Samples were placed perpendicular to a 300 W

xenon arc light source, which was calibrated to match the intensity of 1 sun

(AM 1.5). In case of p/n junctions created on low-doped n-type silicon

(~1015

atoms/cm3), the backside of samples was doped with phosphorus

(similar to the procedure for junction formation) to create n+ silicon. This was

necessary to ensure an Ohmic contact between the aluminum/silicon alloy and

n-type silicon. JV measurements were recorded on a VersaSTAT 4

potentiostat. For each dopant setting, at least 5 different samples were

measured.

Finite element simulations of boron and phosphorus doping

Junction depths and doping concentrations of p/n junctions created with SSD,

LPCVD and PECVD were simulated in COMSOL Multiphysics (version 4.4)

using the finite element method (FEM). All simulations were done with a time-

dependent transport of diluted species on rod-like structures of various

dimensions (similar to the realized pillar arrays), using a free tetrahedral mesh,

with a maximum mesh size of 0.5 μm and a minimum of 1 nm.


59

The boron (or phosphorus) oxide source was simulated as an infinite source of

dopant atoms, with a fixed surface concentration (~1022

atoms/cm3).

Three drive-in temperatures were simulated in time, i.e. 900, 1000 and

1050 °C. Although heating up and cooling down of the furnace was also

included in the simulation, the mentioned drive-in times always correspond to

the duration of the drive-in temperature step after stabilization to its desired

value.

3.3. Results and discussion

Figure 3.2 shows the schematic illustration of the fabrication of micropillars on

a base p-type wafer, radially doped with phosphorus. First, the backside of the

wafer was covered with silicon nitride, which acts as a diffusion barrier to

prevent the formation of a junction on the backside. The desired pattern of

micropillars was transferred to the wafer using standard photolithography, and

dry etching to achieve the desired height of the pillars. In order to fabricate a

radial p/n junction a phosphorus oxide was grown by SSD or CVD processes.

Subsequently, a thermal step was done at a set temperature and time, to

create a p/n junction with the targeted junction depth. Finally, aluminum

contacts were fabricated on the front and backside (upon removal of the SiRN

layer) of the wafer to ensure an Ohmic contact to the silicon. In case of ridges

and flat surfaces, the same procedure was followed, but then with larger

dimensions and without any photolithographic pattern, respectively.

Chapter 3

60

Figure 3.2: Schematic illustration of the fabrication of radial p/n junctions in silicon

micropillars. (A) Fabrication of silicon micropillars using DRIE on patterned photoresist on

a silicon wafer. (B) Removal of residual photoresist by O2 plasma etching. (C) Formation

of a phosphorus oxide layer, using CVD. (D) In-diffusion of phosphorus into the boron

doped base wafer. (E) Removal of silicon nitride backside by HF etching, immediately

followed by sputtering of the aluminum contacts. The same procedure was followed for

boron doping of n-type silicon wafers, with SSD instead of CVD for the deposition of the

dopant oxide layer.

3.3.1. Junction analysis on flat substrates

After the diffusion of the dopant, step D in Figure 3.2, the p/n junctions were

analyzed by different methods. For flat surfaces, ball grooving and SIMS

measurements were performed. Figure 3.3 shows typical grooves, under a

light microscope, formed on flat doped surfaces by a stainless steel ball before

(A, B, C) and after (D, E, F) staining. In case of an n-type silicon wafer that is

boron-doped via SSD (Figure 3.3A, D), the inner part after staining

(Figure 3.3D) shows the base n-type silicon and the gray-colored outer ring is

the p-doped layer. Conversely, for p-type wafers that were doped with

phosphorus by means of PECVD (Figure 3.3B, E) and LPCVD

(Figure 3.3C, F), the inner part (base p-type) is darker than the outer ring

(doped n-type), although this effect is less pronounced in the case of LPCVD

doping. Diameters of both circles in the stained images were measured with


61

image analysis software and junction depths (Table 3.1) were calculated by

means of Equation 3.1. Thus, although the ball grooving and staining

technique was originally developed for junctions with depths of >10 μm, it also

functions for junctions with a depth in the range of submicron to a few microns.

Figure 3.3: Optical microscopy images of flat, doped silicon samples after ball grooving,

before (A, B, C) or after (D, E, F) staining with CrO3/HF. (A, D) SSD-boron doped n-type

silicon (1050 °C, 15 min). (B, E) P-PECVD doped p-type silicon (1000 °C, 15 min). (C, F)

P-LPCVD doped p-type silicon (1050 °C, 15 min). Scale bars represent 200 µm.

Table 3.1: Junction depth values of boron (SSD) and phosphorus (CVD) doped samples,

based on data obtained from ball grooving and staining and from SIMS.

Staining (µm) SIMS (µm)

P-LPCVD 15 min, 1050 °C 1.1±0.1 1.1±0.1

P-PECVD 15 min, 1050 °C 1.0±0.1 -

P-APCVD 15 min, 1050 °C 2.8±0.1 3.0±0.2

P-APCVD 100 min, 1000 °C 2.3±0.1 2.4±0.2

B-SSD 15 min, 1000 °C 0.6±0.1 0.7±0.1

B-SSD 15 min, 1050 °C 1.0±0.1 1.3±0.1

B-SSD 120 min, 1050 °C 2.2±0.1 2.5±0.2

Chapter 3

62

Figure 3.4 shows depth profiles of dopants as measured by SIMS on various

flat-doped samples. As the base doping level of the silicon substrates was not

measured with SIMS, but only derived from the resistivity, an accurate

determination of the junction depth cannot be made.

Figure 3.4: SIMS depth profiles of dopant elements (B/P) of flat, doped samples obtained at

different in-diffusion temperature and time settings and using different doping processes (P-

LPCVD, P-APCVD and B-SSD). The marked area is an example of the linear regime, used to

extrapolate a more accurate junction depth, for boron doped (SSD) at 1050 °C for 15 min.

The base doping level varies from 5×1014

to 5×1015

atoms/cm3 which is in the

range of the measurement limitations of the SIMS system. Therefore an

extrapolation over the linear regime (as indicated in Figure 3.4) was used to

estimate the junction depths (Table 3.1), assuming an average doping level of

1015

atoms/cm3. The differences in junction depths as determined with the

staining method and the SIMS method are small, about 0.1-0.3 µm, where

SIMS indicates generally somewhat deeper junctions. Nevertheless, the

observed trends in junction depth as function of drive-in temperature and time

are identical for both methods.


63

When comparing the different doping methods for phosphorus, the junction

depths of the APCVD doped samples differed significantly from the other

doping techniques. For the same time and temperature settings

(15 min, 1050 °C), APCVD yielded a junction twice as deep as for LPCVD

(2.3 vs. 1.1 µm). The SIMS profiles (Figure 3.4) give additional insight in the

different doping mechanisms. For P-APCVD, the dopant concentration profiles

show a bend at about 1 µm, and the surface concentrations exceed

2×1020

atoms/cm3. This is not the case for P-LPCVD and B-SSD doping, for

which the diffusion profiles decrease monotonously.

In Figure 3.5, the experimentally determined junction depths are plotted

(symbols) for three different temperatures and various doping techniques.

Each symbol is an average over at least 5 measurements (ball grooving).

Moreover, FEM simulation results, assuming simple Fick‟s law diffusion, are

also given in Figure 3.5 (solid lines).

Figure 3.5: Junction depth as a function of drive-in time and temperature: solid lines

represent simulations and symbols represent experimental data by means of ball grooving

and staining. Error bars are not shown; the largest standard deviation was 0.09 μm.

Chapter 3

64

Clearly, most of the data points agree with the FEM simulations, except, as

expected, the phosphorus-based junctions realized by APCVD. In fact, the

junction depths obtained for this doping method are significantly larger than

predicted by modeling and those found experimentally using other doping

methods. This can be attributed to the high surface concentration of this

doping method. High (surface) concentrations of phosphorus can give rise to

anomalous kink-and-tail depth-diffusion profiles with a plateau region near the

surface.[26]

In case of sufficiently high P surface concentrations

(>2×1020

atoms/cm3 at a drive-in temperature of 1000 °C), the so-called

vacancy mechanism governs the dopant diffusion in the plateau region (at

depths up to ~1 μm), while the kick-out mechanism governs it in the deeper

regions. In other words, diffusion of self-interstitials – also named point

defects – dominates in the kink region, and P interstitials in the tail region.

Only at high P concentrations, the vacancy mechanism contributes to

P diffusion (and thereby enhances the overall dopant diffusion speed). The

changeover from the vacancy mechanism to the kick-out mechanism is

responsible for the appearance of the kink-and-tail depth-diffusion profiles

visible in Figure 3.4 (APCVD data). In contrast, for low P surface

concentrations, only the kick-out mechanism affects the depth-diffusion

profiles, and no plateau appears. In this case, Fick‟s diffusion law is valid as a

model for P (and B) diffusion into silicon, as shown for the investigated

PECVD, LPCVD, and SSD settings. Due to the anomalous diffusion

mechanism in the case of P-APCVD doping, this method is excluded from

further analysis.

3.3.2. Junction analysis in structured substrates

3D ridge and pillar structures, boron-doped using SSD (1050 °C for 120 min),

were investigated subsequently. Figure 3.6A and B show HR-SEM images of

cross sections of ridge samples after staining with CrO3/HF. Similar to staining

on flat-doped surfaces, the staining is clearly visible in terms of a line on the

junction interface. The junction depth of 2.2 µm agrees with FEM simulations

(Figure 3.6C) and with the staining experiments on flat surfaces (see above).


65

The latter indicates that ball grooving of flat surfaces suffices to get a good

indication of the junction depth also of micron-sized 3D structures. The sharp

edge on the top (convex corner Figure 3.6B) and the round shape in the

bottom corner (concave corner Figure 3.6C) are also present in the simulated

ridge (Figure 3.6A). The images and simulations clearly indicate that boron-

SSD on 3D structures yields a uniform thickness of the doped layer.

Figure 3.6: (A, B) Cross-sectional HR-SEM images (80° angle) of 100x30 μm ridges

(SSD-boron doped; 1050 °C, 120 min). Scale bars represent 3 µm. (C) Cross section of

FEM simulated doping (SSD-boron doped; 1050 °C, 120 min) of a ridge structure.

Subsequently, the staining method was applied to micropillar structures. Two

different approaches were used to stain the interior of pillars. In the first

approach, the top of doped pillars was removed by means of a maskless DRIE

step, as shown in Figure 3.7C. This enables a top view on such “chopped”

pillars with SEM imaging (Figure 3.7A). Chopped pillars were also exposed to

the staining solution, resulting in the appearance of a clear line on the inside of

the pillar, as shown in Figure 3.7B, which resembles the p/n interface. The

second approach employed FIB etching to laterally remove half of a pillar. This

enabled visualization of the junction along the height of a pillar (Figure 3.7D).

Chapter 3

66

Figure 3.7: (A, B) Top view SEM images of unstained (A) and stained (B) pillars (boron

doped SSD at 1050 °C, 120 min). (C) Schematic view of maskless DRIE etching in a pillar

(cross section), to reveal the interior of the pillar. The thick arrow indicates the imaging

direction of A and B. (D) Side view of a split (using FIB) and stained pillar. (E) FEM

simulation of a pillar with similar dimensions (4 µm width, 20 µm height, boron doped at

1050 °C, 15 min). Scale bars represent 2 μm.

In case of the first approach – pillar chopping and staining (Figure 3.7A, B) –

the stained pillar clearly reveals the junction and junction depth (2 µm). This

stained line was also observed for the second approach, in which a pillar was

cleaved vertically. As expected, the staining line perfectly follows the contour

of the pillar: a uniform thickness (2 µm) of the doped layer along the pillar

circumference can be seen. The difference in surface roughness at the FIB

interface visible between the left-hand and right-hand side of the cleaved pillar

in Figure 3.7D is an artifact from a second FIB step.


67

The seemingly thinner junction at the top side of the pillar is merely a result of

the large angle at which the image was taken. Junction depths as determined

with both approaches are in agreement with previous measurements on flat

samples (see above) and FEM simulations (Figure 3.7E, 2.2 µm).

Similar results, regarding uniform doping along the pillar height, were obtained

for P-LPCVD doped samples. In the case of P-PECVD doped pillars, no

contrast was visible along the pillar height, which is believed to be caused by

directionality during formation of the dopant layer. For this reason, the

P-PECVD samples were also excluded in the JV measurements.

3.3.3. Electrical characterization

In order to verify the influence of radial p/n junctions on light capturing

capabilities, JV measurements were performed on doped flat surfaces and

similarly radially doped micropillar arrays, i.e. SSD-boron on n-type silicon and

LPCVD-phosphorus on p-type silicon (1050 °C, 15 min). JV plots are shown in

Figure 3.8.

Chapter 3

68

Figure 3.8: JV measurements of different samples: flat junctions (continuous lines) and

radial junctions in pillar arrays (dashed lines) for boron and phosphorus dopants. The

dotted lines indicate the 1σ-range around the average (at least 5 samples were analyzed

for each configuration). The current density is normalized to the sample area (not the

actual surface area of the pillars).

The open-circuit voltage (VOC) for boron-doped samples is approximately

0.5 V, whereas for phosphorus doped samples the VOC is around 0.45 V,

which is slightly lower than the 0.5-0.7 V reported in literature for silicon.[1,2,27]

It

has to be noted that, in contrast to many literature studies, neither back

reflector nor surface passivation was applied in our work. For both boron and

phosphorus doping, the short-circuit current density (JSC) values were

significantly higher for pillar samples – 30 and 38 mA/cm2 for boron and

phosphorus doping, respectively – compared to doped flat samples (ca.

24 mA/cm2).

Using the fill factor (FF), VOC and JSC, the overall efficiency η can be calculated

(Equation 3.2):

(3.2)

where Pin is the input power, which is 100 mW/cm2 (AM 1.5).


69

For boron-doped samples, the efficiency increased from 8.3% for flat samples

to 9.4% for pillar arrays, whereas phosphorus-doped samples showed

η values of 6.4% and 11.0% for flat and pillared samples, respectively. These

efficiencies for radially doped p/n junctions are in agreement with literature

values, typically showing efficiencies above 5%.[1,2,19,27,28]

Thus, properly

doped radial p/n junctions indeed enhance the light trapping via an increase in

effective junction area on a given footprint (0.5 x 0.5 cm2).

A pillar array with a junction depth larger than 2 μm (SSD-boron of n-type

silicon, drive-in settings: 1050 °C/120 min) was also subjected to JV analysis.

In this case, the junction depth is larger than the pillar radius, leading to

completely doped-through pillars. Such over doped pillar arrays displayed a

low JSC value (7 mA/cm2), which can be attributed to a loss of effective junction

area on the 0.5 x 0.5 cm2 footprint: 35% of the sample footprint is covered with

pillars. Although the pillars themselves do lower the reflectivity of the sample,

this is apparently not sufficient to compensate for the loss in effective junction

area. As expected, over-doped pillars showed a poor efficiency (2%).

Altogether, these results show the potential of using radially doped micropillars

for more efficient light capturing, at the same time emphasizing the need for

proper control of the doping process to achieve the appropriate junction depth.

3.4. Conclusions

All investigated doping methods, i.e. SSD, LPCVD, APCVD, PECVD, gave

uniform p/n junctions on horizontal/flat surfaces. SSD and LPCVD also yielded

homogeneous junction depths on 3D structures (i.e. microridges, micropillars)

in silicon. Ball grooving and staining on flat surfaces yielded accurate values

for junction depths, and the values are similar to data based on HR-SEM (on

flat and 3D samples) and SIMS. Junctions made by doping using B-SSD,

P-LPCVD or P-PECVD can be accurately predicted using Fick‟s law. In case

of P-APCVD junctions, the measured dopant concentration profiles (and hence

junction depths) deviated from model results, typically resulting in much

Chapter 3

70

deeper junctions. This is attributed to an additional diffusion mechanism (i.e.

vacancy mechanism).

Radial junctions made by SSD (boron) and LPCVD (phosphorus) doping had

higher JSC values and efficiencies compared to doped flat surfaces. The

positive effect on light capturing by arrays of properly doped radial junctions

was further evidenced with experiments on over-doped pillar arrays, which

displayed an even lower JSC than doped flat substrates.

Future experiments will focus on the effect of the junction depth in micropillar

arrays and footprint size on the light capturing efficiency. Moreover, such pillar

arrays with radial junctions will be implemented in solar-to-fuel devices.

Acknowledgements

Roald Tiggelaar is acknowledged for the assistance with the experiments and

the discussions. Alexander Milbrat assisted with the JV setup and

measurements. Mark Smithers is acknowledged for the HR-SEM images,

Frans Segerink is thanked for the FIB experiments.


71

3.5. References

[1] E. Garnett, P. Yang, Nano Lett., 2010, 10, 1082-1087.

[2] M. C. Putnam, S. W. Boettcher, M. D. Kelzenberg, D. B. Turner-Evans, J. M. Spurgeon,

E. L. Warren, R. M. Briggs, N. S. Lewis, H. A. Atwater, Energy Environ. Sci., 2010, 3,

1037-1041.

[3] K. Q. Peng, S. T. Lee, Adv. Mater., 2011, 23, 198-215.

[4] V. Schmidt, J. V. Wittemann, U. Gösele, Chem. Rev., 2010, 110, 361-388.

[5] R. Kapadia, Z. Fan, K. Takei, A. Javey, Nano Energy, 2012, 1, 132-144.

[6] M. D. Kelzenberg, D. B. Turner-Evans, B. M. Kayes, M. A. Filler, M. C. Putnam, N. S.

Lewis, H. A. Atwater, Nano Lett., 2008, 8, 710-714.

[7] M. Gharghi, E. Fathi, B. Kante, S. Sivoththaman, X. Zhang, Nano Lett., 2012, 12, 6278-

6282.

[8] E. L. Warren, H. A. Atwater, N. S. Lewis, J. Phys. Chem. C, 2013, 118, 747-759.

[9] A. I. Hochbaum, P. Yang, Chem. Rev., 2009, 110, 527-546.

[10] I. Oh, J. Kye, S. Hwang, Nano Lett., 2011, 12, 298-302.

[11] Y. Hou, B. L. Abrams, P. C. K. Vesborg, M. E. Björketun, K. Herbst, L. Bech, A. M. Setti,

C. D. Damsgaard, T. Pedersen, O. Hansen, J. Rossmeisl, S. Dahl, J. K. Nørskov, I.

Chorkendorff, Nat. Mater., 2011, 10, 434-438.

[12] S. W. Boettcher, E. L. Warren, M. C. Putnam, E. A. Santori, D. Turner-Evans, M. D.

Kelzenberg, M. G. Walter, J. R. McKone, B. S. Brunschwig, H. A. Atwater, N. S. Lewis,

J. Am. Chem. Soc., 2011, 133, 1216-1219.

[13] E. L. Warren, J. R. McKone, H. A. Atwater, H. B. Gray, N. S. Lewis, Energy Environ.

Sci., 2012, 5, 9653-9661.

[14] S. Yu, F. Roemer, B. Witzigmann, J. Photon Energy, 2012, 2, 0280021-0280029.

[15] A. Mallorquí, E. Alarcón-Lladó, I. Mundet, A. Kiani, B. Demaurex, S. De Wolf, A. Menzel,

M. Zacharias, A. Fontcuberta i Morral, Nano Res., 2014, 1-9.

[16] A. C. Fischer, L. M. Belova, Y. G. M. Rikers, B. G. Malm, H. H. Radamson, M.

Kolahdouz, K. B. Gylfason, G. Stemme, F. Niklaus, Adv. Funct. Mater., 2012, 22, 4004-

4008.

[17] S. Ingole, P. Aella, P. Manandhar, S. B. Chikkannanavar, E. A. Akhadov, D. J. Smith, S.

T. Picraux, J. Appl. Phys., 2008, 103, 104302-104308.

[18] J. C. Ho, R. Yerushalmi, Z. A. Jacobson, Z. Fan, R. L. Alley, A. Javey, Nat. Mater.,

2008, 7, 62-67.

[19] J. Jin-Young, G. Zhongyi, J. Sang-Won, U. Han-Don, P. Kwang-Tae, H. Moon Seop, Y.

Jun Mo, L. Jung-Ho, Nanotechnology, 2010, 21, 445303.

[20] B. S. Meyerson, W. Olbricht, J. Electrochem. Soc., 1984, 131, 2361-2365.

[21] L. Yu, S. Misra, J. Wang, S. Qian, M. Foldyna, J. Xu, Y. Shi, E. Johnson, P. R. i.

Cabarrocas, Sci. Rep., 2014, 4, 4357.

[22] P. L. O‟Sullivan, F. H. Baumann, G. H. Gilmer, J. Appl. Phys., 2000, 88, 4061-4068.

[23] U.-H. Kwon, W.-J. Lee, Thin Solid Films, 2003, 445, 80-89.

[24] R. S. Muller, T. I. Kamins, M. Chan, Device Electronics for Integrated Circuits, John

Wiley & Sons Australia, Limited, 2003.

[25] W.C. Roman, L.R. Wilson, US Patent 3.830.665, 1974.

[26] M. Uematsu, J. Appl. Phys., 1997, 82, 2228-2246.

[27] D. R. Kim, C. H. Lee, P. M. Rao, I. S. Cho, X. Zheng, Nano Lett., 2011, 11, 2704-2708.

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72

This chapter has been published as: R. Elbersen, W.J.C Vijselaar, R.M.

Tiggelaar, J.G.E. Gardeniers, J. Huskens, Adv. Energy Mater., 2015, accepted

73

Chapter 4

Effects of Pillar Height and Junction

Depth on the Performance of Radially

Doped Silicon Pillar Arrays for Solar

Energy Applications

The effects of pillar height and junction depth on solar cell characteristics were

investigated in order to provide design rules for arrays of such pillars in solar

energy applications. Radially doped silicon pillar arrays were fabricated by

deep reactive ion etching (DRIE) of silicon substrates followed by the

introduction of dopant atoms by diffusion from a phosphorus oxide deposited

by low-pressure chemical vapor deposition. Increasing the height of the pillars

led to doubling of the efficiency from 6% for flat substrates to 12% for 40 µm

high pillars (at 900 nm junction depth), because of an increase of the total

junction area and lower optical reflection. For higher pillars, the current density

and efficiency decreased, which is attributed to the presence of larger amounts

of defect states at the surface introduced during the etching process. This

effect could be counteracted by a passivation layer (Al2O3) on the pillar

surface. Junction depths below 600 nm resulted in leaky diodes. An optimum

in efficiency (13%) was found for a junction depth of 790 nm (at 40 µm pillar

height). At increased junction depths, the efficiency decreased due to thinning

of the undoped core of the pillars, which was supported by the observation that

pillars with a diameter of 4 µm and a junction depth of 1.2 µm became less

efficient than flat silicon substrates.

Chapter 4

74

4.1. Introduction

Silicon is a widely used material in the field of photovoltaics and solar-to-fuel

devices, because of its outstanding electrical properties and the large toolbox

available for structuring of the material.[1-3]

Combined with the earth abundancy

and relatively low production costs, it is used extensively in the

nano/micro-fabrication area. Previous studies in the field of photovoltaics have

shown large improvement in solar cell performance, such as a lower reflectivity

of silicon, structuring by means of wet and dry etching as well as various

methods to introduce dopants.[4-7]

One of the recent developments is the shift

from planar to radial p/n-junctions using nano- or micropillars.[8,9]

The

advantage of pillars with a radial p-n junction for use in solar panels, and more

specifically in solar-to-fuel devices, is two-fold. First, the radial junction

decouples the direction of light incidence and charge transport processes,

reducing the recombination losses. Secondly, the high surface area for a given

footprint is ideal for catalysis and light absorption, as a lower reflectivity results

in improved light absorption.[10-12]

Already a few examples of full-scale (lab)

devices for solar-to-fuel have been reported, where hydrogen is produced in

an electrolyte using a silicon solar cell functionalized with proper catalysts.[13,14]

Optimization of the silicon solar cell is important for both photovoltaics and

solar-to-fuel applications, since higher efficiencies will ultimately affect their

economic benefit and thereby the commercial and industrial interest in solar

energy devices.

Pillar dimensions (height, width and density) and p/n junctions in the pillars

(radial vs. axial, depth and doping levels) have effects on all performance

parameters discussed above (light absorption, charge separation and surface

area) which ultimately determine device efficiency. Yet, the relationships

between these fabrication and performance aspects are difficult to predict and

decouple. For example, increasing the height of the pillars inherently increases

the total junction area present in the solar cell, and possibly decreases the

reflectivity of sunlight.[15]

Previous publications have shown a positive effect of

Effects of Pillar Height and Junction Depth on the Solar Cell Performance

75

increased pillar heights on the efficiency of solar cells.[16,17]

Voight et al. have

used simulations to predict the most efficient radius and height of a pillar.[16]

In summary, they found an optimum of 2 µm for the pillar diameter with a

corresponding height of 96 µm. Another important aspect in the design of the

pillar array is the diameter-over-pitch (D/P) ratio. A D/P ratio between

0.5-0.8 has been suggested, as this has shown the highest theoretical and

experimental efficiencies for various systems.[17-19]

The radial junction depth

variation in micropillars can be varied by tuning the doping process, and a

trend of improved JV characteristics for thinner junctions, down to 50 nm, has

been shown in simulations.[18]

A thin junction leads to less recombination,

which implies that the outer highly doped shell of a radially doped micropillar

should be kept thin, but also should keep its carrier separation functionality.

Pillars with a deep junction may suffer from bulk recombination, which

negatively affects the efficiency of the solar cell.[20]

Clearly, an optimal radial

junction depth exists for any given configuration of a solar cell (i.e. pillar

diameter, pitch, height and specimen footprint) that yields the highest overall

efficiency. To date, no studies have shown the joint optimization of pillar height

and junction depth.

Here, we show the optimization of the electrical performance of radially doped

arrays of micropillars with a fixed diameter, pitch and footprint by variation of

the pillar height and junction depth (xj). Arrays were used with a pillar diameter

of 4 µm in combination with a pitch of 6 µm (D/P = 0.67), and heights in the

range of 0 to 60 µm. At the same time, a full range of junction depths, from

shallow (~140 nm) to deep junctions (~1640 nm), has been realized using low-

pressure chemical vapor deposition (LPCVD) for the creation of the required

dopant source, i.e. a thin layer of phosphorus oxide. Such a sweep of different

junction depths can lead to the optimization of the solar cell, for a given doping

technique. Furthermore, preliminary experiments are discussed to further

improve the efficiency of pillar array-based solar cells by depositing a

passivation coating on the surface of the micropillars.

Chapter 4

76


4.2.1. Fabrication of radial p/n junctions in silicon micropillar arrays

Radial p/n junctions were prepared as previously reported, and shown in

Figure 4.1.[7]

In short, p-type silicon substrates ((100) oriented, 5-10 Ω cm, 525

µm thickness, single side polished, Okmetic Finland) were covered with 100

nm silicon nitride (SiNx). On the front side, after removal of the SiNx, the

substrate was patterned with arrays of hexagonally packed dots (4 µm

diameter, 6 µm pitch, 0.5 x 0.5 cm2 cell size on a specimen of 2 x 2 cm

2) by

standard photolithography (Olin 907-17 photoresist). This pattern was

transferred into the silicon by deep reactive ion etching (CF-chemistry, Adixen

AMS100SE), and the height of the pillar arrays was controlled by the etching

time, whereby the etch rate of silicon was ca. 3.2 µm/min. After removal of the

photoresist layer and residual fluorocarbons using an oxygen plasma, a

phosphorus oxide (approximately 400 nm thick) was grown by LPCVD

(Tempress tube furnace), using phosphine (PH3) as a dopant precursor.

Dopant transfer into the pillars was performed at temperatures ranging from

900 to 1100 °C and various drive-in times (5-60 min) under a stream of N2.

The combination of drive-in time and temperature determines the radial

junction depth in the pillars. After the thermal diffusion step, the phosphorus

oxide was removed by immersion in BHF (NH4F-buffered aqueous HF) for

10 min, as well as stripping off the silicon nitride from the backside of the

substrate in 50% aqueous HF (30 min). Values of the junction depth were

predicted by FEM (Finite Element Modeling, COMSOL Multiphysics 4.2)

simulations and verified with ball grooving and staining.[7]


77

Figure 4.1: Schematic fabrication process. (A) Removal of topside silicon nitride, followed

by photolithography. (B) Deep reactive ion etching of Si. (C) Low-pressure chemical vapor

deposition of phosphorus oxide. (D). Drive-in diffusion of phosphorus, resulting in radial

p/n junctions. (E) Removal of silicon nitride and deposition of metal front and back contact.

4.2.2. Atomic layer deposition

To reduce the reflectivity of the micropillar arrays, a layer (42 nm) of aluminum

oxide (Al2O3) was conformally coated on several samples, using a thermal

ALD process at 100 °C (Picosun P-300S reactor). Trimethyl-aluminum (TMA)

and H2O were used as precursors and N2 was the carrier gas, yielding a

growth rate of 0.83 Å per cycle (after initial growth stabilization). The time for

one complete Al2O3 ALD cycle was 9.3 s, where each cycle was defined as:

0.1 s TMA exposure, 4 s N2 purge, 0.2 s H2O exposure, and 5 s N2 purge.


To ensure Ohmic contact to the solar cells, 1 µm aluminum/silicon alloy

(99% Al, 1% Si) was sputtered (Oxford PL 400) on the front and backside of

each specimen, where on the front side a shadow mask was applied to protect

the pillar arrays from coating. To measure the photovoltaic characteristics, the

samples were positioned perpendicular to a 300 W xenon arc light source with

an intensity of 1 sun (AMG 1.5). JV measurements were recorded on a

VersaSTAT 4 potentiostat for a linear voltage sweep from -0.7 to 0.7 V at a

rate of 0.2 V/s. For each setting (pillar height or junction depth) at least four

different samples were measured.

Chapter 4

78


After DRIE fabrication of the micropillars, a few samples were broken and the

cross sections were taken in a scanning electron microscope (Figure 4.2). Due

to the nature of the etching process (B-HARS) on high aspect ratio structures,

a slight tapering occurred at about 33% from the top of the pillars. This effect

was more pronounced for the 60 µm pillars (18 min etching), where the

diameter decreased approximately 500-600 nm, compared to 100-200 nm in

the case of 40 µm (12 min etching). The pillars were still broad enough to

prevent an overdoping of the pillar arrays, and losing the beneficial effect of a

radial p/n junction, however it can potentially influence the measurements.

Figure 4.2: Cross-sectional SEM images of micropillar arrays with a height of 40 µm (A)

and 60 µm (B).

The combinations of drive-in temperature and time used here led to junction

depths between 140-1640 nm, as predicted by FEM simulations,[7]

and were

experimentally verified by ball grooving and staining experiments on five

different flat samples (140, 790, 900, 1170 and 1550 nm, see Chapter 3 for

methodology). Since the phosphorus surface concentration upon drive-in is

relatively low, transport of phosphorus into silicon can be described by Fick‟s

law of diffusion.[21]

The influence of the height of silicon micropillars with incorporated radial p/n

junctions was investigated by analyzing their electrical properties. Figure 4.3

shows the JV characteristics of samples with seven different pillar heights, i.e.

from flat to 60 µm. All samples had a junction depth of 900 nm. The large


79

increase in both current density (JSC) as well as open circuit voltage (VOC) for a

sample with 10 μm high pillars compared to a flat sample (Figure 4.3A)

indicates that even a shallow structure already drastically improves the light

absorbing properties of the solar cell. This can be explained by both an

increase in total junction area and a decrease in reflectively. The latter is

supported by previously reported work by various groups, who showed that the

reflectivity of polished, flat silicon (ca. 35%) decreases to values below 10% by

even the smallest amount of micro/nano structuring.[1,22,23]

The parameters JSC

and VOC were plotted as a function of the pillar height (Figure 4.3B), along with

their respective fill factors (FF) and efficiencies (η), as shown in Figure 4.3C. A

monotonous increase of VOC is visible, from 400 mV for flat samples to 460 mV

for 60 µm high pillars. This is attributed to the increase of the total surface area

– and concomitantly of the junction area – of the solar cell on the given

footprint, which is 5 times higher for 10 µm high pillars and increases to

22 times for the 60 µm high pillars. The JSC values, after a gradual increase

with pillar height up to 40 µm, decrease again for larger pillar heights. This is

reflected in the overall efficiency: since the fill factor remains fairly constant,

the efficiency exhibits a maximum for a pillar height of 40 µm. We conclude

that for these pillar arrays, with a 4 µm diameter, 2 µm spacing and a junction

depth of 900 nm, the optimum pillar height is 40 µm.

Chapter 4

80

Figure 4.3: (A) JV measurements of n-emitter (900 nm junction depth) p-type base

substrates for different pillar heights, each line is the average of at least 4 different

samples of the same setting. (B) Current density and open circuit voltage as a function of

the pillar height, error bars indicate the 1σ-range. (C) Corresponding fill factors and

efficiencies of the average values shown in B. (D) JV measurements on specimen with 60

µm high pillars before and after ALD deposition of 42 nm Al2O3.

We attribute the decrease in current density for heights above 40 μm to

surface recombination by an increasing number of defect states at the, equally

increasing, outer surface of the silicon pillars. These defects have been

induced by the dry etching method in combination with the circular pillar

design, because of which the sidewalls of the pillars are not terminated by a

low-index crystallographic plane of silicon. This has led to defects at the

surface of the silicon pillar compared to (100) silicon.[24]

In addition, the

working principle of the applied „Bosch‟ process, which is a cyclic process

involving gas pulses of SF6 (etching gas) and C4F8 (passivation gas), has led

to scalloping of the pillar sides,[25]

which further increases the amount of defect

states.[24]

Cryogenic etching would lead to pillars with a lower sidewall

roughness without scallops, however, this method did not produce good

quality micropillars with heights above 20 μm at the pitch used here.


81

To reduce surface recombination, a passivation layer (42 nm) of Al2O3 was

deposited by atomic layer deposition (ALD) on a sample with 60 µm pillars,

after initial JV analysis of the same specimen. The passivation layer resulted in

increased JSC (Figure 4.3D), open circuit voltage and fill factor. The increase in

JSC may also be explained by the anti-reflective properties of the Al2O3 layer.[26]

The JV curves were fitted to determine the shunt (RSH) and series (RS)

resistances, and the open circuit voltage (VOC). Upon application of the

passivation layer, RSH was found to increase from 308 to 1064 Ω cm2 and RS

decreased from 3.1 to 2.4 Ω cm2, whereas the VOC barely changed. These

improvements show that surface defects indeed play an important role for

arrays with higher pillar, and that a conformal coating of Al2O3 can be used to

reduce the impact of the defects.

Subsequently, the junction depth was varied by changing the drive-in

temperature between 900-1100 °C and the drive-in time between 5-60 min

using pillar arrays with the optimum pillar height of 40 µm. Figure 4.4 shows JV

measurements for twelve different junction depths. Junctions made at 900 or

950 °C (see Figure 4.4A) did not give properly functioning diodes, most likely

due to too low dopant concentrations (<2x1019

atoms/cm3 surface

concentration for 1050 °C as determined by SIMS, see Figure 4.5). In case of

a drive-in temperature of 1000 °C, both the series and shunt resistances

decreased significantly with the drive-in time, resulting in a proper diode

(Figure 4.4A). As a consequence, higher current densities and correspondingly

increased open circuit voltages were observed. The increase in JSC and VOC

for thicker junctions continued until a junction depth of 790 nm (Figure 4.4B).

For junctions ≥90 nm the current density dropped, and the VOC also decreased

slightly, but not as pronounced as JSC (Figure 4.4C). The series and shunt

resistances remained rather constant for larger junction depths, due to which

the FF remained constant as well at about 70% (Figure 4.4D). For xj values

≥790 nm bulk recombination became significant, resulting in lower efficiencies.

Chapter 4

82

Figure 4.4: JV measurements of various n-doped p-type base micropillar arrays for

different junction depths, each line represents the average of at least 4 different samples

of the same setting. (A) JV data for junction depths between 140-660 nm. (B) JV data for

junction depths between 790-1640 nm. (C) Current density and open circuit voltage as a

function of the junction depth shown in A and B, error bars indicate the 1σ-range.

(D) Corresponding fill factor and efficiency of the average values shown in C.

Figure 4.5: SIMS measurement of a flat sample, doped with LPCVD of phosphorus at

1050 °C, for 15 min. The dotted line indicates the base boron concentration of the used

wafer, prior to doping, estimated by a 4-point probe measurement.


83

For junctions above 1.55 μm JSC dropped even below the current density of flat

samples (22 mA/cm2, see Figure 4.3A). Some insight in this behavior can be

obtained by calculating the doping profile plus the depletion zone in the radially

doped pillars. For n+/p junctions as used here, the donor density (ND) is much

larger than the acceptor density (NA), therefore the depletion zone Wdep can be

approximated by:[27]

√

(4.1)

where εSi is the permittivity of silicon, Φbi is the built-in potential (V), q is the

electric charge and NA is the acceptor density (atoms/cm3). The built-in voltage

is defined as:[27]

(4.2)

where k is the Boltzmann constant, T is the temperature (K), and ni is the

intrinsic carrier concentration (atoms/cm3). Equation 4.2 gives a built-in

potential of 0.67 V for a base doping level of 2×1015

atoms/cm3. Wdep largely

depends on NA, and since the used substrates have a resistivity of 5-10 Ω cm,

the depletion zone was calculated to be in the range of 584 to 808 nm.

Because the doping level of the introduced n dopants is much higher than the

base p doping, the depletion zone can be expected to be located mainly from

the junction depth inward into the core of the pillar. This implies that 4 μm

pillars with junctions deeper than 1.2 – 1.4 µm will have no p-type core left.

This agrees favorably with the experimental data for junction depths of

1.37 μm and higher (Figure 4.4B). Summarizing, our pillar arrays, in

combination with LPCVD phosphorus doping, show an optimal xj value of

approximately 800 nm. Simulations have shown that thinner junctions should

perform better.[18,20]

To make such thinner junctions experimentally with good

diode quality, a doping method should be used which gives a higher dopant

surface concentration.

Chapter 4

84

4.4. Conclusions

The solar cell performance of radially n-doped silicon pillar arrays was studied

as a function of the pillar height and junction depth. Compared to flat samples,

pillar arrays gave rise to a large increase in current density, from 22 mA/cm2

for flat samples (6% efficiency) up to 37 mA/cm2 for 40 µm pillar arrays

(12% efficiency, 900 nm junction). However, for heights of 50 and 60 µm, JSC

decreased, which is attributed to increased numbers of surface defect states,

resulting from the deep reactive ion etching process. This effect was

counteracted by an Al2O3 passivation layer. The LPCVD process for

phosphorus doping did not give proper diodes for shallow radial junctions. The

optimum junction depth found experimentally was 790 nm (13% efficiency for

40 µm high pillars). For deeper junctions, a steady decrease of JSC was

observed, which is explained by the narrowing p core of the pillars, resulting in

efficiencies poorer than flat silicon surfaces for junction depths exceeding

approximately 1.2 µm. Further research towards more efficient silicon pillar

array solar cells should focus on the fabrication of shallower junctions, <600

nm, using a more effective doping technique, in combination with optimized

passivation and anti-reflective coatings. In addition, future research should

also verify what the optimal pillar configuration is (e.g. nano/micro-scale),

combined with different D/P ratios.

Acknowledgements

Wouter Vijselaar is acknowledged for the discussions about this chapter and

for his assistance with the JV measurements. Roald Tiggelaar is thanked for

corrections and discussions on this chapter.


85

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Lewis, Chem. Rev., 2010, 110, 6446-6473. [3] Y. Li, Q. Chen, D. He, J. Li, Nano Energy, 2014, 7, 10-24. [4] J. Jin-Young, G. Zhongyi, J. Sang-Won, U. Han-Don, P. Kwang-Tae, H. Moon Seop, Y.

Jun Mo, L. Jung-Ho, Nanotechnology, 2010, 21, 445303. [5] B.M. Kayes, M.A. Filler, M.C. Putnam, M.D. Kelzenberg, N.S. Lewis, H.A. Atwater, Appl.

Phys. Lett., 2007, 91, 103110. [6] K. Peng, A. Lu, R. Zhang, S.-T. Lee, Adv. Funct. Mater., 2008, 18, 3026-3035. [7] R. Elbersen, R.M. Tiggelaar, A. Milbrat, G. Mul, H. Gardeniers, J. Huskens, Adv. Energy

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Kelzenberg, M.G. Walter, J.R. McKone, B.S. Brunschwig, H.A. Atwater, N.S. Lewis, J. Am. Chem. Soc., 2011, 133, 1216-1219.

[12] Y. Hou, B.L. Abrams, P.C.K. Vesborg, M.E. Björketun, K. Herbst, L. Bech, A.M. Setti, C.D. Damsgaard, T. Pedersen, O. Hansen, J. Rossmeisl, S. Dahl, J.K. Nørskov, I. Chorkendorff, Nat. Mater., 2011, 10, 434-438.

[13] S.Y. Reece, J.A. Hamel, K. Sung, T.D. Jarvi, A.J. Esswein, J.J.H. Pijpers, D.G. Nocera, Science, 2011, 334, 645-648.

[14] E.L. Warren, H.A. Atwater, N.S. Lewis, J. Phys. Chem. C, 2013, 118, 747-759. [15] M.D. Kelzenberg, S.W. Boettcher, J.A. Petykiewicz, D.B. Turner-Evans, M.C. Putnam,

E.L. Warren, J.M. Spurgeon, R.M. Briggs, N.S. Lewis, H.A. Atwater, Nat. Mater., 2010, 9, 239-244.

[16] F. Voigt, T. Stelzner, S. Christiansen, Prog. Photovolt. Res. Appl., 2012, 21, 1567-1579. [17] D. Zhou, Y. Pennec, B. Djafari-Rouhani, O. Cristini-Robbe, T. Xu, Y. Lambert, Y.

Deblock, M. Faucher, D. Stiévenard, J. Appl. Phys., 2014, 115, 134304. [18] F. Wang, H. Yu, J. Li, S. Wong, X.W. Sun, X. Wang, H. Zheng, J. Appl. Phys., 2011,

109, 114301. [19] J. Li, H. Yu, S.M. Wong, G. Zhang, X. Sun, P.G.-Q. Lo, D.-L. Kwong, Appl. Phys. Lett.,

2009, 95, 243113. [20] A. Dalmau Mallorquí, F.M. Epple, D. Fan, O. Demichel, A. Fontcuberta i Morral, Phys.

Status Solidi A, 2012, 209, 1588-1591. [21] M. Uematsu, J. Appl. Phys., 1997, 82, 2228-2246. [22] O. Gunawan, K. Wang, B. Fallahazad, Y. Zhang, E. Tutuc, S. Guha, Prog. Photovolt.

Res. Appl., 2011, 19, 307-312. [23] H. Xu, N. Lu, D. Qi, J. Hao, L. Gao, B. Zhang and L. Chi, Small, 2008, 4, 1972-1975. [24] L.-B. Luo, X.-B. Yang, F.-X. Liang, H. Xu, Y. Zhao, X. Xie, W.-F. Zhang, S.-T. Lee, J.

Phys. Chem. C, 2011, 115, 18453-18458. [25] H. Jansen, M. de Boer, S. Unnikrishnan, M.C. Louwerse and M. Elwenspoek, J.

Micromech. Microeng., 2009, 19, 033001. [26] G. Dingemans, R. Seguin, P. Engelhart, M.C.M. van de Sanden, W.M.M. Kessels, Phys.

Status Solidi RRL, 2010, 4, 10-12. [27] C.C. Hu, Modern Semiconductor Devices for Integrated Circuits, Prentice Hall, United

States, 2009.

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87

Chapter 5

Electrical Characterization of Silicon

Micropillars with Radial p/n Junctions

Containing Passivation and Anti-

Reflection Coatings

The effects of anti-reflective and passivation layers were investigated to

optimize hexagonal packed silicon micropillar arrays, with radial p/n junctions

incorporated. These anti-reflection coatings (Al2O3, SiO2, SiNx and ITO) were

first grown on flat solar cells with varying thickness, to verify the optimal

thickness for light capturing calculated from theory by the Fresnel equations.

Al2O3, SiO2, and SiNx were chosen because of the possible two-fold

improvement function, namely passivation and anti-reflection properties. ITO

was chosen because of the three-fold function, passivation, anti-reflection and

conductive properties. These layers were grown on both n-type base

(p-emitter) and p-type base (n-emitter) silicon pillar substrates with radial p/n

junctions, using different methods. Upon analysis of these structures using

high-resolution scanning electron microscopy, atomic layer deposition of Al2O3

gave the best uniformity over the whole pillar range, compared to a

low-pressure chemical vapor deposition of SiO2, SiNx, and sputtering of ITO.

For the latter three materials coatings, the layers were not homogeneously

distributed, but this was of no influence on the properties of the coatings. For

ITO, a loss of indium atoms was visible by HR-SEM. In terms of electrical

characterization, all samples, with the exception of ITO, outperformed the flat

silicon solar cell. The Al2O3 samples performed best, for both p- and n-type

base pillars, increasing the efficiency from 6.1 to 13.4% (p-type) and 7.4 to

10.1% (n-type).

Chapter 5

88

5.1. Introduction

Silicon has been used as a materials in photovoltaic (PV) cells, and have been

applied intensively for many decades.[1-3]

Silicon is an earth abundant, stable

and non-toxic semiconductor, in addition, the knowledge gained in the fields of

nano/micro-engineering of silicon enabled the fabrication of complex silicon

solar cells. In particular, the development from 2D to 3D structures has

enabled the fabrication of nano/micropillar structures with radial junctions[4-6]

and their use in PV and solar-to-fuel devices.[7-9]

These nano/micropillars have

gained increasing attention, owing to the advantages of an increase in junction

area for a given footprint, as well as their ability to orthogonally decouple the

directions of incoming light and charge separation.[10,11]

Moreover, micropillars

(and other microstructures such as pyramids, trenches, and surface

roughening) decrease the reflectivity of a silicon surface and thus increase the

amount of charges that can be theoretically collected from a given footprint or

surface area.[4,12,13]

On the other hand, the efficiency of a solar cell is

determined, among other variables, by the amount of collected charges, which

is lowered by the extent of recombination in the solar cell and by the reflected

light. Especially for high aspect ratio 3D nano/microstructures, surface

recombination is an important factor, due to the increased surface area.

Surface recombination can be reduced by surface passivation. Surface

passivation methods can be subdivided into two categories: chemical and

field-effect passivation.[14,15]

Recombination consumes both an electron and a

hole, therefore if either one is trapped, the probability for recombination

increases significantly. In reality, the energy trap states are associated with

surface defects (for example, dangling bonds) and are distributed throughout

the band gap due to slight variations in structure and bond angle. These

surface defects can be reduced by the application of a surface coating, which

method is referred to as chemical passivation, which effectively reduces the

recombination rate.[16]

Another way to inhibit recombination is by a significant

Radial p/n Junctions Containing Passivation and Anti-Reflection Coatings

89

reduction in the density of the minority charge carriers at the surface by an

electric field. An electric field can be induced by means of the introduction of

fixed charges at the surface of the crystalline silicon (c-Si). This is called

field-effect passivation.[17,18]

Surface coatings have multiple influences on the performance of a silicon solar

cell, foremost by their role in surface passivation.[19,20]

Already a relatively thin

layer, of a few nanometers, is sufficient to obtain either or both chemical and

field-effect passivation. If the thickness of the passivation layer is increased,

the coating can also function as an anti-reflective coating (AR coating),

provided that it has the correct thickness (i.e. tens of nanometers), a low

extinction coefficient, and a refractive index that is lower than that of

silicon.[21,22]

Aluminum oxide (Al2O3), silicon-rich silicon nitride (SiNx), and

silicon dioxide (SiO2) are often used, non-conducting surface coatings. An

electrically conductive and optically transparent coating can improve the

efficiency even further, by enhancing the charge collection at the emitter,

thereby effectively reducing the distance that charges have to travel through

the emitter. Such a coating can thus fulfill a three-fold function: as a

passivation layer, as an AR coating, and in the reduction of the resistance in

the cell. Transparent conductive oxides are such triple-function coatings, and

indium tin oxide (ITO) is the most widely applied.[23-25]

Here, we show the realization and characterization of various surface coatings

on micropillar arrays with a radial p/n junction, to function as a passivation and

AR layer, in order to increase the overall efficiency of PV cells. In order to

function as AR coating, different optimized thicknesses are required on p- and

n-type silicon solar cells. To find the optimal thickness, the performance of

each coating has been simulated by means of finite element modeling, in order

to predict the reflectivity of silicon upon the structuring with arrays of

micropillars and applying an AR coating. For the deposition of non-conductive

coatings, two different techniques have been used: atomic layer deposition

(ALD) of Al2O3 and low-pressure chemical vapor deposition (LPCVD) of SiNx

and SiO2. In addition, we have investigated the conformality of these layers, by

Chapter 5

90

analyzing the thickness on the sidewalls of the silicon micropillars, and

evaluated the electrical characteristics of the coated solar cells. The 3D

thickness analysis has been achieved by the combination of focused ion beam

(FIB) etching and high resolution scanning electron microscopy (HR-SEM).


5.2.1. Finite Element Simulations of the reflectivity of silicon micro pillars

The reflectivity of cubic packed micropillar arrays was simulated using a finite

element modeling package (COMSOL Multiphysics 4.4). The simulation was

performed by a parametric sweep (20 nm step) in the wavelength domain of

visible light (400 – 1100 nm). The pitch and diameter of the micropillars were

set to 6 and 4 μm respectively, and the height of the micropillars was varied

between 0 and 40 μm (similar to the experimentally realized pillar arrays). The

slab of silicon underneath the micropillar array was limited to 1 μm. The

footprint of the fabricated arrays was 5 x 5 mm2, which is orders of magnitude

larger than the wavelength of the incoming light, therefore we only simulated

one pillar of which the outcome was periodically repeated in the lateral

directions. For this reason, the side boundaries of the simulation had a Floquet

periodicity. The incoming light was a plane wave in the z-direction and had an

input power of 1 W. The maximum free triangular mesh size in the used

materials (silicon and air) was set to 1/5 of the minimum wavelength in the

material. Furthermore, the opposing boundaries were symmetrical with respect

to each other to ensure the Floquet periodicity. The realized and simulated

pillar geometries are depicted below (Figure 5.1).


91

Figure 5.1: The real and simulated geometry of the COMSOL simulation. Note the curved

bottom of the pillar.

5.2.2. Fabrication of radial p/n junctions in silicon micropillar arrays

Figure 5.2 gives a schematic representation of the fabrication and coating of

an array of micropillars with radial p/n junctions. P- and n-type silicon (100)

substrates, with resistivities of 5-10 Ω cm for p-type and 1-10 Ω cm for n-type,

100 mm diameter, 525 μm (p-type) and 375 μm (n-type) thickness, single side

polished (Okmetic Finland), were prepared as previously reported.[26]

In short,

substrates were cleaned and covered with 100 nm silicon-rich silicon nitride

(SiNx), via LPCVD. The silicon nitride on the front side of the wafer was

removed by reactive ion etching (RIE, Adixen AMS100DE), and cleaned by

means of oxygen plasma (30 min) and piranha (mixture of sulfuric acid and

30% aqueous hydrogen peroxide, 3:1 (v/v), 20 min). By means of standard

photolithography, squares (5 x 5 mm2) with hexagonally packed circles

(4 µm diameter, 2 µm spacing) were defined in a photoresist polymer (Olin

906-12). Silicon micropillars (40 µm in height) were etched into the silicon

substrate by deep reactive ion etching (DRIE, Bosch process) and the

substrates were cleaned subsequently in oxygen plasma (30 min) and piranha

(20 min) to remove the photoresist and fluorocarbon residues. P/n and n/p

junctions were formed by the deposition of boron oxide (using solid source

dotation, SSD) and phosphorus oxide (LPCVD), respectively.

Chapter 5

92

For SSD of boron, boron nitride wafers were placed in between the silicon

target wafers and, under a flow of 6000 sccm O2, a boron oxide layer was

formed on the silicon surface. In case of the LPCVD of phosphorus, a mixture

of 330 sccm PH3 and 50 sccm O2 was supplied for 45 min at 350 mTorr in

order to deposit the phosphorus oxide on the silicon surface. The formed

dopant oxide layers were then annealed at 1050 °C for 15 min to accomplish

diffusion of the dopant into the silicon micropillars, to form the proper radial

junction. Prior to the deposition of the passivation layers, the dopant oxide was

stripped in buffered hydrogen fluoride solution (BHF, 10 min), upon which the

wafers returned to their hydrophobic state. Subsequently, the wafers were

cleaned by immersion in 100% nitric acid (HNO3, 2x 5 min), fuming 69% nitric

acid (10 min) and immersion in 1% aqueous hydrofluoric acid (HF) to remove

the native oxide (1 min). The passivation layers were applied using different

methods as described in detail in sections 5.2.3-5.2.5. In short, sputtering was

chosen as a control, because the directionality of this deposition technique is

expected to lead to a non-conformal coating of high aspect ratio

microstructures, which then can be compared with the highly conformal

methods of LPCVD and ALD. Ohmic contacts were realized by selectively

removing the surface coating around the pillar arrays by completely filling and

covering the pillar arrays with photoresist. HMDS was spin-coated in between

the pillar arrays (4000 rpm, 2 min), and subsequently AZ9260 photoresist was

spin-coated on the samples (1000 rpm, 4 min). The samples were dried

overnight at 10-3

mbar at room temperature. Hereafter, the samples were

exposed to photolithography (3 times 10 s UV, 10 s delay) and developed

(8 min). Al2O3 and SiO2 were both stripped by wet etching in BHF (etch rates:

180 nm/min and 210 nm/min, respectively), SiNx was dry etched by RIE

(Adixen AMS100DE). The last step was removal of the photoresist mask layer

and fluorocarbon residues using oxygen plasma (Tepla360). An Ohmic contact

(1 µm, Al/Si, 99/1%) was sputtered (Oxford PL400) onto the backside of the

wafer and onto the front side, the latter by means of a shadow mask to prevent

deposition on the pillars arrays.


93

Figure 5.2: Schematic fabrication process. (A) Deep reactive ion etching of a silicon wafer

with a photoresist pattern on the front side and silicon-rich silicon nitride on the backside.

(B) Deposition of the dopant oxide by either SSD (boron) or LPCVD (phosphorus). (C)

Formation of the radial junction, by a drive-in step at 1050 °C for 15 min. (D). Deposition of

a passivation layer by either ALD (Al2O3), LPCVD (SiO2, SiNX) or sputtering (ITO). (E)

Removal of the silicon nitride and deposition of aluminum front and back contact by

sputtering.

5.2.3. Atomic layer deposition

To reduce the reflectivity and to passivate the micropillar arrays, a layer of

aluminum oxide was conformally coated onto the pillar arrays. Al2O3 films were

grown in a Picosun P-300S reactor by a thermal ALD process at 100 °C.

Trimethyl-aluminum (TMA) and H2O were used as precursors and N2 was the

carrier gas, yielding a growth rate of 0.83 Å per cycle (after initial growth

stabilization). The time for one complete Al2O3 ALD cycle was 9.3 s, where

each cycle was defined as: 0.1 s TMA exposure, 4 s N2 purge, 0.2 s H2O

exposure, and 5 s N2 purge.

5.2.4. Low-pressure chemical vapor deposition

The deposition of silicon oxide and silicon nitride films was done by LPCVD.

SiO2 was grown at 725 °C with a 50 sccm tetraethyl orthosilicate flow

(200 mTorr, 8.1 nm/min deposition rate). For SiNx, a flow of 50 sccm SiH2Cl2

and 150 sccm NH3 was used at a pressure of 250 mTorr at 825 °C

(6.6 nm/min deposition rate).

Chapter 5

94

5.2.5. Sputtering

Indium tin oxide (ITO) was deposited by means of an in-house built sputter

device. The silicon target wafer was placed on a rotating chuck (5 rpm),

44 mm from the ITO source, in a vacuum chamber (5.5 x 10-3

mbar) with a

40 sccm flow of argon in the reactor chamber. The ITO source had an angle of

45° with respect to the wafer surface. By means of a DC power of 50 W and a

20 sccm argon flow, ITO was sputtered on the silicon substrate (2.6 nm/min).

5.2.6. Focused ion beam

FIB structures were made with a Nova 600 Dual Beam – SEM/FIB setup. A

Ga+ liquid metal ion source was used to mill away approximately half of a

single pillar in the z-direction with respect to the footprint of an array, with a

beam current of 0.92 nA and a 10 kV extraction voltage.


To measure the electrical characteristics of the radial p/n junctions, samples

were positioned perpendicular to a 300 W xenon arc light source, with an

intensity of one sun (AMG 1.5). JV measurements were recorded on a

VersaSTAT 4 potentiostat using a linear voltage sweep from -0.7 to 0.7 V at a

rate of 0.2 V/s. For each variation in sample (i.e. type of coating and/or layer

thickness), at least four specimens were measured. Averages are given in

each figure and standard deviations are listed in the accompanying table.


5.3.1. Simulations

Infinite flat silicon substrates reflect 35% of the incoming light. This can be

analytically calculated by the Fresnel equations (Figure 5.3, analytical model).

In order to enhance the overall efficiency of a PV cell, reduction of reflection of

is of crucial importance. This is done by either an anti-reflection coating,

structuring the surface or a combination of both. In order to apply a correct

coating thickness on the surface to maximize the solar cells electrical output,


95

the reflection of the structured surface as function of wavelength is needed.

FEM is a powerful tool to simulate structures over a broad wavelength

spectrum. In order to confirm the FEM simulation, it is compared to the

analytical Fresnel model. As can be seen in Figure 5.3A, there is fairly good

agreement between the analytical Fresnel model and the FEM simulation. The

periodical ripples are due to simulating only a slab of silicon with a thickness of

1 μm. This introduces a double air-silicon interface (front- and backside) and

gives rise to an interference pattern, known as the Fabry-Perot effect. The

analytical model assumes an infinite thick slab and has only one silicon/air

interface, ergo, no interference pattern is visible. The reflectivity is lowered

substantially upon the addition of pillars with a height of 5 μm (Figure 5.3A)

and lowered even further by increasing the height of the pillars up to 40 µm.

Based on the FEM simulations, we postulate that light absorption for this

hexagonal packing of the pillar array with a height of 40 μm is limited by the

packing density of the pillar arrays within the footprint. Since the diameter of

the pillars is an order of magnitude larger than the wavelength of the incoming

light, the top surfaces of the pillars will reflect light as a flat surface. Light

entering the space in between the pillars will be scattered multiple times to

such an extent that it will be absorbed by the pillars. The top surfaces of the

pillars add up to 34% of the total array area, therefore 66% of the light is

assumed to be completely absorbed and 34% reflected as if it was on a

continuous surface of polished silicon. Figure 5.3A also includes a curve of

34% of the theoretical reflection of a flat surface. This curve is in reasonable

agreement with the simulation done for the 40 μm high pillars.

Chapter 5

96

Figure 5.3: (A) The simulation results of the reflection of pillars with different heights. The

results include the theoretical reflection of a flat silicon surface and when only 34% of the

light is reflected of a flat surface. (B): The theoretical photon absorbance of flat, pillar array

and coated pillar array.

With the reflection spectrum known, the optimal thickness of the AR coating

was calculated by considering a combination of three spectra as a function of

the wavelength, namely the photon flux[27]

the internal quantum efficiency

(IQE),[28]

and the reflectivity of the sample. By multiplying these spectra, the

theoretical photon absorbance of the silicon cell was obtained (Figure 5.3B).

The surface area underneath each curve in Figure 5.3B is directly reflected in

the current density output of a complete solar cell. Therefore, the photon

absorption capabilities of a flat surface are increased by adding an

anti-reflection coating to the surface, and are even more improved by applying

an AR coating to these pillars (see Figure 5.3B). The thickness of an AR

coating is such, that it has a minimum in reflection at the maximum photon flux

in the visible light region (~600 nm). To be specifically for the latter, the total

amount of photons can be maximized by adjusting the minimum in the

reflectivity curve. The minimum in the reflectivity is directly coupled to the

thickness of the AR coating and the refractive index of the used coating. The

optimized calculated thickness values in current densities are given in Table

5.1 for three anti-reflection coatings.

5.3.2. Anti-reflection coatings

Different AR coatings (Al2O3, SiO2, SiNx) were deposited on flat (p-type) and

pillared (p- and n-type) samples. Table 5.1 shows the ellipsometrically


97

measured optimal thicknesses of the experimentally deposited AR coatings on

both p- and n-type base pillar arrays with their corresponding doping.

Table 5.1: Simulated and measured optimal coating thicknesses of various AR

coating materials.

Material Optimal thickness

(nm)a

Thickness on

p-type (nm)b

Thickness on

n-type (nm)

Al2O3 91 87 86

SiNx 71 66 65

SiO2 106 110 106 a Theoretically calculated

b Measured by ellipsometry

To inspect the coating over the entire height of the pillar and thus to assess

the conformality of the AR coating layers, the coated pillars were cut in half

along the z-direction, by means of FIB etching. An overview of pillars coated

with Al2O3, SiO2, SiNx and ITO is given in Figure 5.4. Here, it is clearly visible

that the deposition of Al2O3 by ALD has resulted in a perfectly conformal

coating over the whole height of the pillar. In contrast, both LPCVD materials

(i.e. SiO2 and SiNx) exhibit a gradient in thickness along the height of the

micropillar. At the bottom, the layer is almost twice as thick as at the top.

Sputtering of ITO caused a problem in the scallops from the fabrication

process of the micropillars (DRIE; Bosch process, extra highlighted in

Figure 3). Due to the relatively high directionality of the material flux of physical

vapor deposition (i.e. sputtering) as compared to ALD or LPCVD. This resulted

in a non-conformal ITO thickness at the sidewalls of the pillars, at least at the

top where scallops, resulting from the fabrication, cause a shadowing effect in

the directional sputtering process. Further down the height of the pillar less

scalloping is visible and here the pillar is continuously coated. For all coatings,

the difference in conformality between the depositions of these materials is

attributed to the different deposition methods used, although some removal of

SiO2 and SiNx during FIB etching, which would lead to preferential removal

from the tops of the pillar because of the concomitantly higher exposure times

upon etching of the pillar, cannot be excluded.

Chapter 5

98

Figure 5.4: Cross-section HR-SEM images showing the layers of Al2O3, SiNx, SiO2 and

ITO along the sides of pillars that have been cut in half-orthogonal to the substrate to

inspect the conformality of the AR coatings across the entire pillar height. The HR-SEM

images are false colored manually in Photoshop to aid the visualization of the coatings.

The pillar on the right has been coated by ALD (Al2O3).

The indium doping level of is utmost importance for ITO, since it is a

conductive oxide because of the incorporation of indium atoms. One way to

check and visualize the doping level of the coating over the height of the pillar,

is by energy selective backscattered (ESB) SEM imaging. ESB is suitable for

visualizing both the contrast between the applied coating and pillar as well as

that between elements of which the layer is composed. From top to bottom,

the indium content in the coating is reduced, as the ESB image at positions

further down the pillar only shows some bright spots in the coating

(see Figure 5.4, ITO). At the bottom, almost no indium is present and hence

the coating is composed mostly of tin oxide. When indium is depleted from the

layer, it is assumed that ITO loses its conductive property.


99


To verify the positive effect of the deposited layers, JV measurements were

performed on flat surfaces and on both coated and non-coated silicon pillar

arrays with radial junctions. Prior to the measurements of the unmodified flat

and bare pillar arrays, the samples were dipped in 1% HF (1 min) to ensure

removal of the native oxide.

Measurements on different thicknesses for pillared p/n junctions were only

performed on p-type silicon (n-emitter). To verify whether the estimated

optimal thickness (as shown in the simulations described above) was correct,

JV measurements were performed, and the current density output compared

(Figure 5.5). This was done for Al2O3, SiO2 and SiNx, and showed optimal

thicknesses of 90, 110 and 71 nm respectively, well in agreement with the

simulated optimal values (91, 106, 71 nm, respectively).

Figure 5.5: The current density output as a function of the thickness of the anti-reflection

coating for p-base samples for Al2O3, SiO2 and SiNx, doped at 1050 °C for 15 minutes.

The transparent layers indicate the 1σ error range.

All coated samples (Figure 5.6) show an improvement in current density

compared to the bare pillar arrays, indicating that the layers are indeed

functioning as passivation and/or AR coating, except for the ITO sample on

n-type silicon. For the p-type base samples (n-emitter, Figure 5.6A), all

Chapter 5

100

samples show an improvement over the bare pillared samples, where SiO2

and SiNx show a larger improvement than Al2O3 in terms of JSC (Table 5.2).

We contribute these improvements to a combination of effects. Firstly, all

coatings have a refractive index different from silicon, and therefore each

material will act as an anti-reflection coating. Secondly, all applied coatings

passivate the silicon surface by reducing the amount of surface trap states by

chemical passivation (i.e. reducing the amount of dangling silicon bonds,

which is proportional to the total surface area of the micropillar array). Thirdly,

from literature it is known that SiO2 and SiNx introduce a positively charged

interface,[16]

due to which the minority carriers (holes) in the n-emitter are

electrically shielded from the surface and thus from the trap states (i.e. field

effect passivation).[29]

In contrast, Al2O3 induces a negatively charged

interface,[16]

due to which the minority carriers (holes) are attracted towards the

surface and thus into the possible trap states. This effectively increases the

minority carrier concentration at the c-Si interface, which limits the

improvements of Jsc upon use of Al2O3. The reason for the large increase of

VOC for the Al2O3 sample is unknown, however, we speculate that the chemical

passivation of the ALD technique is more effective than that of the LPCVD

methods. In terms of efficiency, all coatings lead to a significant increase

compared to bare arrays, up to 13.4% for Al2O3, compared to the 6.1 % of the

bare pillars (see Table 5.2).

In case of the n-type base samples (p-emitter, Figure 5.6B), an opposite effect

is observed. The increase in JSC is the highest for Al2O3, compared to the SiO2

and SiNx layers, which is expected based on the negatively charged Al2O3

interface with c-Si, whereas ITO performs slightly worse than the flat sample.

The adverse effect of the positively charged interface upon coating with SiO2

or SiNx has the most impact on samples with SiO2 as passivation coating,

since it is known that for SiNx field effect passivation, in this case negative, can

be reduced by annealing which gives a reduction of the charge density of the

overall positively charged interface.[30]

SiNx can be deposited by

plasma-enhanced chemical vapor deposition (PECVD) (at ca 400 °C) which is


101

followed by an annealing step at 700 °C. However, LPCVD SiNx is deposited

at 825 °C and the annealing step is done at the same time. Similar to the

p-type base samples, Al2O3, SiO2 and SiNx result in an increase in the overall

efficiency compared to bare micropillars (up to 10.1% for Al2O3). The ITO layer

shows an increase in current density, but the VOC and FF are lower, resulting

in a similar efficiency as its bare pillared counterpart.

Figure 5.6: JV measurements on p- (A) and n-type (B) base micropillars with radial p/n

junctions, with and without coating materials.

Table 5.2: JV characteristics for various coatings on both p- and n-type base specimens

with 40 µm silicon micropillars arrays.

Sample η

(%)

JSC

(mA/cm2)

VOC

(V)

FF

(%)

P-base bare 6.1±1.3 29.9±3.0 0.41±0.01 54±0.07

P-base Al2O3 13.4±1.0 33.6±2.7 0.47±0.01 73±0.01

P-base SiNx 10.4±1.4 39.4±3.4 0.42±0.02 62±0.08

P-base SiO2 10.2±1.2 40.9±1.5 0.44±0.02 57±0.04

N-base bare 7.5±0.8 23.5±2.4 0.45±0.01 68±0.02

N-base ITO 7.4±1.0 27.0±2.2 0.43±0.01 63±0.03

N-base Al2O3 10.1±0.7 33.8±0.8 0.46±0.01 70±0.05

N-base SiNx 9.5±0.9 28.9±2.9 0.45±0.01 72±0.02

N-base SiO2 8.3±0.8 25.1±2.0 0.46±0.01 72±0.03

To prove that the increase in efficiency upon applying a coating is not due to

differences between wafers, bare p-type base samples, which were first

electrically analyzed, were passivated with an Al2O3 coating. JV

measurements were recorded again after coating, and indeed revealed a clear

increase in the overall efficiency (Figure 5.7).

Chapter 5

102

Figure 5.7: JV measurements on a bare pillared sample (black line) and after ALD

deposition of 40 nm Al2O3 on this specimen (dashed line).

Such JV-measurements before and after application of a coating were not

possible for the LPCVD materials, since the required temperature for LPCVD

processes (well above 400 °C) causes severe roughening of the aluminum

contact, which results in short-circuiting and hence destroys the junction.[31]

When comparing p- and n-type base specimen, p-type base samples gave a

higher current density for identical coatings, whereas for n-type wafers the VOC

and FF were higher. The increase in JSC for coated p-type base samples is

higher than for coated n-type base samples, for which reason the p-type

specimen gave a higher overall efficiency. The large differences between the

recorded VOC and JSC between the two different base wafers for identical

applied coatings is hard to explain, although this is probably caused by

experimental parameters, such as different doping techniques (LPCVD vs.

SSD), base concentrations (1-10 (p-type) vs 5-10 Ω cm (n-type)) and doping

profiles (Figure 5.8).


103

Figure 5.8: JV measurements on A) p- and B) n-type base micropillars with radial p/n

junctions, with and without coating materials.

Both LPCVD materials SiO2 and SiNx show a non-uniform coating on the

sidewalls of the pillars (see Figure 5.4). At the topside of the pillars, the exact

thickness and high uniformity of the AR-coating are crucial in order to obtain

perfect AR behavior (which is accomplished in this work, see 5.3.2). However,

for the sidewalls these aspects – i.e. coating thickness and uniformity – are of

lesser importance, since, as we mentioned above, light entering the space in

between pillars will, after several scattering events, finally be absorbed by the

pillars. At the sidewalls of the pillars, the contribution of the coating therefore

mostly will be passivation. For this, a thickness of a few nanometers is

sufficient, without stringent uniformity requirements. In fact, the explored

LPCVD coatings fulfill the specifications to act as AR coating on the topside of

the pillars and as passivation layer at the sidewalls, which is clear when taken

the following arguments into account. The reflection is reduced by the pillar

arrays and 34% of the light is reflected „normally‟ (see section 5.3.1). If the

coating only functioned as anti-reflection coating, the overall efficiency could

only be 8.2% and 10.1% for p- and n-type base, respectively. From Table 5.2 it

becomes clear, that the overall efficiency gain is more. This implies indirectly

that the coating also functioned as a passivation layer. ALD materials are

Chapter 5

104

formed by self-limiting deposition cycles, which is evidenced in perfect

conformality on the topside and sidewalls of the pillar array. Therefore, ALD is

a good way to both passivate and create an AR-coating on high aspect ratio

micropillars, which follows from the electrical characterization (see Table 5.2).

Al2O3, SiO2 and SiNx have a double function (two-fold coating), but a three-fold

function of a coating is also an option, i.e. conductive oxides. Unfortunately,

the composition of ITO is not constant over the pillar height (see section 3.2).

Both effects counteract the theoretical efficiency improvement of the

ITO-coating, and as a result, the performance of ITO-coated solar cells is only

improved marginally with respect to bare pillar arrays. ITO as a passivation

and AR-coating is not successful; series resistances were not lowered and the

JSC output was only increased slightly, whereas the VOC even decreased.

5.4. Conclusions

In this work, the deposition and functionality of different anti-reflective and

passivation coatings was investigated. Using simulations, the optimal

thickness for these materials were predicted and empirically tested on flat

silicon solar cells. Four different layers were then grown on radial p/n junctions

(both p- and n-type base) using different techniques (ALD of Al2O3, LPCVD of

SiO2 and SiNx, and sputtering of ITO) and analyzed and characterized by

HR-SEM imaging and JV-measurements. The ALD deposition was conformal

over the height of the pillar, whereas for the LPCVD and sputtering deposition,

gradients were visible. For LPCVD the layer at the top of pillar was thinner

than the bottom side, whereas the sputtering technique was not able to fill the

scalloping (caused by DRIE, Bosch process). For ITO it was visible that less

indium was present further down the pillar, meaning it probably lost its

conductive property. JV measurements showed that Al2O3 improved the

overall efficiency the most (6.1 to 13.4% for p-type and 7.4 to 10.1% for

n-type), whereas ITO was the only coating to show a (small) decrease,

compared to flat samples. This is probably due to the lack of indium atoms,

caused by the sputtering of ITO of high aspect ratio structures. It can be


105

concluded that atomic layer deposition is most suitable for the growth of these

anti-reflective and passivation layers on high aspect ratio structures.

Acknowledgements

Wouter Vijselaar is greatly acknowledged for his ideas, discussions and ALD,

LPCVD and JV experiments in this chapter. Roald Tiggelaar is thanked for

corrections and discussions on this chapter. Henk van Wolferen is

acknowledged for the FIB experiments. Mark Smithers is thanked for the

HR-SEM images.

Chapter 5

106

5.5. References

[1] J. Zhao, A. Wang, P. P. Altermatt, S. R. Wenham, M. A. Green, Sol. Energy Mater. Sol. Cells, 1996, 41–42, 87-99.

[2] A. Shah, P. Torres, R. Tscharner, N. Wyrsch, H. Keppner, Science, 1999, 285, 692-698. [3] T. Saga, NPG Asia Mater, 2010, 2, 96-102. [4] E. Garnett, P. Yang, Nano Lett., 2010, 10, 1082-1087. [5] K. Q. Peng, S. T. Lee, Adv. Mater., 2011, 23, 198-215. [6] A. I. Hochbaum, P. Yang, Chem. Rev., 2010, 110, 527-546. [7] S. Y. Reece, J. A. Hamel, K. Sung, T. D. Jarvi, A. J. Esswein, J. J. H. Pijpers, D. G.

Nocera, Science, 2011, 334, 645-648. [8] E. L. Warren, H. A. Atwater, N. S. Lewis, The Journal of Physical Chemistry C, 2013,

118, 747-759. [9] K. S. Joya, Y. F. Joya, K. Ocakoglu, R. Van De Krol, Angew. Chem. Int. Ed., 2013, 52,

10426-10437. [10] B. M. Kayes, H. A. Atwater, N. S. Lewis, J. Appl. Phys., 2005, 97, 114302. [11] L. Tsakalakos, J. Balch, J. Fronheiser, B. A. Korevaar, O. Sulima, J. Rand, Appl. Phys.

Lett., 2007, 91, 233117. [12] Z. Yu, H. Gao, W. Wu, H. Ge, S. Y. Chou, J. Vac. Sci. Technol. B, 2003, 21, 2874-2877. [13] H. Xu, N. Lu, D. Qi, J. Hao, L. Gao, B. Zhang, L. Chi, Small, 2008, 4, 1972-1975. [14] G. Dingemans, N. M. Terlinden, D. Pierreux, H. B. Profijt, M. C. M. van de Sanden, W.

M. M. Kessels, Electrochem. Solid-State Lett., 2011, 14, H1-H4. [15] B. Hoex, J. J. H. Gielis, M. C. M. van de Sanden, W. M. M. Kessels, J. Appl. Phys.,

2008, 104, 113703. [16] R. B. M. Girisch, R. P. Mertens, R. F. De Keersmaecker, Electron Devices, IEEE

Transactions on, 1988, 35, 203-222. [17] A. G. Aberle, S. Glunz, W. Warta, Sol. Energy Mater. Sol. Cells, 1993, 29, 175-182. [18] J. Schmidt, EU PVSEC Proceedings, 2012, DOI: 10.4229/25thEUPVSEC2010-2AO.1.6,

1130 - 1133. [19] D. R. Kim, C. H. Lee, P. M. Rao, I. S. Cho, X. Zheng, Nano Lett., 2011, 11, 2704-2708. [20] A. D. Mallorquí, E. Alarcón-Lladó, I. C. Mundet, A. Kiani, B. Demaurex, S. De Wolf, A.

Menzel, M. Zacharias, A. Fontcuberta i Morral, Nano Res., 2015, 8, 673-681. [21] M. Faustini, L. Nicole, C. Boissière, P. Innocenzi, C. Sanchez, D. Grosso, Chem. Mater.,

2010, 22, 4406-4413. [22] A. Szeghalmi, M. Helgert, R. Brunner, F. Heyroth, U. Gösele, M. Knezl, Appl. Opt.,

2009, 48, 1727-1732. [23] G. Dingemans, R. Seguin, P. Engelhart, M. C. M. van de Sanden, W. M. M. Kessels,

Phys. Status Solidi RRL, 2010, 4, 10-12. [24] F. Duerinckx, J. Szlufcik, Sol. Energy Mater. Sol. Cells, 2002, 72, 231-246. [25] H. MäcKel, R. Lüdemann, J. Appl. Phys., 2002, 92, 2602-2609. [26] R. Elbersen, R. M. Tiggelaar, A. Milbrat, G. Mul, H. Gardeniers, J. Huskens, Adv.

Energy Mater., 2015, 5, 1401745. [27] R. Hulstrom, R. Bird, C. Riordan, Solar Cells, 1985, 15, 365-391. [28] S. C. Baker-Finch, K. R. McIntosh, Photovoltaic Specialists Conference (PVSC), 2010

35th IEEE, 2010. [29] G. Dingemans, Ph.D. thesis, Technical University Eindhoven, 2011. [30] F. Duerinckx, J. Szlufcik, Sol. Energy Mater. Sol. Cells, 2002, 72, 231-246. [31] J. Bullock, D. Yan, Y. Wan, A. Cuevas, B. Demaurex, A. Hessler-Wyser, S. De Wolf, J.

Appl. Phys., 2014, 115, 163703.

This chapter has been adapted from: A. Milbrat, R. Elbersen, R. Kas, R.M.

Tiggelaar, J.G.E. Gardeniers, J. Huskens, G. Mul, “Spatioselective

Electrochemical and Photoelectrochemical Functionalization of Silicon

Microwires with Axial p/n Junctions”, Adv. Mater., 2015, accepted 107

Chapter 6

Spatioselective Electrochemical and

Photoelectrochemical Functionalization

of Silicon Microwires with Axial p/n

Junctions

A powerful method is presented to functionalize selectively the top and bottom

of semiconductor wires with axial junctions. A light switch is used to address

individual segments electrochemically for modification. The principle is

demonstrated by deposition of platinum on the bottom p type and silver on the

top n+ type of silicon microwires with an axial junction. Between the dual

functionalizations, an unmodified band is observed which is related to the

depletion layer of the p/n interface.

Chapter 6

108

6.1. Introduction

Semiconductor wires and wire arrays of nano- to micrometer size have unique

optical, electronic, electrochemical, thermal, mechanical and magnetic

properties.[1]

Therefore, they are one of the most considered

structures for electronic, sensor, photonic, thermoelectric, photovoltaic,

photoelectrochemical and battery applications.[1-5]

Semiconductor wires often

require functionalization, for example, by deposition of catalysts,[6]

additional

semiconductors,[7]

grafting with organic molecules[8]

or polymers,[9]

in order to

tailor their properties for the targeted application. However, these modifications

are commonly performed across the entire surface of the wires. Janus-type

wires on the other hand, of which the top and bottom segments have different

functionalizations, could provide access to new types of devices or improve

the functionality of existing ones.[10]

Many applications, such as sensors,[11]

tunnel field-effect transistors,[12-15]

light-emitting diodes,[16,17]

photovoltaics[18-20]

and photonics,[16,21]

require or would benefit from an axial homo- or

heterojunction and electrical communication between the segments.

The feasibility of creating bi-functionalized semiconductor wires and wire

arrays has been reported previously in literature for their use in

photocatalysis,[22-24]

microfluidics[25,26]

or as super hydrophobic surfaces.[27]

However, the field of Janus wires is not yet extensively explored, mainly

because their preparation is complex and requires several steps. So far,

bi-functionalized wires have been created by physically masking the part of the

wire that was to remain unmodified. Typically, wires were embedded

completely in a polymeric material first, which was subsequently etched back

to expose parts of the wires for further functionalization. This masking process

makes it difficult to control the functionalization boundary precisely,

reproducibly, and homogeneously across an array, which is particularly

important for, for example, axially heterostructured wires where a small

misalignment could lead to a failure of the device.

Spatioselective Functionalization of Silicon Microwires with Axial p/n Junctions

109

Herein, we show a method for the direct and spatioselective

bi-functionalization of semiconductor microwires, which employs the different

electronic properties of an axial junction in dark and under illumination.

Exemplary, we have used silicon microwires with an axial n+/p junction.

Figure 6.1 schematically shows the concept. It starts from a silicon microwire

that has an axial n+/p junction, prepared by the n-doping of a flat p-base wafer

followed by dry etching to create the microwires. We anticipated that the

junction would induce diode-like behavior when a negative potential is applied

to the p-region, preventing electrons to pass from bottom to top. This would

allow the selective functionalization of the bottom segment by reductive

electrodeposition. The feasibility of this hypothesis is tested here by the

electrodeposition of Pt nanoparticles from a hexachloroplatinic acid precursor

solution (Figure 6.1a). Under illumination, the junction induces electrons to

migrate to the n+-Si surface and allow its selective functionalization, which will

be demonstrated here by the electrodeposition of silver (Figure 6.1b and 6.1c).

The holes accumulated in the p-Si part recombine with electrons supplied by

an external source, i.e. by applying a negative bias to the base silicon, or

oxidize p-Si surface. Performing both steps consecutively results in dually and

spatioselectively functionalized arrays of microwires. Platinum and silver were

chosen for a proof of concept, because these metals form Ohmic contacts to

the p-type and n+-type silicon, respectively. As Figure 6.1 indicates, we

observed an unmodified band between the functionalized segments in the final

wires. We provide here analytical data and theory, as well as a preliminary

explanation for this phenomenon.

Chapter 6

110

Figure 6.1: Schematic illustration of the spatioselective functionalization process of silicon

microwires with an axial n+/p junction: an initial silicon microwire (left) is functionalized by

the electrochemical deposition of Pt in the dark on the p Si part (a) and of Ag under

illumination on the n+-Si part (b, c). Sequential deposition of Pt and Ag leads to a bi-

functionalized silicon microwire (right) in which a depletion zone is visible between the

functionalized areas. Step (d) provides an optional, but here unexplored, route.


6.2.1. Fabrication of axial p/n junctions in silicon micropillar arrays

The fabrication process for the axial p/n junction is schematically shown in

Figure 6.2. Boron doped, p-type silicon substrates ((100) oriented, resistivity

5-10 Ω cm, 100 mm diameter, 525 μm thickness, single side polished, Okmetic

Finland) were cleaned by immersion in 100% nitric acid (HNO3) (2x 5 min) and

in fuming 69% nitric acid (15 min), followed by quick dump rinsing in

de-mineralized (DI) water, immersion in 1% aqueous hydrofluoric (HF) acid to

remove the formed oxide shell and another quick dump rinsing cycle. After

spin drying the wafers, 100 nm thick silicon-rich silicon nitride (SiRN) was


111

deposited using low-pressure chemical vapor deposition (LPCVD) on both

sides of the wafer, removed from the front side with reactive ion etching

(Adixen AMS100DE; octafluorocyclobutane (C4F8) and methane (CH4)),

followed by an oxygen plasma treatment and piranha cleaning (mixture of

concentrated sulfuric acid and 30% aqueous hydrogen peroxide, 3:1 (v/v),

20 min) to remove any contamination (i.e. fluorocarbon traces from the

DRIE-process). Subsequently, the front side was covered by a phosphorus

spin-on-glass (P-SOG, Filmtronics P509), spun at 6000 rpm for 30 s, and

annealed at 1100 °C for 60 min. The remaining P-SOG and SiRN layers were

removed by immersion in buffered hydrogen fluoride (1:7, BHF) for 10 min,

washed with DI water and dried with a nitrogen flow. By means of standard

UV-lithography, six 2 x 2 cm2 areas with an array of microwires (specifications:

diameter 4 μm, spacing 2 μm, hexagonally stacked with a packing density of

35%) were defined in photoresist (Olin 907-17), and post-baked for 10 min at

120 °C after exposure and development. The photoresist acted as a mask

layer during cryogenic (-100 °C) deep reactive ion etching (DRIE; Adixen

AMS100SE, 1000 W) of silicon, using sulfur hexafluoride (SF6, 200 sccm) for

etching silicon and O2 (30 sccm) for passivating the sidewalls. The height of

the wires was determined by the etch duration, which was set to 2 min,

resulting in wire heights of approximately 7 μm. After etching, the photoresist

mask was stripped off with oxygen plasma, followed by piranha cleaning

(20 min), rinsing with DI water and drying with nitrogen. Prior to selective

electrodeposition experiments, the sample was immersed in 1% aqueous

hydrofluoric (HF) acid solution for at least 1 min to remove the silicon oxide

shell, washed by quick dump rinsing in de-mineralized (DI) water, spin dried

and the backside sputter-coated with an 1 μm thick aluminum/silicon alloy

(99% Al, 1% Si) (Oxford PL 400, 7000 W) to create a low resistance Ohmic

contact.

Chapter 6

112

Figure 6.2: Schematic illustration of the synthesis of silicon microwires with axial n+/p

junctions. a) Low-pressure chemical vapor deposition (LPCVD) of silicon-rich silicon nitride

(SiRN) on p type silicon substrates. b) Removal of SiRN from the front side by reactive ion

etching (RIE). c) Spin coating of phosphorus spin on glass (P-SOG) at 6000 rpm for 30 s.

d.) Thermal phosphorus drive in at 1100 °C for 60 min. e) Definition of microwire arrays by

standard UV lithography. f) Cryogenic (-100 °C) deep reactive ion etching (DRIE). g)

Removal of photoresist and silicon oxide and sputtering of aluminum/silicon alloy (99% Al,

1% Si).

6.2.2. Electrodeposition of platinum and silver

Prior to the electrodeposition experiments, specimens were immersed in

1% aqueous hydrofluoric acid (HF) solution to remove the native oxide,

followed by creation of a 1 μm thick aluminum/silicon alloy (99% Al, 1% Si) by

sputtering on the backside, to function as a low-resistance Ohmic contact.

Broken out microwire arrays (2 x 2 cm2) were used full sized for Pt deposition

or further broken in 4 pieces (approximately 1 x 1 cm2) for Ag deposition.

Platinum was deposited on the bottom p-Si segments from an aqueous

solution of 5 mM hexachloroplatinic(IV) acid (H2PtCl6) and 0.5 M sodium

sulfate (Na2SO4), potentiostatically at -0.7 V. Charge densities of 130 mC/cm2

were supplied. Silver was deposited on the top n-Si segments from an

aqueous solution of 1 mM silver nitrate (AgNO3) and either 0.5 M Na2SO4,

0.005 M H2SO4 or 0.5 M H2SO4 as the electrolyte, with a pH of 5.3, 2.4 and

0.6, respectively. Voltages applied were -0.1 V, +0.1 V and +0.3 V. The

deposition was discontinued when the charge density amounted to

25 mC/cm2.


113

A solar simulator with a 300 W xenon lamp and an air mass 1.5 global filter

was used as a light source for experiments performed under illumination. The

intensity of the simulated sunlight was adjusted to 2 suns (200 mW/cm2) with a

standard reference silicon solar cell and partially cut off at 570 nm with a

cut-on filter (Newport) to avoid significant homogeneous photodecomposition

of AgNO3 in solution by shorter wavelengths. The custom-made Teflon-based

reactors with a volume of about 8 ml were equipped with an optical glass

window and were open to the environment. Active surface areas applied were

3.14 cm2 for platinum and 0.28 cm

2 for silver deposition, respectively, as

determined by the O-rings of the reactors. A standard three-electrode system

with a platinum mesh counter electrode was used. A potentiostat (PAR,

VersaStat 4) served as a power source. All applied potentials are reported

versus an Ag/AgCl (3 M NaCl, BASi MF-2052) reference electrode, and all

electrochemical experiments were performed at room temperature.

6.2.3. Scanning electron microscopy and energy-dispersive X-ray

spectroscopy

High-Resolution Scanning Electron Microscopy (HR-SEM) images were taken

with a Philips FEI XL30 FEG-ESEM equipped with a Secondary Electron (SE)

detector or a FEI Sirion FEG-SEM with a Through the Lens Detector (TLD),

operated at typical acceleration voltages of 10 kV.HR-SEM in combination with

Energy-Dispersive X-ray spectroscopy (EDX). EDX mapping was performed

with a MERLIN FEG HR-SEM with an inlens SE detector and an EDX

Spectrometer, 80 mm2 detector.


Figure 6.3a shows platinum particles, electrodeposited in the dark, selectively

on the p-type base and bottom segments of the axially doped silicon

microwires. Clearly, the top n+-type segments have remained unmodified. A

control experiment, performed at identical electrochemical conditions but

applied to p-Si microwires without phosphorus n+-Si top segments, yielded

completely covered microwires (Figure 6.3b).

Chapter 6

114

This confirms our concept of the blocking of the electron flow to the n+-Si top

parts in the dark by the diode present in the axially doped microwires. The

metal was deposited as particles and not as a continuous film, which is

consistent with the theory of Volmer–Weber island growth.[15]

In both samples

shown in Figure 6.3, the density of the particles is higher at the top of the

functionalized segment compared to the bottom of the microwires, which is

tentatively attributed to diffusion limitation of the precursor in between the

microwires at these densely packed arrays.

Figure 6.3: Cross-sectional SEM images of a) Si microwires with a n+/p junction and b)

p-Si microwires after the electrodeposition of Pt particles at 0.7 V and 130 mC/cm2 in the

dark from a solution of 5 mM H2PtCl6 and 0.5 M Na2SO4.

Figure 6.4 shows silver particles, electrodeposited selectively on the top n+-Si

segments under illumination (Figure 6.4a) and semi-selectively on the p-type

base and bottom segments in dark (Figure 6.4b) of the axially doped silicon

microwires. Selective photo-supported electrodeposition of silver on the top of

the wires at the n+-Si segments was achieved in 0.5 M H2SO4.

Electrodeposition of Ag in the dark yielded major deposition on the bottom p-Si

segments and minor deposition on the top n-Si segments (Figure 6.4b). We

assume that the formation of a Schottky junction between Ag and p-Si close to

the n+/p junction caused a “leak” of electrons through the n

+/p junction by a

partial overlap of both junction depletion layers. Thus, an Ohmic contact

between semiconductor wire segments and functionalized material is required

to achieve high selectivity in functionalization.


115

Figure 6.4: Cross-sectional SEM images of silicon microwires with an axial n+/p junction

after the electrodeposition of Ag particles at 25 mC/cm2 from a solution of 1 mM AgNO3

and 0.5 M H2SO4 at a) +0.3 V under illumination and b) 0.3 V in the dark.

To realize bi-functionalized silicon microwires, we first performed the

electrodeposition of platinum in the dark, followed by an immersion of the

sample into a 1% aqueous HF solution (30 s), and subsequently conducted

the photo-induced electrodeposition of silver. This order is necessary in our

case because otherwise Ag is galvanically replaced by Pt from the Pt

precursor solution. Figure 6.5 shows cross-sectional SEM images of such

bi-functionalized silicon microwires with an axial n+/p junction. The presence of

silver on the top parts and platinum on the bottom parts of the microwires

shown in Figure 6.5a, was confirmed by SEM/EDX mapping (Figure 6.5b). The

deposition boundary of silver is observed at 2.4 μm and that of platinum at

3.3 μm from the top of the microwire. In between the metal-covered areas, the

microwires exhibit an unmodified band with a width of approximately 0.9 μm.

In the following, these observations will be discussed in more detail.

Chapter 6

116

Figure 6.5: Cross-sectional SEM images (a,c) and SEM/EDX mapping (b) of silicon

microwires with an axial n+/p junction after the electrodeposition of Pt particles at -0.7 V

and 130 mC/cm2 in the dark from a solution of 5 mM H2PtCl6 and 0.5 M Na2SO4, followed

by the electrodeposition of Ag particles at 25 mC/cm2 under illumination from a solution of

1 mM AgNO3 in a,b) 5 mM H2SO4 electrolyte at -0.1 V and c) 0.5 M Na2SO4 electrolyte at

+0.3 V.

The mechanism of our concept of dual functionalization of axially doped

microwires and the occurrence of the unmodified band in between the metal-

covered areas can be explained using the theory of a p/n junction. Figure 6.6a

shows band edges of a p- and highly n-doped semiconductor (silicon in our

case) with its Fermi levels. Connecting the p- and n-type parts results in an

electron flow from filled states in the n-Si conduction band to empty states of


117

the p-Si valence band until the Fermi level of both silicon types equalize. A

depletion layer is thus formed, and this causes bending of the p-Si and n-Si

bands (Figure 6.6b). The depleted areas in n-Si and p-Si get positively and

negatively charged, respectively. Due to the higher doping level of n-Si, the

depletion layer penetrates mostly into p-Si.

Figure 6.6: Schematic illustration of n+/p-Si band diagrams a) before contact, b) in contact

at equilibrium, c) reverse-biased, d) under illumination.

The orientation of the diode in our concept is such that it is reverse-biased

when the base is put at a negative potential. Consequently, the potential

barrier in the junction prevents a significant amount of electrons to pass the

junction in the dark (Figure 6.6c). These electrons, supplied by an external

source, occupy the empty states in the p-Si valence band and thereby enlarge

the depletion layer into the bulk or migrate to the surface of the p-type

semiconductor, where they induce its selective functionalization, which is in

our case the electrodeposition of platinum. We assume that in this case only

electrons outside of the depletion layer are available for the reduction of Pt

precursor at the silicon surface.

Chapter 6

118

Upon illumination, photoexcited electrons drift across the junction from the p-Si

conduction band into the n+-Si conduction band while holes migrate from the

n+-Si valence band to the p-Si valence band due to the induced electric field.

This diminishes the width of the depletion layer and leads to an accumulation

of electrons in the n+-type part and of holes in the p-type material

(Figure 6.6d). These accumulated electrons on the n+-Si side are subsequently

used for the regioselective deposition of silver.

We hypothesize that the unmodified band occurs due to the depletion layer of

the n+/p junction. The depletion layer width (W) of an abrupt n

+/p junction

under equilibrium conditions is given by Equation 6.1 and 6.2:

√ ( )

(6.1)

𝜙

𝑙𝑛 (

) (6.2)

in which ε is the permittivity of the material (1.034×10-10

AsV-1

m-1

for Si), ND

and NA are the donor and acceptor densities (m-3

), ϕbi is the built-in potential

(V), q is the unit charge (1.602×10-19

C), kB is Boltzmann‟s constant

(1.3806×10−23

JK-1

), T is the absolute temperature (K) and ni is the intrinsic

carrier concentration (1.0×1016

m-3

at 300 K for silicon). The boron doping

level, NA, of the base wafer of the specimen was determined (1.4×1021

m-3

) by

measuring its sheet resistance. The calculated depletion layer width depends

only slightly on the heavily doped material. Based on secondary ion mass

spectroscopy (SIMS) (Figure 6.7) data of a phosphorus-doped specimen we

used ND doping levels in the range of 1022

m-3

to 1024

m-3

for calculations.

Consequently, the expected depletion layer width in equilibrium ranges from

0.83 μm to 0.84 μm, respectively. Any influences of the silicon/electrolyte

junction and changes of the depletion layer width upon an applied reverse bias

in the dark or under illumination are not considered, due to the unknown IR

drop caused by electron flow from p-Si to the solution in the dark and to n+-Si

under illumination. The values for the width of the depletion layer obtained by

this simplified model correspond well with experimental observations of the


119

width of the deposition-free zone, for which typically values of 0.9 μm

(Figure 6.5c) have been found.

Figure 6.7: Secondary Ion Mass Spectroscopy (SIMS) depth profile of phosphorus dopant

concentration in a boron doped silicon specimen with a concentration of

1.43×1021

atoms/m3. The junction position is determined by extrapolation of the linear

regime towards boron background doping concentration.

According to the theory given above, the depletion layer is expected to

penetrate mostly into the low-doped p-region, and therefore the junction

should be positioned close to the top of the metal-free zone of the wires. In

more quantitative detail, the estimated penetration depth of the depletion layer

into the n+-Si side (Wn) is in the range of 0.104 μm to 0.001 μm, while the

depths at the p-Si side (Wp) amount to 0.724 μm to 0.840 μm, using ND values

of 1022

m-3

and 1024

m-3

, respectively, calculated with Equation 6.3 and 6.4:

(6.3)

(6.4)

Based on the observed deposition of Ag at the top 2.4 μm of the wires

(Figure 6.5c), the junction is expected to be positioned at about the same

height from the top of the microwires. To locate the junction position

Chapter 6

120

experimentally, we performed SIMS measurements (Figure 6.7), ball grooving

and staining of the junction of a doped flat wafer in a CrO3/HF aqueous

solution (as explained in Chapter 3), and wet etching by the same staining

solution of a microwire sample with an axial junction (Figure 6.8). The results

are different: SIMS, ball grooving in combination with staining, and a diffusion

model for predicting the doping profile at the drive-in settings used here,[28]

indicate the junction to be located at approximately 3.6 μm from the top. In

contrast, the doped microwires show a transition at 2.2 μm from the top

(Figure 6.8). In the latter case, however, a transition becomes visible due to a

higher etching rate of n+-Si compared to p-Si. Consequently, a small fraction is

etched from the microwire top, suggesting the transition being close to the Ag

boundary at 2.4 μm from microwire tops. However, this may not necessarily

prove exact correspondence with the position of the junction.

Figure 6.8: Cross-sectional SEM image of silicon microwires with an axial n+/p junction

stained in a CrO3/HF aqueous solution for 2 min.

The boundary of silver deposition in the dark was observed at the same

location as for deposition under illumination, i.e. at 2.4 μm from the microwire

top (Figure 6.4). The absence of the unmodified band is in this case is


121

not clear. We speculate that it might be either due to electronic effects in the

microwires or electrostatic attraction or repulsion of precursor metal ions. The

formation of a Schottky contact between Ag and p-Si, of which the depletion

layer partially overlaps with the n+/p junction, may reduce the n

+/p junction

depletion layer width at the microwires surface, thereby allowing Ag deposition

up to the junction in the dark. Furthermore, silver deposition on the depletion

layer of the n+/p junction may be caused by the attraction of the positively

charged Ag+ ions in solution to the negatively charged depleted layer in p-Si

(Figure 6.6b). In contrast, platinum ions are present as negatively charged

[PtCl6]2-

complexes[29]

and would be repelled by the depleted layer in p-Si.

6.4. Conclusions

In conclusion, we have developed a new method to functionalize

semiconductor wires with an axial junction spatioselectively by utilizing its

differences in electronic nature in the dark and under illumination. We have

demonstrated separate functionalization of the n+- and p-type segments of

silicon microwires, as well as the combined dual functionalization, with

electrochemically deposited platinum particles and photoelectrochemically

deposited silver particles, respectively. More investigation is needed to

understand the observed unmodified band between deposited particles of Pt in

the dark and Ag under illumination, its absence in the deposition of Ag in the

dark and under illumination, as well as to clarify its origin. However, the finding

of this phenomenon may help to improve fundamental understanding of

interfaces between semiconductors, metals and electrolytes.

The proposed concept is highly selective, relatively simple and can be

potentially also applied to wires or wire arrays with semiconductor-

semiconductor axial diode heterojunctions or metal-semiconductor Schottky

junctions. Besides reductive electrodeposition of metals, any other reductive or

electron-induced reaction, such as electrochemical grafting with organic

molecules is potentially possible. Also, oxidative or electron-poor surface

reactions are conceivable if an inverted junction is constructed and care is

taken to prevent semiconductor surface oxidation.

Chapter 6

122

Thus, we believe that our method has great potential to improve the ability of

creating micro-sized structures with complex compositions and engineer

multifunctional devices and systems with new functions.

Acknowledgements

Alexander Milbrat is greatly acknowledged for the ideas, discussions, figures

and electrochemical measurements in this chapter. Roald Tiggelaar and

Recep Kas are acknowledged for the discussions. Mark Smithers is thanked

for the HR-SEM and EDX imaging.


123

6.5. References

[1] N. P. Dasgupta, J. Sun, C. Liu, S. Brittman, S. C. Andrews, J. Lim, H. Gao, R. Yan, P. Yang, Adv. Mater., 2014, 26, 2137-2184.

[2] E. L. Warren, H. A. Atwater, N. S. Lewis, J. Phys. Chem. C, 2013, 118, 747-759. [3] F. Patolsky, C. M. Lieber, Mater. Today, 2005, 8, 20-28. [4] A. I. Hochbaum, P. Yang, Chem. Rev., 2010, 110, 527-546. [5] Y. Cui, Q. Wei, H. Park, C. M. Lieber, Science, 2001, 293, 1289-1292. [6] Y. M. A. Yamada, Y. Yuyama, T. Sato, S. Fujikawa, Y. Uozumi, Angew. Chem., Int. Ed.,

2014, 53, 127-131. [7] M. R. Shaner, K. T. Fountaine, S. Ardo, R. H. Coridan, H. A. Atwater, N. S. Lewis,

Energy Environ. Sci., 2014, 7, 779-790. [8] M. Y. Bashouti, K. Sardashti, S. W. Schmitt, M. Pietsch, J. Ristein, H. Haick, S. H.

Christiansen, Prog. Surf. Sci., 2013, 88, 39-60. [9] N. Gao, W. Zhou, X. Jiang, G. Hong, T.-M. Fu, C. M. Lieber, Nano Lett., 2015, 15, 2143-

2148. [10] A. Walther, A. H. E. Müller, Chem. Rev., 2013, 113, 5194-5261. [11] Z. Jiang, Q. Qing, P. Xie, R. Gao, C. M. Lieber, Nano Lett., 2012, 12, 1711-1716. [12] A. M. Ionescu, H. Riel, Nature, 2011, 479, 329-337. [13] C.-Y. Wen, M. C. Reuter, J. Bruley, J. Tersoff, S. Kodambaka, E. A. Stach, F. M. Ross,

Science, 2009, 326, 1247-1250. [14] A. L. Vallett, S. Minassian, P. Kaszuba, S. Datta, J. M. Redwing, T. S. Mayer, Nano

Lett., 2010, 10, 4813-4818. [15] L. Guo, G. Oskam, A. Radisic, P. M. Hoffmann, P. C. Searson, J. Phys. D: Appl. Phys.,

2011, 44, 443001. [16] M. Hocevar, G. Immink, M. Verheijen, N. Akopian, V. Zwiller, L. Kouwenhoven, E.

Bakkers, Nat. Commun., 2012, 3, 1266. [17] J. Motohisa, Y. Kohashi, S. Maeda, Nano Lett., 2014, 14, 3653-3660. [18] B. Tian, T. J. Kempa, C. M. Lieber, Chem. Soc. Rev., 2009, 38, 16-24. [19] M. Yao, N. Huang, S. Cong, C.-Y. Chi, M. A. Seyedi, Y.-T. Lin, Y. Cao, M. L. Povinelli,

P. D. Dapkus, C. Zhou, Nano Lett., 2014, 14, 3293-3303. [20] J. D. Christesen, X. Zhang, C. W. Pinion, T. A. Celano, C. J. Flynn, J. F. Cahoon, Nano

Lett., 2012, 12, 6024-6029. [21] M. S. Gudiksen, L. J. Lauhon, J. Wang, D. C. Smith, C. M. Lieber, Nature, 2002, 415,

617-620. [22] C. Liu, J. Tang, H. M. Chen, B. Liu, P. Yang, Nano Lett., 2013, 13, 2989-2992. [23] S. W. Boettcher, E. L. Warren, M. C. Putnam, E. A. Santori, D. Turner-Evans, M. D.

Kelzenberg, M. G. Walter, J. R. McKone, B. S. Brunschwig, H. A. Atwater, N. S. Lewis, J. Am. Chem. Soc., 2011, 133, 1216-1219.

[24] Y. Qu, L. Liao, R. Cheng, Y. Wang, Y.-C. Lin, Y. Huang, X. Duan, Nano Lett., 2010, 10, 1941-1949.

[25] T. Wang, H. Chen, K. Liu, S. Wang, P. Xue, Y. Yu, P. Ge, J. Zhang, B. Yang, ACS Appl. Mater. Interfaces, 2015, 7, 376-382.

[26] T. Wang, H. Chen, K. Liu, Y. Li, P. Xue, Y. Yu, S. Wang, J. Zhang, E. Kumacheva, B. Yang, Nanoscale, 2014, 6, 3846-3853.

[27] L. Mammen, K. Bley, P. Papadopoulos, F. Schellenberger, N. Encinas, H.-J. Butt, C. K. Weiss, D. Vollmer, Soft Matter, 2015, 11, 506-515.

[28] M. Uematsu, J. Appl. Phys., 1997, 82, 2228-2246. [29] C. R. K. Rao, D. C. Trivedi, Coord. Chem. Rev., 2005, 249, 613-631. [30] Y. L. Kawamura, T. Sakka, Y. H. Ogata, J. Electrochem. Soc., 2005, 152, C701-C705.

124

125

Summary and Outlook

Silicon is a widely used material in the photovoltaic industry, and its

advantageous properties and availability ensure that it can play an important

role in the transition to a sustainable production of energy. Apart from already

commercially available PV cells, silicon can also take part in new alternatives,

such as solar-to-fuel (S2F) devices. However, before silicon can be used in

such a device, it has to be altered to withstand different conditions, for

example a water environment in case of a water splitting S2F device.

Moreover, the structuring of silicon, e.g. into micropillar arrays, provides ways

to enhance the performance of both PV and S2F devices. This thesis

discusses the use of silicon as a base material for the structuring of solar cells,

and their optimization and modification.

Chapter 3 has reported the fabrication and doping of silicon micropillars,

followed by an electrical characterization. The micropillars were made by

means of standard photolithography and deep reactive ion etching, with a

diameter of 4 µm. The radial p/n junctions were formed by different methods,

such as low-pressure chemical vapor deposition of phosphorus and solid

source dotation of boron. It was verified that the junction was formed

homogeneously over the full height of the pillar as made visible by focused ion

beam cutting, staining, and SEM imaging. In both phosphorus and

boron-doped samples, the pillared solar cells showed an improvement in

efficiency, compared to flat solar cells.

The micropillars were further optimized, as described in Chapter 4, where the

height and junction depth were varied to determine their optimal values. The

height of the pillars was varied between 0 and 60 µm, and showed the highest

solar cell efficiency for a height of 40 µm. The efficiency of higher pillars was

lower, probably due to the fact that etching of the silicon introduced more

defect surface states, leading to more recombination. The optimum for the

junction depth was found to be 790 nm. Samples with smaller depths were not

functional, as the diode behavior showed leakage. For junction depths

Summary and Outlook

126

>790 nm, the efficiency dropped, which was explained by the narrowing of the

undoped inner part of the pillars by the depletion zone.

Chapter 5 has discussed the further optimization of silicon pillar devices, by

means of a passivation and anti-reflective coating. The defects introduced in

the silicon by deep reactive ion etching could be eliminated by applying a thin

layer of either Al2O3 (by atomic layer deposition), SiNx or SiO2 (both by

low-pressure chemical vapor deposition). By tuning the thickness of this layer,

the layer also acted as an anti-reflective coating, which increased the current

density of all samples. The 3D and conformal deposition of these layers was

also investigated by focused ion beam and SEM imaging. For both p- and

n-type doped samples, atomic layer deposition of Al2O3 gave the highest

increase in solar cell efficiency.

Finally, in Chapter 6, a method for the functionalization of silicon micropillars

was discussed. For that purpose, axial p/n junctions were fabricated by

spin-on-dopant diffusion, followed by the cryogenic etching of silicon, which

minimized sidewall damaging. By using the axial nature of the junction, the

bottom and top parts were functionalized selectivity with platinum (in the dark)

and silver (under illumination), respectively. The metals were deposited by

electrodeposition, without the use of a masking step. A non-functionalized

zone between the n- and p-type parts was observed, and calculations

suggested that this matches the depletion zone.

To conclude, silicon micropillars with radial p/n junctions were fabricated and

optimized using various techniques. These structures might also be applied in

silicon-based S2F devices, to enhance the light absorption, ultimately

increasing the overall efficiency of such a device. The jointly passivating and

anti-reflective coating could even function as a chemically protective layer, to

increase the stability of silicon in an aqueous environment. In addition, it was

shown that (axially doped) silicon pillars could be functionalized with different

materials, by using the p/n junction and its electrical performance in dark and

under illumination to direct the flow of electrons. This approach could be useful

to drive reactions that require different catalysts on the same pillar.

127

Samenvatting en Visie

Silicium is een veelgebruikt materiaal in de zonnecelindustrie en, vanwege de

uitstekende eigenschappen en grote beschikbaarheid, zal het een belangrijke

rol kunnen spelen bij de transitie naar een duurzame energiewinning. Behalve

voor zonnecellen kan het ook belangrijk zijn voor nieuwe alternatieven, zoals

een zonlicht-tot-brandstof (S2F-)apparaat. Voordat silicium daarvoor gebruikt

kan worden, moet het eerst gemodificeerd worden zodat het onder

verschillende condities kan functioneren, zoals in een waterige oplossing die

nodig is bij watersplitsing. Bovendien kan het structureren van silicium een

grote bijdrage leveren aan de prestaties van apparaten die zonne-energie

omzetten. In dit proefschrift wordt het gebruik van silicium als basismateriaal

voor het structureren van zonnecellen beschreven, alsmede de optimalisatie

en modificatie van deze materialen.

In Hoofdstuk 3 is de fabricage en dotering van silicium micropilaren

beschreven, gevolgd door een elektrische karakterisatie. De micropilaren zijn

gemaakt met behulp van standaard-fotolithografie en droog-etsen (DRIE), en

hebben een diameter van 4 µm. De radiale junctie is gevormd door middel van

verschillende doteringstechnieken, zoals de depositie van fosfor bij lage druk

(LPCVD) en de dotering van boor vanuit een vaste bron (SSD). Het is

aangetoond dat de radiale junctie homogeen door de pilaren gevormd was

door een dwarsdoorsnede te bekijken van een pilaar nadat deze

doorgesneden was met behulp een gefocusseerde ionenbundel (FIB). De

elektrische eigenschappen van zowel fosfor- als boor-gedoteerde pilaren

waren verbeterd in vergelijking met vlakke zonnecellen.

De hiervoor beschreven micropilaren zijn verder geoptimaliseerd, zoals

beschreven in Hoofdstuk 4, door middel van de variatie van de hoogte en de

junctiediepte. De hoogte is gevariëerd tussen de 0 en 60 µm, en gaf de

hoogste efficiëntie bij een hoogte van 40 µm. De lagere efficiëntie van hogere

pilaren is toegeschreven aan het toenemend aantal oppervlaktedefecten bij

Samenvatting en visie

128

toenemende pilaarhoogte, hetgeen tot meer recombinatie leidt. Voor de

junctie-diepte is een optimum van 790 nm gevonden. Pilaren met dunnere

juncties gaven geen correct werkende diode en vertoonden lekkage in de

elektrische metingen. Junctiedieptes groter dan 790 nm lieten een lagere

efficiëntie zien, hetgeen verklaard is door het sluiten van de junctie omdat de

depletiezones elkaar raken in het binnenste van de pilaren.

In Hoofdstuk 5 is een verdere optimalisatie besproken, waarbij een laag

gebruikt is om passivatie en anti-reflectiviteit te bewerkstelligen. De defecten

die geïntroduceerd zijn door het etsen, konden worden verminderd door een

dunne laag Al2O3 (door middel van atoomlaag-depositie, ALD), SiNx of SiO2

(beide door middel van LPCVD) op te brengen. Door de dikte van de laag

goed af te stemmen op de lichtabsorptie, kon de laag tevens als een anti-

reflectielaag gebruikt worden. Het 3D deponeren van deze lagen is

onderzocht, wederom met behulp van FIB. Voor zowel de p- als n-gedoteerde

zonnecellen bleek een laag van Al2O3 de grootste efficiëntieverhoging te

geven.

In Hoofdstuk 6 tenslotte is een methode besproken voor het functionaliseren

van silicium. Hiervoor is een axiale junctie in vlak silicium gemaakt met behulp

van „spin-on-doping‟, gevolgd door cryogeen etsen om zo micropilaren te

verkrijgen die deels p- en deels n-gedoopt zijn. Door gebruik te maken van de

p/n junctie konden de onderste en bovenste helften apart gefunctionaliseerd

worden met respectievelijk platina (in het donker) en zilver (in het licht). Deze

metalen zijn afgezet door middel van elektrochemische depositie, zonder

daarbij gebruik te maken van een maskerlaag. Een klein,

niet-gefunctionaliseerd pilaargedeelte is waargenomen tussen de delen die

met platina en zilver bedekt waren en berekeningen geven aan dat dit

overeenkomt met de breedte van de depletiezone.

Samenvattend blijkt dat micropilaren met radiale juncties goed gefabriceerd

zijn en verder geoptimaliseerd hebben kunnen worden, door gebruik te maken

van verschillende technieken. Deze siliciumstructuren kunnen wellicht gebruikt

Samenvatting en visie

129

worden voor S2F-apparaten, om zo zoveel mogelijk licht te absorberen en

daarmee de efficiëntie te verhogen. De passivatie- en anti-reflectielaag kan

wellicht ook als chemische beschermlaag dienen, om zo de stabiliteit van de

zonnecellen te verbeteren in waterige oplossingen. Bovendien is aangetoond

dat axiaal gedoteerde siliciumpilaren met verschillende materialen

gefunctionaliseerd konden worden door gebruik te maken van de

eigenschappen van de p/n-junctie in licht en donker. Deze aanpak kan een

bijdrage leveren aan het aanbrengen en gebruiken van verschillende

katalysatoren op dezelfde pilaren.

130

131

Appendix A

A.1. Process flow radial junctions

Process parameters for radial junctions in micropillars using solid source

dotation of boron or low-pressure chemical vapor deposition of phosphorus.

A.1.1. Wafer selection

Substrate Silicon <100> OSP N-type (#subs109)

Orientation: <100> Diameter: 100mm Thickness: 381 µm ± 15 Polished: Single side polished Resistivity: 1-10 Ωcm Type: N

OR

Substrate Silicon <100> OSP P-type (#subs108)

Orientation: <100> Diameter: 100mm Thickness: 525 µm ± 25 Polished: Single side polished Resistivity: 5-10 Ωcm Type: P

A.1.2. Wafer processing

Steps 1-31 are only necessary in the process of n-type wafers, p-type wafers

start at 32.

Process Comment

1

Cleaning in 99% HNO3 (#clean001)

NL-CLR-WB14 Purpose: removal of organic traces. • Beaker 1: 99% HNO3 • Time: 5 min

N-TYPE

ONLY BEGIN

2



3

Quick Dump Rinse (QDR) (#rinse119)

NL-CLR- WB14 Purpose: removal of traces of chemical agents.

4

Cleaning in 69% HNO3 at 95 °C (#clean003)

NL-CR-WB14 Purpose: removal of metallic traces. • Beaker 3a or beaker 3b: 69% HNO3 • Temp: 95 °C • Time: 10 min

5



Appendix A

132

6 Substrate drying (WB14) (#dry159)

NL-CLR-WB14 Batch drying of substrates

7

Etching in HF (1%) (#etch127)

NL-CLR-WB15 Purpose: removal of native SiO2 from silicon wafers. Beaker: HF 1% Time: 1 min

8



9

Substrate drying (WB15)

(#dry160)


10

LPCVD of SiRN (250 MPa) (#film155)

NL-CLR-Tempress LPCVD G4 Program: N2 LSNIT-G4 (200 mTorr) • SiH2Cl2 flow: 150 sccm • NH3 flow: 50 sccm

100 nm in 12

min

11

Inspection of LPCVD/PECVD layers (#metro113)

NL-CLR-cold light source Particle and haze inspection by using cold light source

12

Ellipsometer measurement (#metro107)

NL-CLR-Woollam M-2000 ellipsometer

13

DRIE of SiO2, SiRN (#etch157)

NL-CLR- AdixenDE Layer thickness: < 5 μm SiO2 SH Temp: -10°C - Pos: 120mm - He pres.: 10 mbar Flows C4F8: 20 sccm - CH4: 15 sccm - He: 150 sccm Pressure: 8.5 10

-3 mbar

ICP: 2800 Watt CCP: 350 Watt (RF)

Backside only,

45 sec

14

Chamber clean AdixenDE (#etch201)

NL-CLR-AdixenDE Chamber clean to remove fluorocarbon Needed after every 20 min processing SH Temp: any- Pos: 150mm - He pres.: 10 mbar Flow O2: 200 sccm APC 100% / Pressure: 1.5 10

-2 - 6.0*10

-6 mbar

ICP: 3000 Watt CCP: 50 Watt (RF) Clean with a plain silicon wafer in the etch tool Cleaning time: 30 minutes

15

Stripping of photoresist and FC after DRIE (#strip121)

NL-CLR-TePla 360M Recipe 035

16



17



18

Quick Dump Rinse (QDR)

(#rinse119)

NL-CLR-WB14 Purpose: removal of traces of chemical agents.

19

Cleaning in 69% HNO3 at 95 °C

NL-CR-WB14 Purpose: removal of metallic traces.

Process flows

133

(#clean003) • Beaker 3a or beaker 3b: 69% HNO3 • Temp.: 95 °C • Time:10 min

20



21

Substrate drying (WB14) (#dry159)


22



23



24



25

LPCVD of PSG (TEOS)

(#film188) NL-CLR-LPCVD H4 • Program: N2-PSG • 330 sccm PH3

• 50 sccm TEOS • 45 min deposition

26

Anneal at 1050 °C (#film168)

NL-CLR-Furnace B3 • Standby temperature: 800 °C • Temp.: 1050 °C • Gas: N2 • Flow: 2 L/min

27

Etching in BHF (1:7) (#etch124)

NL-CLR-WB06 Use dedicated beaker BHF (1:7)

15 min // Until

hydrophobic

28



29

Substrate drying (#dry120)

NL-CLR-WB06-08 Batch drying of substrates

30


NL-CLR- AdixenDE Layer thickness: < 5 μm SiO2 SH Temp: -10°C - Pos: 120 mm - He pres.: 10 mbar Flows C4F8: 20 sccm - CH4: 15 sccm - He: 150 sccm Pressure: 8.5 10

-3 mbar


Backside only,

45 sec

31

Chamber clean Adixen DE (#etch201)


-2 - 6.0*10

-6 mbar


N-TYPE

ONLY END

32



Appendix A

134

33



34



35


NL-CR-WB14 Purpose: removal of metallic traces. • Beaker 3a or beaker 3b: 69% HNO3 • Temp.: 95 °C • Time: 10 min

36



37



38



39



40



41



100 nm in 12

min

42


NL-CLR-cold light source Particle and haze inspection by using cold light source Inspection of LPCVD/PECVD deposited layers like: TEOS SiO2, Si3N4, SiRN, Poly-Silicon Procedure: use streaking light for inspection

43



44


NL-CLR- AdixenDE Layer thickness: < 5 μm SiO2 SH Temp: -10°C - Pos: 120mm - He pres.: 10 mbar Flows C4F8: 20sccm - CH4: 15sccm - He: 150 sccm Pressure: 8.5 10

-3 mbar


Front side

only

45



-2 - 6.0*10

-6 mbar


Process flows

135

46



47



48



49



50



51



52



53



54



55



56

Dehydration bake (#lith102)

NL-CLR-WB21/22 Dehydration bake at hotplate • Temp.: 120 °C • Time: 5 min

57

Priming (liquid) (#lith101)

NL-CLR-WB21/22 Primer: Hexamethyldisilazane (HMDS) Use spin coater: • Program: 4000 (4000rpm, 30sec)

58

Coating Olin Oir 906-12

(#lith104)

NL-CLR-WB21 Coating: Primus Spinner • Olin OIR 906-12 • Spin Program: 4000 (4000rpm, 30sec) Prebake: hotplate • Time: 60 sec • Temp.: 95 °C

59

Alignment & exposure Olin 906-12 (#lith120)

NL-CLR- EV620 Electronic Vision Group EV620 Mask Aligner • Hg lamp: 12 mW/cm

2

• Exposure time: 3 sec

Vacuum +

hard contact

Appendix A

136

60

Development Olin OiR resist (#lith111)

NL-CLR-WB21 After exposure bake: hotplate • Time 60 sec • Temp.: 120 °C Development: developer: OPD4262 • 30 sec in beaker 1 • 15-30 sec in beaker 2

61



62


NL-CLR-WB21 Single substrate drying

63

Post bake Olin OiR resist (#lith109)

NL-CLR-WB21 Post bake: Hotplate • Temp.: 120 °C • Time: 10 min

64

Inspection by optical microscope

(#metro101)

NL-CLR- Nikon Microscope • Dedicated microscope for lithography inspection

65

Plasma etching of silicon (B-HARS) (#etch158)

NL-CLR-Adixen AMS 100 SE B-HARS Standard SH temp: 10 °C - Pos: 200mm - He pres.: 10mbar

Parameters Etch Deposition

Gas SF6 C4F8

Flow [sccm] 250 200

Time [sec] 3 1

Priority 2 1

APC % 100 100

ICP [watt] 1500 1500

CCP LF [Watt] 80 80

Pulsed [msec] 10 on/90 off 10 on/90 off

Variable time:

+/- 3 µm/min

etch rate

66

Stripping of Photoresist and FC after DRIE (#strip121)


67



68



69



70



71



Process flows

137

72



73



74



75

Solid Source Diffusion (SSD) of Boron at 1050 °C (#dopi104)

NL-CLR-SSD furnace Tempress B1 Standby temperature: 700°C Program: SSD-1050 B2O5 deposition • Temp 900 °C • Gas O2, 2 SLM • Gas N2, 2 SLM • Time 15 min Anneal (soak) • Temp.: 1050 °C • Ramp up: 5 °C/min • Cool down: 7.5 °C/min • Gas N2: 4 SLM • Time: variable

N-type ONLY

15 min

76


NL-CLR-WB06

N-type ONLY

10 min

77



N-type ONLY

78

Substrate drying (WB06-WB08)

(#dry157)

NL-CLR-WB06-WB08 Batch drying of substrates

N-type ONLY

79

Dry Oxidation of silicon at 800°C (#film126)

NL-CLR-Furnace B3 • Standby temperature: 800 °C • Program: Ox800 • Temp.: 800 °C • Gas: O2 • Flow: 1 l/min

N-type ONLY

15 min

80


NL-CLR-WB06

N-type ONLY

15 min // Until

hydrophobic

81



N-type ONLY

82

Substrate drying (WB06-WB08) (#dry157)


N-type ONLY

83

LPCVD of PSG (TEOS) (#film188)

NL-CLR-LPCVD H4 Program: N8-PSG • 50 sccm TEOS • 330 sccm PH3

P-type ONLY

84

Annealing of Silicon at 1050°C (#film168)

NL-CLR-Furnace B3 • Standby temperature: 800°C • Program: ANN1050

• Temp.: 1050°C • Gas: N2 • Flow: 2l/min

P-type ONLY

15 min

Appendix A

138

85


NL-CLR-WB06

P-type ONLY

15 min // Until

hydrophobic

86


(#rinse119)


P-type ONLY

87



P-type ONLY

88


NL-CLR- AdixenDE Layer thickness: < 5 μm SiO2 SH Temp: -10 °C - Pos: 120mm - He pres: 10 mbar Flows C4F8: 20sccm - CH4: 15sccm - He: 150 sccm Pressure: 8.5 10

-3 mbar


Backside only,

45 sec

89



-2 - 6.0*10

-6 mbar


90



91

Etching 1% HF (#etch210)

NL-CLR-WB06 use Beaker HF with 1%

1 min // Wafer

MUST be

hydrophobic!

92



93



94

Sputtering of Al (#film122)

NL-CLR-Oxford PL400 • Program: 1000 nm Al position 1 • Pressure: 10 mTorr Deposition rate (100 mm wafer) = 820 nm/min

Backside:

1:13 min

Front side:

2x 36 sec with

shadow mask

Process flows

139

A.2. Process flow axial junctions

Process flow for cryogenic etching of axial n+/p junctions using spin-on-dopant

of phosphorus.

A.2.1 Wafer selection

Substrate Silicon <100> OSP P-type (#subs108)

Orientation: <100> Diameter: 100 mm Thickness: 525 µm ± 25 Polished: Single side polished Resistivity: 5-10 Ωcm Type: P

A.2.2. Process flow

Process Comment

1



2

Cleaning in 99% HNO3

(#clean001) NL-CLR-WB14 Purpose: removal of organic traces. • Beaker 2: 99% HNO3 • Time: 5 min

3



4



5



6 Substrate drying (WB14) (#dry159)


7



8


(#rinse119)


9



10



100 nm in 12

min

Appendix A

140

11


NL-CLR-cold light source Particle and haze inspection by using cold light source

12



13

DRIE of SiO2, SiRN

(#etch157) NL-CLR- AdixenDE Layer thickness: < 5 μm SiO2 SH Temp: -10°C - Pos: 120mm - He pres.: 10 mbar Flows C4F8: 20 sccm - CH4: 15 sccm - He: 150 sccm Pressure: 8.5 10

-3 mbar


Front side

only, 45 sec

14

Chamber clean AdixenDE (#etch201)


-2 - 6.0*10

-6 mbar


15



16



17



18



19


NL-CR-WB14 Purpose: removal of metallic traces. • Beaker 3a or beaker 3b: 69% HNO3 • Temp.: 95 °C • Time:10 min

20



21



22



23


(#rinse119)


24

Substrate drying NL-CLR-WB15

Process flows

141

(WB15) (#dry160)

Batch drying of substrates

25

Spin-on-dopant (#film)

NL-CLR-WB22 • Filmtronics P509 • Program: 6000 rpm, 30 sec

Check expiry

date!

26

Anneal at 1100 °C (#film169)

NL-CLR-Furnace B3 • Standby temperature: 800°C • Temp.: 1100°C • Gas: N2 • Flow: 2l/min

Experimental

Check with

operator!

Time: 60 min

(+/- 3.6 µm

junction)

27

Etching in BHF (1:7)

(#etch124) NL-CLR-WB06 Use dedicated beaker BHF (1:7) Temp.: Room temperature

15 min // Until

hydrophobic

28



29


NL-CLR-WB06-08 Batch drying of substrates

30


NL-CLR- AdixenDE Layer thickness: < 5 μm SiO2 SH Temp: -10°C - Pos: 120 mm - He pres.: 10 mbar Flows C4F8: 20 sccm - CH4: 15 sccm - He: 150 sccm Pressure: 8.5 10

-3 mbar


Backside only,

45 sec

31



-2 - 6.0*10

-6 mbar


32



33

Dehydration bake (#lith102)

NL-CLR-WB21/22 Dehydration bake at hotplate

• Temp.: 120 °C • Time: 5 min

34

Priming (liquid) (#lith101)

NL-CLR-WB21/22 Primer: Hexamethyldisilazane (HMDS) Use spin coater: • Program: 4000 (4000rpm, 30sec)

35

Coating Olin Oir 906-12 (#lith104)

NL-CLR-WB21 Coating: Primus Spinner • Olin OIR 906-12 • Spin Program: 4000 (4000rpm, 30sec) Prebake: hotplate • Time: 60 sec • Temp.: 95 °C

36

Alignment & exposure Olin 906-12 (#lith120)

NL-CLR- EV620 Electronic Vision Group EV620 Mask Aligner • Hg lamp: 12 mW/cm

2

• Exposure time: 3 sec

Vacuum +

hard contact

Appendix A

142

37

Development Olin OiR resist (#lith111)

NL-CLR-WB21 After exposure bake: hotplate • Time 60 sec • Temp.: 120 °C Development: developer: OPD4262 • 30 sec in beaker 1 • 15-30 sec in beaker 2

38



39


NL-CLR-WB21 Single substrate drying

40

Post bake Olin OiR resist (#lith109)

NL-CLR-WB21 Post bake: Hotplate • Temp.: 120 °C • Time: 10 min

41

Inspection by optical microscope (#metro101)

NL-CLR- Nikon Microscope • Dedicated microscope for lithography inspection

42

Chamber clean O2 plasma (#etch200)

NL-CLR-AdixenSE Chamber clean: removal of fluorocarbon residue Apply always before (cryogenic) SF6/O2 processing SH temp: any - Pos: 200 mm - He pres.: 10mbar Gas: 200 sccm O2 ICP: 2000 W, CCP: 50 W

30 min

43

DRIE of Silicon C-SF6/O2 Cryogenic (#etch177)

NL-CLR-Adixen SE Temperature: -100 °C Gas: 100 sccm SF6 Gas: 32.5 sccm O2 ICP: 1000 W SH: 200 mm He pres.: 10 mbar

Approximately

2.5-3 µm/min

44



45



46



47



48



49


(#rinse119)


Process flows

143

50



1 min // Wafer

MUST be

hydrophobic!

51



52



53

Sputtering of Al (#film122)

NL-CLR-Oxford PL400 • Program: 1000 nm Al position 1 • Pressure: 10 mTorr Deposition rate (100 mm wafer) = 820 nm/min

Backside:

1:13 min

Front side:

2x 36 sec with

shadow mask

144

145

Dankwoord

Na vier jaar is het dan zo ver, ik mag mijn dankwoord schrijven. Met de nadruk

op „mag‟, doel ik op het feit dat het een eer is om dit te kunnen doen. Na een

langdurig project, waarbij je in het begin vaak nog geen idee hebt wat eruit zal

komen, is het opleveren van je „boekje‟ een gevoel waar je trots op kan zijn.

Uiteindelijk is het een resultaat dat tot stand gekomen is door vele

experimenten, discussies, presentaties en een goede dosis toeval. Tijdens mijn

promotie heb ik het geluk gehad dat ik met veel personen heb mogen

samenwerken en daarvoor wil ik iedereen graag bedanken in dit dankwoord.

Allereerst wil ik graag mijn professoren, Jurriaan en Han, bedanken door mij de

mogelijkheid te hebben geven een promotieonderzoek op dit interessante

onderwerp te doen. Samen zijn jullie een sterk team begeleiders en vullen

elkaars kwaliteiten goed aan. Ik heb altijd genoten van onze twee-wekelijkse

besprekingen, waarin we efficiënt door de plannen en resultaten heen gingen.

Het feit dat ik gedeeld werd tussen twee vakgroepen heb ik altijd als voordeel

gezien, zowel wetenschappelijk (bredere expertise) als sociaal (twee keer

zoveel taart en vakgroepuitjes). Jurriaan, vooral jouw directe en kritische manier

van denken en begeleiden heeft me vaak geholpen om zo efficiënt mogelijk aan

de slag te gaan, zonder de belangrijke aspecten uit het oog te verliezen. Han, je

kan soms met slechts één zin of vraag een probleem in kaart brengen of zelfs

een complete oplossing geven (“Waarom probeer je de methode van dit patent

uit 1974 niet eens?”). Hierdoor is het schrijven van artikelen en het proefschrift

ook erg vlot verlopen.

Naast de begeleiding van de professoren, heeft Roald mij ook erg veel

geholpen. Roald, vooral in de beginfase van mijn onderzoek heb je mij veel

geleerd op het gebied van werken in de cleanroom, waardoor we binnen no-

time op grote schaal pilaren fabriceerden. Naarmate het cleanroom-werk steeds

beter ging, heb je alsnog je bijdrage geleverd in de talloze discussies van de

nieuwste resultaten en het corrigeren van mijn artikelen. Mede door jou heeft

het een aantal mooie publicaties opgeleverd. Vooral de manier waarop we het

Dankwoord

146

review-artikel uit het niks hebben opgezet, laat zien dat de samenwerking

perfect verliep, met een artikel waar we beide erg trots op zijn (Hoofdstuk 2).

Behalve op wetenschappelijk gebied, hebben we ook erg veel lol gehad met

squash, bier en voetbal. Op één of andere manier raken we daar nooit over

uitgesproken, en dit zal waarschijnlijk ook nooit gebeuren.

Tijdens mijn promotie heb ik ook twee masterstudenten begeleid, Nienke en

Alexander, die ik wil bedanken voor hun inzet. Nienke, jij was op zoek naar een

uitdagend project op het gebied van duurzame energie. Volgens mij is dat goed

gelukt en, samen met Janneke, was de begeleiding ook erg makkelijk

aangezien je heel gemotiveerd en enthousiast was. Dit is uiteindelijk ook terug

te zien in je mooie verslag. Alexander, we had a lot of fun in the cleanroom

trying to replicate a difficult pillar process. Your eagerness and persistence on

the project made the guidance easy, with some nice results in only a few

months‟ time. After your master project, I was happy to hear that you started a

PhD position at Guido‟s group, and our collaboration continued and you

assisted me in the electrical measurements that led to the first paper

(Chapter 3). As you gained experience in your own project, we started a new

experiment, which led to a nice paper about the combination of our separate

projects, as seen in Chapter 6.

Ook wil ik graag mijn paranimfs bedanken, Jasper en Wouter. Jasper, hoewel

onze projecten verre van overeenkomstig waren, hebben we altijd goed kunnen

discussiëren over onze bevindingen, en hielden elkaar scherp. Op sociaal

gebied hebben we een stuk meer samengewerkt, wat zich tot uiting bracht als

geniale avonden met slechte films en presentaties over frituur. Ik ben blij dat we

bijvoorbeeld de aziatische culltuur kennis hebben laten maken met New Kids en

het ontstaan van de kroket. Ook onze coop-wandelingen waren zeer gezellig,

en konden we beide onze verbazing over van alles en nog wat kwijt. Wouter, jij

kwam ongeveer 1,5 jaar voor het einde van mijn PhD bij de MnF vakgroep, en

we zijn eigenlijk direct aan de slag gegaan om voortgang te boeken. Je hebt

veel geholpen met het meedenken van de vervolgstappen van mijn project, en

hieruit is het werk in Hoofdstuk 4 uitgekomen. Met je eigen project kwam je toen

Dankwoord

147

ook al een stuk verder, en in Hoofdstuk 5 hebben we dit tot een mooi resultaat

gebracht. Op persoonlijk gebied was ik ook erg blij dat je bij de vakgroep kwam,

aangezien onze passie voor bier en squash goed overeen kwam, met als

hoogtepunt om 7:00 squashen met een kater op Ameland tijdens het

vakgroepsuitje. Klein minpunt is dat ik nog steeds moet vrezen voor mijn leven

als we samen op de squashbaan staan.

Verder heb ik veel samengewerkt met de mensen betrokken bij het TBSC

cluster op de UT; Janneke, onze projecten waren in het begin niet heel sterk

verbonden, maar met Nienke‟s masteropdracht erbij hebben we toch een aantal

leuke experimenten gecombineerd. Het blijft altijd typisch dat het laatste

experiment voordat we er mee zouden stoppen, de meest interessante data

gaf. Hopelijk gaat het nog ergens toe leiden, maar dat komt vast goed met jouw

optimisme, in combinatie met je realiteit (volgens mij doet er niemand zoveel

controle experimenten als jij ). Sun-Young, we started together on the same

project and tested many different options. Unfortunately, we were not that lucky

to get everything to work as we wanted. You did help a lot with the

measurements at PCS, for which I am thankful. Ook wil ik graag de andere

leden van de TBSC groep bedanken voor alle discussies; Jennifer, Guido,

Annemarie, David, Qing, Saskia, Samuel, Peter, Sebastiaan.

Aangezien ik deel uitmaakte van twee verschillende vakgroepen (MnF en MCS)

en vaak rondliep bij PCS, zijn er een hoop mensen die mij ondersteund hebben

met veel verschillende dingen; Nicole, Izabel, Richard, Marcel, Robert, Stefan,

Brigitte, Jacqueline, Bianca en Regine. Nicole en Izabel, jullie wil ik bedanken

voor het regelen van alle organisatorische zaken rondom FOM, en het

beantwoorden van talloze vragen. Marcel, jij snapte mijn ergernis dat er geen

cola-automaat op de 4de

verdieping van Carré staat, en hebt dit goed opgelost

door een koelkast te vullen op jouw kantoor, waar ik veelvuldig gebruik van heb

gemaakt.

Ook wil ik graag de SaNS-stafleden bedanken voor het regelen dat de

vakgroepen een fijne plek waren om te werken; Wim, Jeroen, Pascal, Nathalie

Dankwoord

148

en Tibor. Pascal, jou wil ik in het bijzonder bedanken, omdat jij met de

begeleiding van mijn bachelor- en masterproject een grote bijdrage hebt

geleverd aan mijn interesse voor het wetenschappelijk onderzoek.

Veel van mijn experimenten heb ik in de cleanroom van het Nanolab

uitgevoerd, en het ondersteunende personeel heeft mij daarbij veel geholpen;

Peter, Hans, Ite-Jan, Samantha, Marion, Huib, Mark, Gerard, Eddy, Ton,

Robert, Rene, Meint, Christiaan en Sharron wil ik daarvoor bedanken. Hans,

Peter en Rene, jullie wil ik speciaal bedanken voor alle vragen die ik tijdens mijn

experimenten had, en vooral voor het oplossen van talloze problemen met de

apparaten, maskers e.d. In het bijzonder wil ik Kees en Stefan bedanken, die

mij meerdere malen met problemen/processen hebben geholpen als

medegebruikers in de cleanroom.

As a PhD takes 4 years, there are many people I have encountered and who

left the group before me and I would like to thank a few in particular: Pieter,

Carmen, Sven, Rik, Wies, Raluca, Rajesh, Kim, Carlo and Jordi. I would also

like to thank all current members of MnF and MCS, but I will not mention every

single one of them, as the list would become extremely long .

Tot slot wil ik graag familie en vrienden bedanken, die mij op allerlei

verschillende manieren geholpen hebben. Pap en mam, jullie wil ik graag

bedanken voor alles wat jullie voor me betekend hebben. Dit valt niet uit te

leggen in een paar zinnen, maar jullie hebben me altijd ondersteund in alle

keuzes die ik gemaakt heb. Als laatste wil ik graag mijn vrouw, Alexandra

bedanken. Alex, jij hebt er voor gezorgd dat ik in mijn privéleven nooit zorgen

heb hoeven maken over wat dan ook. We zijn alweer negen jaar samen, en

tegelijk met het begin van mijn PhD zijn we samen gaan wonen. Afgelopen jaar

zijn we getrouwd, en ik kijk erg uit naar wat de toekomst ons samen nog

allemaal te bieden heeft.

Rick,

Enschede, November 2015

149

Curriculum Vitae

Rick Elbersen was born January 6, 1987 in Deurne, the Netherlands. In 2005,

he started his bachelor chemical engineering at the University of Twente. He

received his bachelor degree in 2009, after which he continued with his master

Molecules & Materials. In 2011, he graduated for his master assignment under

the supervision of Prof. dr. Pascal Jonkheijm and Prof. dr. ir. Jurriaan Huskens

at the Molecular NanoFabrication group. The title of the project was

„Charactization of adamantane functionalized perylene bisimides for the

detection of β-cyclodextrin modified molecules‟.

Starting from July 2011, he has been working as a PhD candidate at the

Molecular Nanofabrication group and the Mesoscale Chemical Systems group

at the University of Twente, under the supervision of Prof. dr. Jurriaan

Huskens and Prof. dr. Han Gardeniers. The aim of the project was the

fabrication and improvement of silicon solar cells. The results of his PhD work

are described in this thesis.

150

Publications

1. R. Elbersen, R.M. Tiggelaar, A. Milbrat, J.G.E. Gardeniers, J. Huskens;

“Controlled Doping Methods for Radial p/n Junctions in Silicon

Micropillars”

Adv. Energy Mater., 2015, 5, 1401745

2. R. Elbersen, W.J.C. Vijselaar, R.M. Tiggelaar, J.G.E. Gardeniers, J.

Huskens;

“Fabrication and Doping Methods for Silicon Nano- and Micropillar

Arrays for Solar Light Harvesting: a Review”

Adv. Mater., 2015, doi: 10.1002/adma.201502632

3. R. Elbersen, W.J.C. Vijselaar, R.M. Tiggelaar, J.G.E. Gardeniers, J.

Huskens;

“Effects of Pillar Height and Junction Depth on the Performance of

Radially Doped Silicon Pillar Arrays for Solar Energy Applications”

Adv. Energy Mater., 2015, accepted

4. A. Milbrat, R. Elbersen, R. Kas, R.M. Tiggelaar, J.G.E. Gardeniers, J.

Huskens, G. Mul;

“Spatioselective Electrochemical and Photoelectrochemical

Functionalization of Silicon Microwires with Axial p/n Junctions”

Adv. Mater., 2015, accepted

5. W.J.C. Vijselaar, R. Elbersen, R.M. Tiggelaar, J.G.E. Gardeniers, J.

Huskens;

“Electrical Characterization of Silicon Micropillars with Radial p/n

Junctions Containing Passivation and Anti-Reflection Coatings”

in preparation

Documents

Fabrication and Doping of Silicon Micropillar Arrays for Solar Light Harvesting Rick Elbersen