Fabrication of Semiconductor

8/4/2019 Fabrication of Semiconductor

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SEMICONDUCTOR FAB PROCEDURE

The story of the Chip

VLSI DESIGN

– Specifications. – Design hierarchy. – Design abstraction - HDL / schematic. – Design simulation - subckts / complete – Design verification. – Design synthesis / custom Transistor level. – Design layout - EDA tools for layers. – DRC / LVS verification . – GDSII tape out.

EDA TOOL CENTRIC

The VLSI FabricationFoundary

The design process

SILICON MATERIALINDUSTRY

– Source of polished siliconwafers as substrates

G D S I I L a y e r d e t a i l s

L i b r a r i e s , M o d e l s

& L a y e r i n g R u l e s

The VLSI fab process

The packaged chip

The ASIC

Packaging

The programmableASIC

FPGA / CPLD

P a c k a g e d A

r r a y

Program codes



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Poly Crystalline Silicon

Crystal Pulling

Wafer slicing

Lapping &

Polishing

Wafer Epitaxy Process

Oxidation & Layering

Metal Etch

Metal Deposition

New Copper Deposition

CVD Process

Ion Implant

Acid Etch

Spin Rinse Dry

Develop&

Bake

Pattern preperation

Stepper exposure

Photoresist coating

Ashing

Probe test & Die cut

Wire Bonding

Packaging

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3A.00


Poly Crystalline Silicon

Raw Poly-crystalline Silicon Rods

Poly silicon ingots / nuggets

Raw Polycrystalline silicon is manufactured by mixing refined Tri-chlorosilanewith Hydrogen gas in a reaction furnace and allowing the polycrystalline silicon togrow onthe surface of electrically heated tantalum metal wicks.

They then refine the polycrystalline tubes by dissolving in hydrofluoric acid and produce poly silicon ingots.Because polycrystalline silicon has randomly oriented crystalline structure it does not haveconsistent

properties for fabrication of semiconductor devices like transistors.

Polycrystalline silicon has to be converted into Single Crystal Silicon by a process called Czokralski CrystalGrowing or Crystal pulling into single crystal of known crystal orientation and without defects and having agiven electrical property by addition of controlled dopants to achieve n-type or p-type single crystal siliconingots. Usually polycrytalline silicon is basically intrinsic in nature with a high resistivity.Commercialcompanies which produce Polysilicon include MEMC , KOMATSU, Shin-Etsu & WACKER SILTRONICS.

Crystal Pulling

The next step in the Semiconductor manufacturing process is converting Polysilicon

into Single crystal silicon and with a controlled dopant to form either a n-type or p-typesilicon crystal of given orientation and resistivity. This is a very crucial step in the

processing of silicon for the semiconductor industry, since without single crystalsilicon it is not possible to build any integrated circuit . Polysilicon itself cannot beused since its crystal structure is non-uniform . This process of single crystal formationis called Crystal Growing.

Crushed polysilicon crystalline is doped with a controlled amount of arsenic or phosphorous for n-type or boron for p-type and melted at about 1400 deg., Centigradein a Quartz cruicible surrounded by an inert gas atmosphere of high purity argon. Themelt temperature is very precisely cooled to a given temperature and a seed of a givencrystal orientation is dipped and slowly rotated as it is pulled upwards at a controlledspeed. Surface tension causes a little of the liquid silicon torise with the seed and cool to form a single crystal as the same orientation as the seed.The process is carefully controlled and continued with the pulling speed varied to

change the diameter of the crystal being grown and then controlled to maintain thegiven diameter as the process continues. The entire process is very slow and may takeseveral days to complete when the finished crystal grown is about 100 Kgs in weightand 12 inches in diameter.

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Single crystal Silicon ingots are characterised by their crystal orientationand n-type / p-type electrical resistivity. The crystal orientation itself isidentified using X-ray diffraction and grinding one or two flats of thesurface of the crystal. This is done before the

crystals are sliced into wafers.


Silicon Crystal CharacterizationPrimary flat

Secondary Flat

ID Wafer Slicing

Once the Silicon crystal ingots are characterized they have to be sliced intowafers about 500 microns thick . This process is done in a precision machinecalled the ID saw with a diamond studded blade whose thickness is about 300microns. The blade is made rigid on the IDsaw machine using special

hydraulics and the diamond studded inner periphery is used as the cutting edge.The Wafers at this stage are called “as cut wafers”. Saw marks will be presentand these need to be removed. The wafers need to be sliced without bow .

Wafer Lapping

The as cut wafers are lapped mechanically in a counter-rotatinglapping machine with aluminium oxide as the lapping medium in theform of fine slurry. This process mechanically removes the slicing

blade marks and makes the two surface sides of the wafer flat and parallel to each other. This process is crucial since further ICmanufacturing process relies on this flatness of the wafer surfacewhere the devices are fabricated after polishing. This process cannotcorrect bow which needs to be taken care in the slicing stage .

The lapped wafers are etched in an acid medium using a mixture of nitric /acetic or Sodium Hydroxide to remove any microscopic damages left over

by the mechanical lapping process. The wafers are then cleaned thoroughlywith ultra-purified RO / DI water to remove any trace of the etchingchemicals. Since the technology feature size of the devices that willultimately be fabricated is deep in the sub micron range, extremely tightcontrol on the nature of the cleansing DI water is essential for the success

of the process.

Wafer Polishing The wafers are then polished in a series of a combination of chemical andmechanical polishing. The wafers are held in a hard ceramic chuck using a waxto hold one side of the wafer and the polishing is carried out on the other side.For the process of IC manufacture only one side is polished and the devices aremade on this polished side at a later stage. The polishing medium is a slurry of fine silica powder in DI/RO water and Sodium hydroxide. The process is carriedout in two or three steps with finer and finer slurry to achieve high polishedquality. The polished wafers are cleaned in a mult-step process with ammonia,hydrogen peroxide, and RO/DI water. An Hydrofluoric acid rinse removesnatural oxides and metallic impurities which would be detrimental to further

process stages. The polished wafers are completely handled in ultra-clean rooms

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Epitaxy Process

The polished wafer enters the device fabrication stage . Many times the devicesare not made directly on the polished surface of the silicon wafer itself, but on aepitaxial layer of silicon grown on the polished side of the wafer which is nowcalled a substrate. This process called EPI grows a layer of single crystal silicon

from vapour into the single crystal silicon substrate at high temperatures.Trichlorsilane or Silicon tetrachloride and hydrogen are combined with either diborane or phosphine gas to achieve the type resistivity ( p-type or n-typerespectively). The purpose of the epi layer is to create a different layer of controlled conditions other than the substrate’s polished layer itself. The epilayer grows following the crystal orientation of the silicon substrate.

Typical EPI Reactor

Oxidation & Layering

The fabrication process enters the device manufacture steps now. Thefirst step in this process and the backbone to the fabrication line is theOxidation Process. This process produces a thin layer of Silicondioxide on the substrate / or on the epi layer as the case may be by

exposing the wafer to a mixture of high-purity oxygen and hydrogenat +/- 1000 deg C. This oxide layer forms the insulating layer and may

be up to about 1500 angstroms. Oxides are also used for gate in theMOS device and in this case the thickness is about 200 to 300angstroms.

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Photo Resist Coating

Photoresist is a photo-sensitive material applied on the wafer in a liquidstate in small quantities. The wafer is then spun at about 3000 rpm whichspreads this photo-resist liquid layer into an uniform layer between 20 to100 microns thick..

The photo-resist layer is then exposed to light of a specific wavelengthwith the MASK superimposing the layer details for photoresist to beremoved from specific locations.

Mask Making

The MASK itself carries the layer image to the details worked out by the IC designer for the layer under fabrication. The Fabrication process itself is thus an incremental process forming layer after layer of thevarious layers in the design in a given sequence to implement physically all the devices and the metallicinterconnects to form the complete IC. The pattern for each layer is in the form of a Software code designed

by the IC design team. The Reticle for the layer in consideration is made in the Pattern Generator whichrasterizes the CAD pattern and with a series of beam splitters and mirror / shutter combinations patterns thereticle’s surface as a one-to-one image of the CAD layer. For devices larger than 1.5 microns, the reticle isfor the entire wafer, but for smaller devices, the patter corresponds to only one device (one of the many onthe wafer) and stepped individually.Semiconductor devices are made up of as many as 50 individual layers

of silicon,poly-Silicon , Silicon Dioxide, Metals and Silicides. The pattern of each layer is contained on aMASK called a RETICLE. These are 1 to 10 times the actual size of the patterns of each layer and a groupof these make up all the needed layers of a typical device and this group is called a SERIES. A RETICLE isan optically clear Quartz Substrate with a chrome pattern. To keep the surface of the Reticle clean, a thin

plastic sheet called the PELLICLE is mounted a short distance away from the surface of the reticle. Thisallows the reticle surface to be cleaned without contacting the Chrome mask surface, and also ensures thatany microscopic dust which may settle on the Reticle will be out of focus during exposure and will notcreate defective layer.

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Laser Pattern generator - scheme E-beam pattern generator

Rotating polygonal scanning mirror

Scan Lens

Magnificationadjustment

Steering

Mirror

Patterndescription

data

Rasterizer

Ultra-violet Laser

Beam shaping

32 beam splitter

Brush of 32 beams

Acousto - opticmodulator

Objective Lens

Laser interferometer for stage position control

Charge Amp

Laser mask height sensor

Objective lens

Three stage beamdeflection system

Pattern generating blank & aperture

First transfer lens

Second transfer lens

Auxiliary blanker & limiting aperature

Source condensing lens

Thermal field emissionelectron beam sourceSource

electrodes

Mask

XDY stage



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Stepper Exposure

Applying and exposing photoresist to create a desired layer on a wafer is similar to MASK making. A stepper Machine is normally used for this purpose. In this process a photoresist coated wafer isexposed to a single wavelength of UV light passing through a Reticle

which contains the image of a given single layer of the device under fabrication. The term “Stepper” comes from the “Step and Repeat”action of moving the wafer in the X and Y axes to align the Reticlewith each individual device position for all the devices that areeventually going to be implemented on the wafer

UV light is used because modern device features are verysmall and are comparable to the wavelength whichultimately becomes the limiting factor. UV has ashorter wavelength (less than 500 nm) than visible lightwhich allows the creation of small features. Even

broadband UV (or multi-wavelength) is capable of goingdown to 2 microns and hence useless for modern daydevices having feature size near 0.18 microns. Thisrequires use of 436 nm (G-line), 405 nm (H line ) , 965nm (I-line) and 248 nm (Deep UV). Experimentations

are also in progress with X-rays for even shorter wavelength. The Stepper Machine has gotelaborate control systems and technologies for accurate geometric movement control andinternal temperature control to prevent anythermal expansion / contraction from ruining the

accurate dimensional control needed in the process.

This process of lithography is one of the mostcomplex and advanced steps in IC fab techniquessince the process creates a preferred windowwhere further processes layers are going to

preferentially fit. Any error here compared to thegeometry feature size of the technology willresult in catastrophic failure of the entire fab

process

Develop & Bake

After developing and stripping

After exposure the wafers are developed in either an acid or base solution toremove the exposed portion of the Photoresist. The wafer is then soft baked at alow temperature to harden the remaining areas of the photoresist.

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Acid Etch

Removing selected areas of material from the wafer involves the use of different types of acids , bases or caustic solutions. Much of the etching work iscarried out in specially designed automatic wafer handling benches. For example to remove oxide layer without damaging the underlying silicon or

polysilicon layer, phosporic acid is used for etching silicon nitride layers, nitricacid for etching metal layers and sulphuric acid used to remove photoresist.Another highly corrosive acid that is used in this processing step is HF (HydroFloric acid ). Acid etching procedures are generally need for cleaning thesurface as well as removal of the mechanical fractures that could have beencreated in the previous process handling steps. Sometimes these steps arereferred to as chemical milling in the micro fabrication industry.

Spin & rinse - drying

Protection of the wafer surface from damage and contamination arethe primary concerns in a wafer fabrication facility. Silicon isextremely brittle and so handling of wafers is carried out using thewafer holding cassettes or boats and adequate measures taken to

prevent even the smallest dust particle from coming into contact withthe wafer surface which will damage the device fabrication process.Fabrication facilities are housed in multimillion dollar Cleanroomsand all personnel wear special gowning (”bunny” suits and surgicalmasks and gloves) to reduce the possibility of air-bornecontamination. Robotics and automated wafer handling is employed

wherever possible, and when manual handling is needed, vaccumwands are used to handle wafers. Even with these precautions wafershave to be constantly cleaned and for this purpose the SPIN,RINSEand DRYER is used. For the purpose of cleaning RO/DI water isused and Ultra High Purity Nitrogen is used for Drying.

Ion Implantation

Ion implant creates an exclusively doped layer in the substrate. Devicefabrication needs precise areas of the substrate doped in precisemethods to form various parts of the devices. The Ion implanter doesexactly this. The ion implanter uses a high current accelerator tube and

steering and focus magnets to bombard the wafer surface with ions of a particular dopant which get implanted in the wafer surface. To create aninsulating or p-type region and acceptor ion such as boron, gallium or indium is implanted. To create a conducting or n-type region a donor ion such as antimony, arsenic , phosphorous or bismuth is implanted.The bombarding ion-density is actually controlled by the ion-beamcurrent ( normal order in the milli-amps range). The process

parameters for ion-generation and focus is precision controlled withoutwhich mis-alignment will ruin the devices under fabrication.

Inside the implanter





Metal deposition

Metals like aluminium, gold and tungsten are used to createconductive layers on the device. They are generally appliedwith two different methods, evaporation and sputtering,grouped into category of “Physical Vapour Deposition” or

PVD.

Evaporation uses heat (either an electric filament or anelectron beam) and high vaccum to vaporize the metal source.The vacuum is of the order of 1 to 5 micro Torr. Theevaporating source material condenses on the cool wafer surface held in a planetary or semi-hemisphericalarrangement over the source.

Sputtering uses a cathode to create an argon plasma which bombards the source material. The dislodged metal moleculesare focused by a “lens” of radiation-absorbment materialcalled the collimator and gets deposited in a thin film on thewafer surface.

While the usual conductive layer metals are aluminium, gold and tungsten, the semiconductor industry hasalways been in search for a process to use Copper since the resistance of copper is 40 % less thanaluminium which translates into about 15 % increase in speed. In ultra-small chips at high current densities,copper is far less vulnerable than aluminium to electromigration (movement of individual atoms caused

by high electric currents}causing voids and conductor breakdown. The problem with Copper was because itwas considered as a Semi-conductor killer. Copper rapidly diffuses into silicon and also change theelectrical properties of silicon in such a way as to prevent transistors functioning. However, IBM finallyovercame this problem with a key technology for copper patterning called Damascene. In conventional

deposition, a layer of metal and photoresist are deposited on the wafer . The unwanted metal is then etchedaway with an appropriate chemical, leaving behind the desired pattern. Next the spaces between the metallicwires so formed is filled with Silicondioxide and finally the entire wafer surface is polished to remove theexcess insulator oxide. The Damascene process patterning involves the same steps, but reverses the order of deposition. The patterns of the metal lines and vias is first formed in the oxide layer by etching the oxide.The metal is then formed on top of this and the excess metal thickness over and above the oxide thickness is

polished away. In both conventional and the Damascene patterning the process is repeated many times toform the alternating layers of metal wires and vias which form the interconnecting network on the chip.To overcome copper’s tendency to diffuse into silicon, IBM devised a means of depositing a complexcopper structure on polymide, a compound used as an electrical insulator in silicon chips.

SEM view of the copper interconnect technology







Probe & Die test

After the final passivation layers are applied, the entire wafer goes through backside preparation, whichthins the wafer to allow better heat dissipation and removes stress fractures which could cause breakage.Each finished wafer may contain several hundred actual devices or DIE. Automated methods to test andisolate faulty DIEs are carried out and the good devices scribed and cut-out into chips. A probe tester uses

needle-like ‘probes’ to contact the bonding pads on each device and check its operation. Devices that failare marked out. The cut DIEs are sent for the wire-bonding process. The yield of the process is the ratio of the good devices in relation to the total devices targeted in the wafer.

Wire bonding

The wire bonding head

Once seperated into individual DIE, the functionaldevices are attached to a LEADFRAME assemblyand gold leads are attached via thermal compressionor ultrasonic welding. The automated process attachesultra-thin wires (about 30 microns ) between eachdevice’s bonding pad and a connector of the LeadFrame.

Packaging

The QUAD PackageAfter wire-bonding is completed, the packaging is completed by sealing the device into a ceramic or plastic enclosure.

Dip package





THE SEQUENCE

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Fabrication of Semiconductor