FADC progress in Vienna

Reported by H.Ishino

for Vienna FADC group

M.Pernicka and H.Steininger

Tests at ViennaY.Ushiroda 　 (KEK) 　

H.Ishino (T.I.T.)Data transfer from FADC to PPCI

Tests for cable cross talk

Other topics related with FADC

Data transfer from FADC to PPCI

• The data transfer was successfully done with the 10MHz clock.

• However, with 20MHz we had a problem.– The first 32 bit datum which has a start bit was

dropped, because the PPCI board needs 80nsec to be ready for receiving data.

– To solve the problem, we dropped the first clock signal.

– Data are transferred successfully. (we performed a long time test for about 12 hours. No error was detected.)

– This may be a potential problem, i.e. a big external noise would cause read out error under real situation.

XVALID (FADC asserts)

10MHz clock

100nsec

Data

80nsec

This datum is not valid

20MHz clock

Data

50nsec

Read out test with a pulse generator

A pulse generator

FADC board

PC (Linux7.1)

data

10bit FADC

TTM trigger (1kHz)

ADC start

Signal input

Read out test with a pulse generator was successfully done.

Checks for cross talk between twisted 30m cables

Single shield

Double shield

Pair shield

No shield

5MHz clock signals

One of twisted cables

The other of the twisted

cables

Differential of the

twisted cables

No cross talk was detected

FADC status

The present Data format32 bits

Start bit (1 bit)

Event counter from TTM (4 bits)

ADC 10 bits ADC 10 bits

Stop bit (1 bit)

ADC 10 bits ADC 10 bits

128/ch

Lower half part of FADC Upper half part of FADC

10 01

0 01 1

0th

127th

We need not duplicate EV counter, start/stop bit. We requested to Vienna group to replace the one of EV and start/stop bit to channel # (4bit) and parity bit.

FADC status

The Data format we request32 bits

Start bit (1 bit)

Event counter from TTM (4 bits)

ADC 10 bits ADC 10 bits

Stop bit (1 bit)

ADC 10 bits ADC 10 bits

128/ch

Lower half part of FADC Upper half part of FADC

10

0 01 1

0th

127th

Channel # (4 bits)

Parity bit (1 bit)

L0 trigger

L0 processor (Altera chip) was already mounted on a FADC board. The program which decides trigger issue by looking at combinations of TA outputs is being developed. If L0 processor issue trigger, a 50nsec width NIM signal and a 120nsec width ECL signal are generated.

By Karawatzki-san (Vienna)

How the L1.5 trigger is implemented (outside of FADC)

We need information of pedestal and noise levels to set a threshold level. Those levels are obtained from a sparcification process running on a PC which collects raw data from FADC boards.

FADC boardsPC (Linux)

Sparc board (CPU50?)

Raw data

Sparcification process

Reduce data size and calculate noise and pedestal

NSM (Network Shared Memory)

Write threshold levels to registers via VME

bus

How often should we update the threshold levels?

By Takeshita san (Osaka U)

noise pedestalRight figures are time variations of noise and pedestal during a run (run#57, exp.17).

Noise decreases by about 6%, while pedestal is almost stable.If we require 5% precision, we need to update the thr. Level one or two times during a run.This estimation came from SVD1.4. Of course the situation of SVD2.0 would be different.

Schedule of FADC

Vienna group will send their system (FADC board, back board, VME crate and power supply) to KEK on middle of Mar.

The full production of FADC boards will start on the end of April and finish on the end of July(?).

L1.5 trigger (inside of FADC)

Registers for a threshold level of each channel have been prepared already. Reading/writing data from/to the registers via VME bus using a sparc CPU board was successfully done.

The output signal of L1.5 trigger

Ch 1

Ch 2

Ch 3

Ch 4

50nsec delay

100nsec delay

150nsec delay

50nsec

20MHz clock

L1.5 output

I am not sure for further more details about cable connection and so on.