Fast position resolution silicon detectorsFast position resolution silicon detectors

OUTLINE

•General properties of position sensitive detectors

•Column Parallel CCD (CPCDD)

•Monolithic Active Pixel Detectors (CMOS imager)

•Depleted Field Effect Transistor Detectors (DEPFET)

•Hybrid Active Pixel Detectors (HAPS)

Gregor Kramberger , DESY

n-Si

U

p+

n+

n-Si

U

up to 1 mm

p+

n+

n-Si

U

up to 1 mm n+

p+

Signal

Position can be determined – center of gravity

Particle tracking Imaging

each particle leaves a trackOnly some photons interact

x

dx

dPexp keV) (5.9 25 m

U

up to 1 mm

Signal

3.6 eV/pair

collection time ~ns order

To obtain good position resolution – high S/N ratio

Segmentation options: •low particle (photons) rate – strip detectors

Bottom side perpendicular segmentationor two detectors (each 1D) can be used!

N

M

Read-out channels/detector module: N+MWhen read-out in:

series: N+M time unitsparallel: bigger of [N,M]

Only projections can be obtained.

M

N•high particle (photons) rate – pixel detectors

Read-out channels/detector module: NxMWhen read-out in:

series: NxM time unitsparallel: bigger of [N,M]

Usually many detector modules are put together to cover the image area!

(silicon is produced in silicon wafer – nowadays already 8” inch)

Detectors diced out of silicon wafers

Similar processing as for microelectronicslithographic steps, etching, implantations, PolySi filling

15 cm diameter

>1m

Slicing the rod in typically 300 m slices

(wafers)

What do we want from one module?A large high resolution “picture” as fast and easy as possible!

few mfew 10 cm2 picture taking rate(frame rate) up to few 10 kHz

without severe restriction on operating conditions, electronics (voltage supply etc) needed

With a lot of effort can be

achieved!

One of the following requirements can be even more demanding on expense of the others!

Many common points: with modification same detector concepts can be used for

both

This talk will try to illustrate different detector options for particle tracking at LC and to some extent their

ability to be exploited for X-ray detection!

The further discussion will refer only to pixel detectors!

• Charge Coupled Devices (CP CCD)

(RAL, Oxford, Liverpool)

•Active Pixel Sensor (APS)

- Depleted Field Effect Transistor Detector

(MPI München, Mainz, Bonn)

- Monolithic Active Pixel Sensors (MAPS, CMOS imager)

(IRES Strasbourg, DESY, NIKHEF)

- Hybrid Active Pixel Sensors (HAPS)

(Warshaw, Krakow, Insubria)

(widely used technology for pixel detectors in HEP)

Division of fast position sensitive detectors with respect to operational principle!

One can not explain everything -> only the concepts will be presented !

things specific to tracking at LC (material budget – thinning of the detectors, power consumption, mechanics, cooling … will be left out)

Different collaborations working on LC

vertex detector(plots taken from their

presentations)

CPCCD - Principles of operation

buried channel CDD•potential minimum moved from the surface by n+

•collected charge is a combination of drift and diffusion (drift much faster – high resistive epi-Si)•p/p+ edge works as a reflection layer•MOS gate is superimposed on top of the n+ layer•the depleted region is controlled by the voltage applied to the electrodes (p1,p2,p3)

CCD is an array of capacitors

PNP CDD•Instead of MOS a p-n-p structure is formed•Larger volume can be depleted and by that higher photon detection efficiency at larger energies ( used for XMM – Newton )

oxidemetal gates

p1

p2

p3

Fully depleted n- bulk

p1

p2

p3

p+

p+ implants

Vp+

(bulk)dep. p

(epi)

U

CPCCD - Readout

Asymmetricaln+ doping

Only one direction of charge transfer possible both direction of charge transfer possible

sine clocks

p1

p2

p3

p1

p2

V

Classical CCD: slow – not appropriate for high frame read-out rates

factor

2in speed

“Classic CCD”Readout time=NxM/out

different frequencies can be used in horizontal shift register

reset

Source follower(1st stage of amplification)2nd stage amplification follows

One can use higher frequency in horizontal shift register – some gain in speed, but not enough!

Typical frequency 5 MHz

Different solution is needed!

2500 20 m pixels

650 20 m

pixels

1.3 cm

10 cm

CCD VXD read-out

2500 20 m pixels

1st layer ladder read-out

TESLA VXD – requires 50 s read-out/frame in layer 1 – huge challenge !read-out of column with ~2500 pixels (10x1.3 cm2) in 50 s (20 kHz frame rate)

S=13 cm2

Fast readout speed only with Column parallel readout new design – first in the world !

• Serial register omitted

• 50 Mpixels/sec from each column

• Image section clocked at high frequency

• Each column has its own ADC/amplifier (compare to classic CCD)

“Column Parallel CCD”Readout time=N/out

• imagine feeding large capacitance (2-3 nF/cm2) at 50MHz:• Low resistivity gates are required - Polysilicon gates replaced by metallized

gates (30% variation in clock amplitudes over CCD - simulations) • Low voltage clocks up to max. 3 V amplitude - to reduce the power heating

• high resistive epi-Si to have large area depleted and therefore fast collection • well capacity ~ 20000 e • n+ implant design to enhance charge transfer between cells

+some other things ……

Two phase, 50 MHz design pixel size 20 μm 20 μm;

Metallized gates + field enhance implant

Metallized gates

PolySi gates + field enhance implant

PolySi gates

SF DC wire bonds

World’s 1st CPCCD prototype

fully designed and operational

at 50 MHz

Fast CPCCD – considerations

Source follower( needs reset ) or Direct Coupling ?

Both charge and Voltage amplifier for DC or SF coupling

5 bit flash ADC

buffer FIFO

Read-out chip (CPR-1 chip, 0.25 mm CMOS, 50 MHz)

FIFO

250 5-bit flash ADCs

Charge Amplifiers DC

Voltage Amplifiers SF

Wire/bump bond pads

Wire/bump bond pads

Next iterations will have also:Gain eq. between columns, CDS, clustering ,data sparsification

nCTIQQ )1(0

Charge losses must be very small: CTI~0.0001 with n=2000 Q/Q0=82%

How to reduce CTI:•2-phase CCD (smaller V)•notch CCD –additional implant

(smaller V Q sees less traps)•fast CCD

(Q has no time to get trapped) – implementation field enhanced implants

•pre-injection of dark current to fill the traps•proper operational temperature

TRAPS - imperfections in Si crystal (capture charge during transfer)

Charge collection efficiency (generated charge clocked through the detector)

CTI denotes the loss of charge when shifted from one cell to

another

Problem of CCDs

radiation induced – radiation damage

CPCCD - Prototype performance

Previous prototype – off-shell 3 phase CCD driven at 50 MHz at –70 with pp 3V amplitudes

ADC 8.2

55Fe spectrum

Pros CP-CCD

•Proven technology – a lot of experience

•with low resistive epi-Si or PNP-CCD large effective thickness can be reached –

good for imaging

•large homogeneity of charge collection

•small pixel sizes of order (20x20 m2) – good spatial resolution < 5 m

Cons CP-CCD

•High costs and limited vendor choice ( only MTech is working on them )

•Radiation hardness is questionable (charge transfer over entire detector – CTI

degradation)

•detectors may need to be operated at lower temperatures

MAPS (CMOS imager)- principles of operation1

5 µ

m

• double-well CMOS process with epitaxial layer

• the charge generated by the impinging particle is reflected by the potential barriers due to doping differences and collected by thermal diffusion by the n-well/p-epi diode

•large charge spreading (signal shared over many pixels)

•“slow” charge collection (t~100 ns – depends on epi-Si)

• integration of the circuitry electronics on the same sensor substrate (1st stage of amplification)

•useable for detection off photons with few keV (limit set by epi-layer thickness)

through the center of N wellthrough the center of P well

fill factor = 100%

-no HV-operation voltage set by CMOS process

Relaxation of excess charge after particle passage

0 nsec

1 nsec

10 nsec

20 nsec

Particle track

If of the substrate is high significant contribution of diffused charge from substrate to

the total charge

0 nsec

1 nsec

10 nsec

20 nsec

MAPS - Readout

Collection (int. time=frame rate)

Output Reset…Reset (common row)

M2 gate potential

Simple readout scheme for the firstprototypes (5 up to now)•a reset cycle (all pixels) – common row reset•cell output is amplified - physical signal: two frames are read-out and subtracted – CDS

Last amplification stage common to all

Current prototype’s clock speed 40 MHz

At present prototypes only reset and clock signals are needed

Full analog information (all pixel) is read-out in series - slow

Signal/Noise ratio

for given event

CDS : get rid of FPN, reset noise, 1/f noise

MIMOSA 6 (being manufactured)• pixel pitch 28x28 m2 • 1 array 30x128 pixels – 29 transistors/pixel – instead of 3 New features:• columns read-out in parallel - max. clock freq.: 30 MHz (CP) • Also 2nd stage amplification and CDS done on-pixel!• ADC conversion done at the edge of columns• data sparsification integrated at the edge off the chip – zero suppression

Chip layout

Single pixel layout

AC coupling capacitor

Charge storage

capacitors

“Large” pixel size and deep submicron technology -> integration of high chip functionality

CP read out

6 clock cycles for row

~5-8 clock cycles will be needed for

processing the signal for each pixels in each

column

R/O parallel to the short side of the detector: for TESLA ~ 200 pixel (0.5 cm)/50s pixels

Analog and digital electronics

pixels

Analog and digital electronics

Analog and digital electronics

optimistic

less optimistic

Column read-out

Column read-out

10 cm

~1 cm

1st layer ladder read-out

chip size 1.73x1.73 cm2

Wafer view

MAPS – prototype performance5 prototypes build so far in different technologies (deep sub ), different

pixel sizes, clock frequencies and epilayer thicknesses

MIMOSA 5 – large size detector - standard 0.6 m CMOS of AMS with 14 m thick EPI layer (1014 cm-3), pixel 17x17 m2, well capacity > 10000 e

•First stitched ladders of few neighboring chips are produced (100 m between chips – can be reduced to 1 m – almost no dead area) • simple serial frame read-out – 150 Hz frame rate (full analog information read-out)• problem with fabrication yield!

Pixel read-out direction~10% of the total surface

max. CMOS die size 2x2 cm2

1 diode – 14.6 V/e- MIMOSA I CMOS 0.6 m

ENC = 14 e- @1.6 ms f. rate 1 diode rad. tol.– 22.9 V/e- IMOSA II CMOS 0.35 m ENC = 12 e- @0.8 ms f. rate

55Fe calibration

To large extent leakage current contribution(shorter frame rate should reduce noise to around 10e)

T=0oC

Large scale prototype test in pion beam

Pros MAPS

•low cost (production of 6 6” wafers for example 44000 Euros, 9 USD/cm2 is expected)

•standard CMOS process – profiting from huge progress in microelectronic industry:

convenient way of design - standard software tools, design kits and libraries, high yield, low

power consumption

•Radiation hardness – up to few 100 kRad less than 10% degradation in collected charge

•low noise due to small gate capacitance (few fF) – theoretically few e - few 10 e

•signal processing (1st and 2nd stage amplification) in each individual pixel is possible ->

good S/N at high speed

•homogeneity of charge collection >97%

•pixel sizes of order (25x25 m2) – could be limited by integration of large number of

transistors Cons MAPS

•limited epi-layer thickness and by that usability for detection of photons (deep sub

maybe no epi)

•requirement for 8 metal layers and also analog design rules for CMOS – not very easily

found

•potential danger of very deep sub-micron technology (trench isolation – charge trapping)

•p-channel JFET or MOSFET integrated on high-ohmic, sidewards-depleted, n-substrate

•a local potential minimum is formed by S/D potentials aided by a deep n implantation

(punch-through bias of the pixels)

• electrons are collected in an internal gate close to the surface (collection time few ns)

• the transistor channel current is modulated by charge collected in the internal gate

• the device can be switched on/off by an external (top) gate

DEPFET - Principles of operation

pulsed clear: pixel dead time < 1% of measuring time

Internal gate fills up with:•signal charges •thermally generated charges (leakage current)

    

random access to pixels !

DEPFET - Readout

DEPFET Column parallel read-out mechanism: •switch on one row through gate contacts and take pedestal current + signal current•reset the row •switch row on again and take pedestal current•subtract the signal-pedestal•repeat for all rows•do CDS

Now: 20 s – 50 kHzTESLA: 20 ns – 50 MHza very ambitious but achievable goalElectronics requirement

•Current read-out (@ drain)•Current memory cells

n x mpixel

IDRAIN

DEPFET- matrix

VGATE, OFF

off

off

on

off

VGATE, ON

gate

drain VCLEAR, OFF

off

off

reset

off

VCLEAR, ON

reset

output

0 suppression

VCLEAR-Control

Reset row i

Gate row i

Current of pixel i,j

sample Iped+Isig sample Iped

Using different readout scheme the frame read-out time can be reduced to as low as 10 s (100 kHz frame rate)

Drawback is larger power consumption:

expected noise < 100 e (at root temperature) with resolution of < 5m

current prototype

development: 128x128 pixels

array clocked at 50 MHz

DEPFET – prototype performance

DEPFET’s field of use – beside tracking in particle physics: •low energy X ray astronomy XEUS (0.1-30 keV sensitivity)•Medical imaging (autoradiography) - BIOSCOPE (64x64 pixel array of 50x50 m2)

single pixel device ENC=4-5 ematrix – 69 e (35oC)1 kHz frame rate - 50 kHz line

55Fe (6 keV) - 37 lp/mm ~ 6.7 m 109Cd (22 keV) - 57 lp/mm ~ 4.3 m

75 m tungsten plateImaged with sources

projections

6 threshold

Real time – space and energy resolution! (different markers can be separated)

Pros DEPFET

•low noise due to small gate capacitance (few 10 fF) – theoretically few e

•external amplification only in the 2. stage what leads to good signal/noise

•the thickness of the substrate can be large - higher efficiency for photons!

•Homogeneity of charge collection >95% (achieved with prototypes so far)

•pixel sizes of order (25x25 m2)

•Non-linearities < 0.1% within large dynamic range

•Radiation hard (deep submicron technology, rad-hard design rules) ?????

Drawback

•High cost (8 implantations, 15 masks, 200 technological steps)•less flexible – not suitable for any vendor

HAPS - Principles of operation

chip

sensor

•fast read-out (charge collection times of ns order)

•each pixel has its own read-out amplifier

•Detection of low-energy photons from the back – large thickness – up to 1 mm - can be depleted

•The read-out chip is mounted directly on top of the pixels (bump-bonding)

Problem is in assembly of pixel detector-hybrid: bump bonding – alignment

This limits the pixel detector resolution – minimal bump-bondable size – pixel area limited by the read-out chip!

Large pixel capacitance – higher noise

BUT…, no limit on read-out chip design

•possible to detect few keV photons from the back

p+

n+

n-

All major HEP experiments conceptAt LHC MHz frame rate – with noise around 200 e

Charge sensitive

preamplifiers

p+

n

PolyresistorInterleaved pixelReadout pixel readout pitch = n x pixel pitch

Large enough to house the

VLSI front-end cell

Small enough for an effective sampling and good spatial resolution

Charge carriers generated underneath one of the interleaved pixel cells induce a signal on the capacitively coupled read-out pixels, leading to a spatial accuracy improvement by a proper signal interpolation.

Silicon On Insulator (SOI) detector

Detector handle wafer

– High resistive

– 300 m thick

Electronics active layer

– Low resistive

– 1.5 m thick

Pixel detector with interleaved pixels

Detector: conventional p+-n, DC-coupled: Electronics: conventional bulk MOS technology

INSULATOR

SUCIMA

Interleaved

Readout

Max charge loss ~ 40%

In good agreement with estimated values for capacitive network

HAPS - Prototype performance

60 m

cell size = 100 m

The read-out pixels were wire bonded to the readout electronics

chip.

The BELLE experiment amplifiers and readout chain were used

880 nm laser used to determine CCE <80 m spot size – scan performed with 2D stage

Resolution between 3-10 m

Pros HAPS

•Proven technology – a lot of experience

•Very fast - up to few MHz frame rate

•good homogeneity of charge collection

•no problems with radiation hardness (can sustain 3 orders of magnitude larger doses

than others)

•large thickness can be depleted – good efficiency for photons

•Independent design of the read-out chip

Cons HAPS

•High cost (ATLAS and CMS estimation)

•Complicated assembly – alignment of hybrids and detectors

•higher noise (large pixel capacitance)

SUMMARYSUMMARY

There is a bright future for silicon in the field of particle detectors!

With new ideas coming and microelectronics industry growing

… sky is the limit