Fault-Tolerant Control Strategy for Neutral-Point …downloads.hindawi.com/journals/jcse/2018/5126404.pdfonly to open circuit fault and short circuit fault of outer switches. When

Research ArticleFault-Tolerant Control Strategy for Neutral-Point-ClampedThree-Level Inverter

Yanxia Shen Beibei Miao Dinghui Wu and Kader Ali Ibrahim

Engineering Research Center of Internet of Things Technology Applications of Ministry of Education Jiangnan UniversityWuxi 214122 China

Correspondence should be addressed to Yanxia Shen shenyxjiangnaneducn and Beibei Miao 6151920004vipjiangnaneducn

Received 15 September 2017 Accepted 31 December 2017 Published 1 February 2018

Academic Editor Ahmed Rhif

Copyright copy 2018 Yanxia Shen et al This is an open access article distributed under the Creative Commons Attribution Licensewhich permits unrestricted use distribution and reproduction in any medium provided the original work is properly cited

A fault-tolerant control technique is discussed for the Neutral-Point-Clamped (NPC) three-level inverter which ensures that theNPC inverter operates normally even under device failures A two-level leg is added to the NPC inverter when the device opencircuit fault occurs the load of this faulty phase is connected to the neutral point of this two-level leg through the bidirectionalthyristors An improved Space Vector Pulse Width Modulation (SVPWM) strategy called ldquoaddition and subtraction substitutionSVPWMrdquo is proposed to effectively suppress fluctuation in capacitor neutral-point voltages by readjusting the sequence and actiontime of voltage vectors The fault-tolerant topology in this paper has the advantages of fewer switching devices and lower circuitcosts Experimental results show that the proposed fault-tolerant system can operate in balance of capacitor neutral-point voltagesat full output power and the reliability of the inverter is greatly enhanced

1 Introduction

Compared with the conventional two-level inverters multi-level inverters have the advantages of lower voltage stressbetter waveform spectrum less voltage change rate andwaveform distortion [1ndash3] Therefore it is widely used invarious electric power conversion and power transmissionapplications such as inverter system low-voltage motordrives and wind power generation [4ndash6] However thereare many switching devices in multilevel inverters and thecontrol of these switches becomesmore complex which leadsto a significant increase in failure rate Then the reliability ofthe circuit is greatly deteriorated If the open fault is not dealtwith in time the voltage stress of certain switch will increaseowing to the fluctuation of capacitor neutral-point voltagesWhat is worse the entire circuit operates abnormally causingserious accidents or incalculable economic losses [7ndash9] Insome applications higher reliability of the circuit is requiredthat it is even expected that the circuit should keep workingfor a period under the device failures So in recent years theresearch of fault-tolerant control for multilevel inverters hasattracted wide attention from scholars [10ndash12]

For three-level inverters there are a variety of fault-tolerant control methods The fault-tolerant control of theActive Neutral-Point-Clamped (ANPC) inverter using theredundant switching states has been proposed in [13] Theinverter can operate in balance of capacitor neutral-pointvoltages with symmetrical three-phase output after the pro-posed fault-tolerant control method is applied Howeverthe amplitude of output voltage and current are greatlydecreased A load-type fault-tolerant solution of the ANPCinverter has been proposed in [14 15] The basic idea ofthis method is to keep the faulty leg at O level which isachieved by connecting the faulty leg to the neutral pointof the DC-link capacitor Similarly the inverter can onlyoperate at reduced rated power The fault-tolerant of half-bridge switches and neutral-point switches in T-type inverterhas been proposed in [16 17]The redundant switching statesare used to synthesize the reference vector of the rotationalvoltage in SVPWM algorithm which enables the inverterto operate normally in the fault condition However forthe open fault of half-bridge switches the DC-link voltageutilization ratio is half of this inverter The fault-tolerantcontrol of the T-type inverter using the additional leg has

HindawiJournal of Control Science and EngineeringVolume 2018 Article ID 5126404 9 pageshttpsdoiorg10115520185126404

2 Journal of Control Science and Engineering

Ud

D6

D5

D10

D11

D12

D17

D18

D1

D2

D3

D4

D7

D8 D14

D13

D15

D16

D9

A

CB

N

QA3

QA1

QA2

QA4

C1

C2

O

QB1 QC1

QB2

QB3

QC4QB4

QC2

QC3

V＄1

V＄2

+

minus

Figure 1 The main circuit of NPC three-level inverter

been proposed in [18] The one-phase bridge of the T-type inverter is used as the additional leg Once a fault isdetected the faulty phase is connected to the additional legby the corresponding bidirectional thyristors The invertercan output the full-rated power in any fault conditionwith higher manufacturing costs and larger size and weightThe eight-switch three-phase inverters (ESTPIs) reconfiguredtopologies for the NPC inverter have been proposed in [19]When the device open circuit fault occurs the correspondingbidirectional thyristors of the faulty leg is triggered andthe faulty leg is connected to the neutral point of the DC-link capacitor However the inverter can only operate athalf output power also the amplitude of the output voltageis decreased by half The fault-tolerant control of the NPCinverter using the asymmetric leg has been proposed in[20] The faulty leg is isolated by the bidirectional thyristorsunder device failures and an asymmetric two-level leg isadded to the inverter To eliminate the low-order harmoniccomponent of the output phase voltages the bipolar Sinu-soidal Pulse Width Modulation (SPWM) method is usedto control the asymmetric leg The inverter can operate inbalance of three phasesrsquo output without reducing the outputpower of the original circuit A software redundancy fault-tolerant control algorithm of the NPC inverter has beenproposed in [21] This method is implemented by using theredundant voltage vectors with some limitations that applyonly to open circuit fault and short circuit fault of outerswitches

When the open circuit fault of inner switches occursin the NPC three-level inverter some voltage vectors arelost and the synthesis of the possible voltage vectors forreference voltage cannot be implemented Consequently the

reconfiguration of the circuit is required for fault-tolerantcontrol In order to ensure the NPC inverter can outputthe full-rated power under device failures a two-level legserves as the additional leg for the faulty phase in thispaper When the open circuit fault occurs in the NPCinverter the faulty leg is connected to the additional legthrough the bidirectional thyristors Both the switching statesP and N generated by modifying the SVPWM algorithmare employed to control the additional leg In addition inorder to accurately suppress the fluctuation of the capacitorneutral-point voltages an improved SVPWM strategy calledldquoaddition and subtraction substitution SVPWMrdquo is proposedto readjust the sequence and action time of voltage vectors inSVPWM algorithm

2 Description of NPC Inverter

Figure 1 shows the main circuit of NPC three-level inverterThere are three switching states for each leg [22] namelyP O and N For instance the relation between switch-ing states and switching sequence of phase A is listed inTable 1

In Table 1 ldquo1rdquo indicates that the power device is turnedon and ldquo0rdquo indicates turn-off The symbol ldquo+rdquo representsthe current flows from the power supply to the load on thecontrary the symbol ldquominusrdquo represents the current flows fromthe load to the power supply

It can be known from Figure 2 that the NPC inverter has27 combinations of switching states that correspond to 27space voltage vectors divided into four classes according totheir magnitudes namely zero- small- medium- and large-voltage vectors [23 24]

Journal of Control Science and Engineering 3

Table 1 Switching states in NPC three-level inverter

Switching states Switching sequenceQA1 QA2 QA3 QA4 D1 D2 D3 D4 D5 D6

P+ 1 1 0 0 0 0 0 0 0 0

Pminus 0 0 0 0 1 1 0 0 0 0

O+ 0 1 0 0 0 0 0 0 1 0

Ominus 0 0 1 0 0 0 0 0 0 1

N+ 0 0 0 0 0 0 1 1 0 0

Nminus 0 0 1 1 0 0 0 0 0 0

I

II

III

IV

V

VI

PPNOPNNPN

NPO

NPP

NOP

NNPONP PNP

PNO

PNN

PONPPO

OON

POOONN

POPONO

OOPNNO

OPPNOO

OPONON

PPPOOONNN

U lt 0

U = 0

U gt 0

Figure 2 Voltage vector distribution of NPC three-level inverter

3 Effect of the Switching States onNeutral-Point Voltages

When the open circuit fault occurs in NPC three-levelinverter the absence of the switching states leads to thechange in the current flow paths Consequently an undesir-able bridge arm phase voltage is generated which can bringout the distortion of the load phase current resulting inthe fluctuation of the capacitor neutral-point voltages Theanalysis is illustrated with QA1 and QA2 single-switch faultof phase AThe direction of the current flows from the powersupply to the load is defined as the positive direction 119868119886 gt 0

(1) QA1 Fault The current can only flow through the switchQA2 and the diode D5 to the load under the switch QA1fault while the inverter operates in the P state and the current119868119886 gt 0 The load is connected to the neutral point of DCside and the inverter operates in the O state as shown inFigure 3(a)The solid line represents that the inverter operatesnormally whereas the dotted line denotes the inverter underthe QA1 fault condition The bridge arm phase voltage variesfrom +12119880119889 to zero which causes the distortion of loadphase current Under these circumstances all voltage vectorsthat start with ldquoPrdquo are undesirable including small-voltage

vectors [PPO] [POO] and [POP] medium-voltage vectors[PON] and [PNO] and large-voltage vectors [PNN] [PPN]and [PNP] as shown in Figure 4(a)These impossible voltagevectors are replaced by the voltage vectors enclosed withbrackets that start with ldquoOrdquo conversely the voltage vectorsthat start with ldquoOrdquo or ldquoNrdquo state in phase A are desirablebecause the QA1 fault has no effect on them That is thenumber of the current branches flowing to load from theneutral point of DC side is more than that in the normal stateTherefore the upper capacitor voltage119881DC1 is greater than thelower capacitor voltage 119881DC2

(2) QA2 Fault As illustrated in Figure 3(a) one condition isthat theQA2 fault occurs in the case that the inverter operatesin the P state and the current 119868119886 gt 0 the current flowsthrough the diodes D3 and D4 to the load and the inverteroperates in the N state This condition brings out the changein the magnitude of bridge arm phase voltage and currentThe other one is that the inverter operates in the O state andthe current 119868119886 gt 0 In the same way the current flows throughthe diodes D3 and D4 to load and the switching state is Nas shown in Figure 3(b) The solid line means the inverterin the normal state and the dotted line indicates the inverterunder the QA2 fault conditionThus it can be observed fromFigure 4(b) that all voltage vectors beginning with ldquoPrdquo andldquoOrdquo are crossed out and these voltage vectors are replaced bythe voltage vectors beginning with ldquoNrdquo the number of thecurrent branches flowing to load from the neutral point ofDC side is less than that in the normal state Similarly it canbe derived that 119881DC2 is greater than 119881DC1

In summary the device open circuit fault can causeunbalance of the capacitor neutral-point voltages in the NPCinverter

4 Fault-Tolerant Topology andWorking Principle

As shown in Figure 4 when theQA1 open circuit fault occursthe equivalent stator flux circle can still be synthesized byadjusting the sequence of the available voltage vectors basedon vector superposition theorem but the voltage utilizationratio is half In contrast the inverter has no fault toleranceability in case of the QA2 fault because there is no redundantvoltage vectors to synthesize the stator flux circle in the area119880AN gt 0 Therefore in order to enable the NPC inverterto operate at full output power under the device failures a


Ud

D6

D5

D1

D2

D3

D4

A

N

QA3

QA1

QA2

QA4

C1

C2

O

B C

V＄1

V＄2

+

minus

(a)

Ud

D6

D5

D1

D2

D3

D4

A

N

QA3

QA1

QA2

QA4

C1

C2

O

B C

V＄1

V＄2

+

minus

(b)

Figure 3 Change of current paths under open circuit fault (a) QA1 fault (b) QA2 fault

I

II

III

IV

V

VI

PPNOPNNPN

NPO

NPP

NOP

NNPONP PNP

PNO

PNN

PONPPO[OON]

POO[ONN]

POP[ONO]

OOPNNO

OPPNOO

OPONON

PPPOOONNN

U lt 0

U = 0

U gt 0

(a)

I

II

III

IV

V

VI

PPNOPNNPN

NPO

NPP

NOP

NNPONP PNP

PNO

PNN

PONPPOOON

POOONN

POPONO

OOP[NNO]

OPP

[NOO]

OPO[NON]

PPPOOONNN

U lt 0

U = 0

U gt 0

(b)

Figure 4 Voltage vector distribution under device open fault of phase A (a) QA1 fault (b) QA2 fault

two-level leg is added to the main circuit of the NPC three-level inverter which consists of two switches Q1 and Q2 andcorresponding antiparallel diodes D19 and D20 In additionsix bidirectional thyristors Trx1 and Trx2 (119909 = 119886 119887 and 119888)are used to constitute the fault-tolerant topology of the NPCinverter as shown in Figure 5

When the NPC inverter operates normally Trx1 (119909 =119886 119887 and 119888) are connected and Trx2 (119909 = 119886 119887 and 119888)are disconnected If the open fault of phase A occurs thefaulty phase is isolated by Tra1 and the midpoint O1015840 ofthis two-level leg is connected to load of the faulty phasethroughTra2 Both the switching states P andN generated bymodifying the SVPWM algorithm are aimed at controlling

the two switches Q1 and Q2 of this two-level leg Obviouslythe O state is not available It is essential to readjust thesequence and action time of voltage vectors In general theproposed reconfiguration topology canmaintain the neutral-point voltages balance and operate at full output power underany fault condition

5 SVPWM Strategy of Addition andSubtraction Substitution

After the fault reconstruction topology is adopted differentvoltage vector distribution can be obtained as illustrated inFigure 6


Ud

D6

D5

D10

D11

D12

D17

D18

D1

D2

D3

D4

D7

D8 D14

D13

D15

D16

D9

C1 +

+C2

O

D19

D20

Q1

Q2

N

Tra2

Trb2

Trc2

Tra1 Trb1 Trc1

QA2

QA3

QA4

QB1

QB2

QB3

QB4

QC1

QC2

QC3

QC4

A B C

QA1

+

minus

O

Figure 5 Fault-tolerant topology of NPC inverter

Table 2 Substitution law of voltage vectors

Region Voltage vectorsI [OOO]rarr [PPP] N-typerarr P-typeII-1 3 5 [OOO]rarr [PPP] N-typerarr P-type [OPN]rarr [PPO]+ [NON]II-2 4 6 [OOO]rarr [NNN] P-typerarr N-type [OPN]rarr [PPO]+ [NON]III [OOO]rarr [NNN] P-typerarr N-typeIV [OOO]rarr [NNN] P-typerarr N-typeV-1 3 5 [OOO]rarr [NNN] P-typerarr N-type [ONP]rarr [POP]+ [NNO]V-2 4 6 [OOO]rarr [PPP] N-typerarr P-type [OPN]rarr [POP]+ [NNO]VI [OOO]rarr [PPP] N-typerarr P-type

The equivalent stator flux circle can still be synthe-sized by adjusting the sequence of the available voltagevectors and the inverter can output the full-rated power Animproved SVPWM strategy called ldquoaddition and subtractionsubstitution SVPWMrdquo is proposed to effectively suppressthe fluctuation of the capacitor neutral-point voltages Thefault-tolerant control of NPC inverters is carried out byadjusting the sequence and operation time of voltage vectorsThe research is conducted only taking phase-A fault as anexample

If the phase-A fault occurs the faulty phase A is replacedwith a two-level leg which is controlled by the switchingstates P and N Therefore the switching states that startwith ldquoOrdquo are prohibited as shown in Figure 6 and theseundesirable voltage vectors should be replaced by othervoltage vectors of the same size Namely N-type voltagevectors ([OON] [ONN] and [ONO]) in the regions I II-1 II-3 II-5 and VI are replaced respectively with P-type

voltage vectors ([PPO] [POO] and [POP]) For the purposeof restraining the fluctuation of the capacitor neutral-pointvoltages effectively P-type voltage vectors ([OPO] [OPP]and [OOP]) in the opposite regions IV V-1 V-3 V-5 andIII should be replaced respectively with N-type voltagevectors ([NON] [NOO] and [NNO]) However there areno redundant voltage vectors in the medium-voltage vectors([OPN] and [ONP]) in regions II and V In this paper themedium-voltage vectors are replaced by the small-voltagevectors adjacent to them Table 2 presents the substitution lawof voltage vectors in each region

ldquoAddition and subtraction substitution SVPWMrdquo is sim-ply defined by adding or subtracting a minimum action time(119879low) to the three-phase action times (119879119886 119879119887 and 119879119888) torealize the substitution of voltage vectors in the SVPWMalgorithm The sequence and action time of voltage vectorsare adjusted by replacing the undesirable voltage vectors withthe remaining voltage vectors of the same size where 119879low


Table 3 The sequence and action time of voltage vectors in each region

Region Switching sequence Action timeI-1 POO-PPO-PPP-PPP-PPO-POO 119872

I-2 POO-PPO-PPP-PPP-PPO-POO 1198721

I-3 PON-POO-PPO-PPO-POO-PON 1198721


I-5 PNN-PON-POO-POO-PON-PNN 1198722

I-6 PON-PPN-PPO-PPO-PPN-PON 1198722

IV-1 NNN-NNO-NOO-NOO-NN0-NNN 1198722


IV-3 NNO-NOO-NOP-NOP-NOO-NNO 1198721


IV-5 NOO-NOP-NPP-NPP-NOP-NOO 119872

IV-6 NNO-NNP-NOP-NOP-NNP-NNO 119872

I

II

III

IV

V

VI

PPNOPNNPN

NPO

NPP

NOP

NNPONP PNP

PNO

PNN

PONPPOOON

POOONN

POPONO

OOPNNO

OPP

NOO

OPONON

OOONNN

PPP

1

23

4

6

12

3456

1 2

3 45 6

5

Ia lt 0 Ia gt 0U = 0

Figure 6 Voltage vector distribution after the fault tolerance

Table 4 Experimental parameters

Dc-link voltage 400VFundamental frequency 119891119899 = 50HzSwitching frequency 119891119896 = 3 kHzSampling time 119879 = 1119890 minus 4

Neutral capacitance 1198621 = 1198622 = 0008 FRL load 4Ω3mH

represents the minimum value among 119879119886 119879119887 and 119879119888 In thismethod the N-type voltage vectors can be substitute for theP-type voltage vectors after 119879low is added to 119879119886 119879119887 and 119879119888 Incontrast the P-type voltage vectors take the place of the N-type voltage vectors by subtracting 119879low to 119879119886 119879119887 and 119879119888 Theprocess will be explained in two regions I-1 and III-2

The sequence and action time of voltage vectors in regionI-1 in the normal state are shown in Figure 7(a) The unde-sirable N-type voltage vectors [ONN] should be replaced bythe P-type voltage vectors [POO] and this process is achieved

by subtracting 119879low in three-phase action times (119879119886 119879119887 and119879119888) as shown in Figure 7(b) where 119879low is 119879119887 Similarlythe impossible voltage vectors [OON] and [OOO] shouldbe changed to [PPO] and [PPP] Finally according to theprinciple that the switching states can only be changed onceor unchanged the redefined sequence and action time ofvoltage vectors should be rearranged as shown in Figure 7(c)

The sequence and action time of voltage vectors in regionIII-2 in the normal state is shown in Figure 8(a) In orderto replace the impossible P-type voltage vectors [OPO] withN-type voltage vectors [NON] 119879low is added in three-phaseaction times (119879119886 119879119887 and 119879119888) where 119879low is 119879119888 The redefinedsequence and action time of voltage vectors can be obtainedas given in Figure 8(b)Therefore the redefined sequence andaction time of voltage vectors in each region listed in Table 3can be summed up

119872 =1198791

21198792

21198793

21198793

21198792

21198791

2

1198721 =1198793

21198791

21198792

21198792

21198791

21198793

2

1198722 =1198792

21198793

21198791

21198791

21198793

21198792

2

(1)

119872 1198721 and 1198722 represent the action time of voltagevectors corresponding to the different switching sequence

6 Experiment Verification

In order to validate the improved SVPWM strategy proposedpreviously a laboratory prototype of the NPC three-levelinverter with fault-tolerant capability is built based on thedSPACE DS1007 platform as shown in Figure 9 The mainexperimental parameters are listed in Table 4 Figure 9 showsthe overall structure of the experimental platform includingNPC inverter three-phase load DS1007 and PC The mainboards used in the experiment are DS5202 and ACMC (ACMotor Control) DS5202 provides 8 channels with maximumsampling frequency of 10MHz and EV1048 not only can be


A

B

C

ONN OOO OOOPOOOON OON ONNTa

Tb

Tc

T1

4

T2

2

T3

2

T1

2

T3

2

T2

2

T1

4

(a)

A

B

C

OOO OOOPOOOON OONPOO

T2

2

T3

2

T1

2

T1

2

T3

2

T2

2

(b)

A

B

C

PPO PPOPPPPOO POOPPP

T1

2

T2

2

T3

2

T3

2

T2

2

T1

2

(c)

Figure 7The sequence of voltage vectors and its action times in region I-1 (a) Conventional switching sequence (b) After 119879low is subtracted(c) After the switching sequence is rearranged

A

B

C

NON NPO NPOOPONOO NOO NON

T1

4

T2

2

T3

2

T1

2

T3

2

T2

2

T1

4

Ta

Tb

Tc

(a)

A

B

C

NOO NOONPONON NONNPO

T1

2

T2

2

T3

2

T3

2

T2

2

T1

2

(b)

Figure 8 The sequence of voltage vectors and its action times in region III-2 (a) Conventional switching sequence (b) After the switchingsequence is rearranged

DS5202 ACMC (EV1048)DS1007

RTW RTI Control desk

PC

Drive ampprotectioncircuit

NPC inverter

PWM generator

R-L load

Signalprocessing

AD channels DA channels

Oscilloscope

Figure 9 Experimental structure diagram

used for AD sampling but also generate PWM signal to drivethe inverter circuit In the experiment the QA1 open fault isset up and fault-tolerant control is carried out

Figure 10 shows the different experimental waveformsof the output voltages current and capacitor neutral-pointvoltages without and with fault-tolerant control in sequenceThe waveforms of phase-A bridge arm phase voltage 119880119886119900 andline-to-line voltage119880119886119887 are given in Figure 10(a) respectivelyIt can be observed from Figure 10(a) that the phase voltage119880119886119900 exhibits three levels and the line-to-line voltage 119880119886119887shows five levels under the normal condition When the faultoccurs the amplitude of the phase voltage119880119886119900 in positive halfperiod is decreased from +12119880119889 to zero and a zero levelappeared for a long time Similarly the amplitude of line-to-line voltage 119880119886119887 in positive half period is lower than that ofthe normal conditionThe voltage waveforms are the same asthat under the normal condition when the proposed methodis adopted for fault-tolerant control namely119880119886119900 is three-levelwaveform with constant output amplitude and 119880119886119887 is five-level waveform with constant output amplitude

Figure 10(b) shows the waveforms of current 119868119886 in phase-A without and with fault-tolerant control respectively It can


Fault-tolerant control

The fault occurs

Uao (V)

Uab (V)

200６

grid

500６

grid

10ＧＭgrid t (ms)

(a)

The fault occurs Fault-tolerant control

Ia (A)

1

grid

10ＧＭgrid t (ms)

(b)

The fault occurs

V＄ (V)

100６

grid

t (ms)500ＧＭgrid

V＄1

V＄2

(c)


V＄ (V)

100６

grid

t (ms)500ＧＭgrid

V＄1

V＄2

(d)

Figure 10 Experimental waveforms (a) 119880119886119900 and 119880119886119887 (b) 119868119886 (c) Capacitor neutral-point voltages before fault-tolerant control (d) Capacitorneutral-point voltages after fault-tolerant control

be seen from Figure 10(b) that the current 119868119886 is sinusoidalbefore the fault occurs but when the fault occurs theamplitude of the load phase current 119868119886 in positive half periodis approximately reduced to half of the normal conditionand the waveform is obviously distorted The load phasecurrent 119868119886 is still sinusoidal with constant amplitude after theproposed fault-tolerant method is applied and the invertercan operate normally

Figures 10(c) and 10(d) show the capacitor neutral-pointvoltages without and with fault-tolerant control respectivelyAs shown in Figure 10(c) when the fault occurs the neutral-point voltage of the capacitor fluctuates obviously and119881DC1 gt119881DC2 The fluctuation of the neutral-point voltage of thecapacitor is well suppressed by the fault-tolerant control asshown in Figure 10(d) Obviously the correctness of the fault-tolerant strategy is proved by experiments

7 Conclusion

In order to enable the NPC inverter to operate at full outputpower under the device failures a two-level leg is taken as theadditional leg of the faulty phase in this paper which is con-trolled with the two switching states P and N In addition an

improved SVPWM strategy called ldquoaddition and subtractionsubstitution SVPWMrdquo is proposed to readjust the sequenceand action time of voltage vectors in SVPWM algorithmThe main advantages of the proposed fault-tolerant SVPWMstrategy include the following

(1)Theproposed fault-tolerant topology has fewer switch-ing devices and lower costs

(2)The inverter is operated continuously without reducedoutput power by the proposed method Therefore the pro-posed fault-tolerant SVPWM strategy can be applied for allkinds of applications

(3) The distortion of capacitor neutral-point voltages iseliminated well after the proposed fault-tolerant method isapplied

(4) The two switches Q1 and Q2 of this two-level legshould withstand the entire input DC voltage after fault-tolerant control Therefore the proposed method is moresuitable for the NPC inverter with medium- or low-voltagepower supply

The effectiveness and fault-tolerant operation of the pro-posed SVPWMstrategy are demonstrated by both simulationand experimental results under various types of faults


Conflicts of Interest

The authors declare that they have no conflicts of interestregarding the publication of this paper

Acknowledgments

This work is supported in part by the National NaturalScience Foundation of China (61573167 and 61572237) Theauthors appreciate the support of the Priority Academic Pro-gram Development of Jiangsu Higher Education Institutionsas well as The Research Innovation Program for CollegeGraduates of Jiangsu Province SJLX16 0107

References

[1] T Wang H Xu J Han E Elbouchikhi and M E H Ben-bouzid ldquoCascaded H-bridge multilevel inverter system faultdiagnosis using a PCA andmulticlass relevance vector machineapproachrdquo IEEE Transactions on Power Electronics vol 30 no12 pp 7006ndash7018 2015

[2] J He N A O Demerdash N Weise and R Katebi ldquoA faston-line diagnostic method for open-circuit switch faults in SiC-MOSFET-based T-type multilevel invertersrdquo IEEE Transactionson Industry Applications vol 53 no 3 pp 2948ndash2958 2017

[3] U-M Choi H-G Jeong K-B Lee and F Blaabjerg ldquoMethodfor detecting an open-switch fault in a grid-connected NPCinverter systemrdquo IEEE Transactions on Power Electronics vol27 no 6 pp 2726ndash2739 2012

[4] K Ma and F Blaabjerg ldquoModulation methods for neutral-point-clamped wind power converter achieving loss andthermal redistribution under low-voltage ride-throughrdquo IEEETransactions on Industrial Electronics vol 61 no 2 pp 835ndash8452014

[5] M Schweizer and J W Kolar ldquoDesign and implementation ofa highly efficient three-level T-type converter for low-voltageapplicationsrdquo IEEE Transactions on Power Electronics vol 28no 2 pp 899ndash907 2013

[6] O S Senturk S Munk-Nielsen R Teodorescu L Helleand P Rodriguez ldquoPower density investigations for the largewind turbinesrsquo grid-side press-pack IGBT 3L-NPC-VSCsrdquo inProceedings of the 4th Annual IEEE Energy Conversion Congressand Exposition (ECCE rsquo12) pp 731ndash738 IEEE Raleigh NCUSA September 2012

[7] J-S Lee and K-B Lee ldquoAn open-switch fault detection methodand tolerance controls based on SVM in a grid-connected t-type rectifier with unity power factorrdquo IEEE Transactions onIndustrial Electronics vol 61 no 12 pp 7092ndash7104 2014

[8] D J Chen Y Z Ye and R Hua ldquoFault diagnosis of three levelinverter in bullet train based on waveform real-time analysisrdquoTransactions of China Electrotechnical Society vol 29 no 6 pp106ndash113 2014

[9] S Yang D Xiang A Bryant P Mawby L Ran and P TavnerldquoConditionmonitoring for device reliability in power electronicconverters A reviewrdquo IEEE Transactions on Power Electronicsvol 25 no 11 pp 2734ndash2752 2010

[10] L L Jiang W Z Ma and L H Li ldquoFault tolerant control strat-egy for modular multilevel convertersrdquo Power System sourcevol 38 no 9 pp 2497ndash2503 2014

[11] J Amini and M Moallem ldquoA fault-diagnosis and fault-tolerantcontrol scheme for flying capacitor multilevel invertersrdquo IEEE

Transactions on Industrial Electronics vol 64 no 3 pp 1818ndash1826 2017

[12] S Ceballos J Pou J Zaragoza E Robles J L Villate andJ L Martın ldquoFault-tolerant neutral-point-clamped convertersolutions based on including a fourth resonant legrdquo IEEETransactions on Industrial Electronics vol 58 no 6 pp 2293ndash2303 2011

[13] J Li A Q Huang Z Liang and S Bhattacharya ldquoAnalysisand design of active NPC (ANPC) inverters for fault-tolerantoperation of high-power electrical drivesrdquo IEEETransactions onPower Electronics vol 27 no 2 pp 519ndash533 2012

[14] Z Wang B Zhang Y Wang Y Zhang and M Cheng ldquoAnal-ysis and control of active neutral-point-clamping three-levelinverters under fault tolerant operation modesrdquo in Proceedingsof the 18th International Conference on Electrical Machines andSystems (ICEMS rsquo15) pp 2140ndash2146 PattayaThailand October2015

[15] A I L de Lacerda and E R C da Silva ldquoFault tolerantActive Neutral Point Clamped inverter short-circuit and open-circuit failuresrdquo in Proceedings of the 24th IEEE InternationalSymposium on Industrial Electronics (ISIE rsquo15) pp 1068ndash1073Rio de Janeiro Brazil June 2015

[16] U-M Choi F Blaabjerg and K-B Lee ldquoReliability improve-ment of a T-type three-level inverter with fault-tolerant controlstrategyrdquo IEEE Transactions on Power Electronics vol 30 no 5pp 2660ndash2673 2015

[17] U-M Choi K-B Lee and F Blaabjerg ldquoDiagnosis and tolerantstrategy of an open-switch fault for t-type three-level invertersystemsrdquo IEEE Transactions on Industry Applications vol 50no 1 pp 495ndash508 2014

[18] S Xu J Zhang and J Hang ldquoInvestigation of a fault-tolerantthree-level T-type inverter systemrdquo in Proceedings of the 7thAnnual IEEEEnergy ConversionCongress and Exposition (ECCErsquo15) pp 1632ndash1638 Montreal Canada September 2015

[19] Y C Liu X L Ge and X Y Feng ldquoResearch on the comparisonof SVPWMalgorithm for two level and three level NPC invertersingle bridge fault reconfiguration topologyrdquo Proceedings of theCSEE vol 36 no 3 pp 775ndash783 2016

[20] D J Chen Y Z Ye and R Hua ldquoResearch on Fault TolerantTopology and control of NPC three level inverterrdquo ControlEngineering of China vol 21 no 2 pp 258ndash267 2014

[21] D B Matos J O Estima and A J M Cardoso ldquoPerformanceof a synchronous reluctance motor drive with a fault-tolerantthree-level neutral point clamped inverterrdquo in Proceedings ofthe 22nd International Conference on Electrical Machines (ICEMrsquo16) pp 1152ndash1159 Lausanne Switzerland September 2016

[22] J-S Lee K-B Lee and F Blaabjerg ldquoOpen-switch fault detec-tion method of a back-to-back converter using NPC topologyfor wind turbine systemsrdquo IEEE Transactions on IndustryApplications vol 51 no 1 pp 325ndash335 2015

[23] Z Wang Y Z Wang J Chen and M Cheng ldquoFault-TolerantControl ofNPC three-level inverters-fed double-stator-windingPMSM drives based on vector space decompositionrdquo IEEETransactions on Industrial Electronics vol 64 no 11 pp 8446ndash8458 2017

[24] U-M Choi andK B Lee ldquoSpace vectormodulation strategy forneutral-point voltage balancing in three-level inverter systemsrdquoIET Power Electronics vol 6 no 7 pp 1390ndash1398 2013

International Journal of

AerospaceEngineeringHindawiwwwhindawicom Volume 2018

RoboticsJournal of

Hindawiwwwhindawicom Volume 2018


Active and Passive Electronic Components

VLSI Design



Shock and Vibration


Civil EngineeringAdvances in

Acoustics and VibrationAdvances in



Electrical and Computer Engineering

Journal of

Advances inOptoElectronics

Hindawiwwwhindawicom

Volume 2018

Hindawi Publishing Corporation httpwwwhindawicom Volume 2013Hindawiwwwhindawicom

The Scientific World Journal

Volume 2018

Control Scienceand Engineering

Journal of



Journal ofEngineeringVolume 2018

SensorsJournal of



RotatingMachinery


Modelling ampSimulationin EngineeringHindawiwwwhindawicom Volume 2018


Chemical EngineeringInternational Journal of Antennas and

Propagation




Navigation and Observation


Hindawi

wwwhindawicom Volume 2018

Advances in

Multimedia

Submit your manuscripts atwwwhindawicom


Ud

D6

D5

D10

D11

D12

D17

D18

D1

D2

D3

D4

D7

D8 D14

D13

D15

D16

D9

A

CB

N

QA3

QA1

QA2

QA4

C1

C2

O

QB1 QC1

QB2

QB3

QC4QB4

QC2

QC3

V＄1

V＄2

+

minus

Figure 1 The main circuit of NPC three-level inverter

been proposed in [18] The one-phase bridge of the T-type inverter is used as the additional leg Once a fault isdetected the faulty phase is connected to the additional legby the corresponding bidirectional thyristors The invertercan output the full-rated power in any fault conditionwith higher manufacturing costs and larger size and weightThe eight-switch three-phase inverters (ESTPIs) reconfiguredtopologies for the NPC inverter have been proposed in [19]When the device open circuit fault occurs the correspondingbidirectional thyristors of the faulty leg is triggered andthe faulty leg is connected to the neutral point of the DC-link capacitor However the inverter can only operate athalf output power also the amplitude of the output voltageis decreased by half The fault-tolerant control of the NPCinverter using the asymmetric leg has been proposed in[20] The faulty leg is isolated by the bidirectional thyristorsunder device failures and an asymmetric two-level leg isadded to the inverter To eliminate the low-order harmoniccomponent of the output phase voltages the bipolar Sinu-soidal Pulse Width Modulation (SPWM) method is usedto control the asymmetric leg The inverter can operate inbalance of three phasesrsquo output without reducing the outputpower of the original circuit A software redundancy fault-tolerant control algorithm of the NPC inverter has beenproposed in [21] This method is implemented by using theredundant voltage vectors with some limitations that applyonly to open circuit fault and short circuit fault of outerswitches

When the open circuit fault of inner switches occursin the NPC three-level inverter some voltage vectors arelost and the synthesis of the possible voltage vectors forreference voltage cannot be implemented Consequently the

reconfiguration of the circuit is required for fault-tolerantcontrol In order to ensure the NPC inverter can outputthe full-rated power under device failures a two-level legserves as the additional leg for the faulty phase in thispaper When the open circuit fault occurs in the NPCinverter the faulty leg is connected to the additional legthrough the bidirectional thyristors Both the switching statesP and N generated by modifying the SVPWM algorithmare employed to control the additional leg In addition inorder to accurately suppress the fluctuation of the capacitorneutral-point voltages an improved SVPWM strategy calledldquoaddition and subtraction substitution SVPWMrdquo is proposedto readjust the sequence and action time of voltage vectors inSVPWM algorithm

2 Description of NPC Inverter

Figure 1 shows the main circuit of NPC three-level inverterThere are three switching states for each leg [22] namelyP O and N For instance the relation between switch-ing states and switching sequence of phase A is listed inTable 1

In Table 1 ldquo1rdquo indicates that the power device is turnedon and ldquo0rdquo indicates turn-off The symbol ldquo+rdquo representsthe current flows from the power supply to the load on thecontrary the symbol ldquominusrdquo represents the current flows fromthe load to the power supply

It can be known from Figure 2 that the NPC inverter has27 combinations of switching states that correspond to 27space voltage vectors divided into four classes according totheir magnitudes namely zero- small- medium- and large-voltage vectors [23 24]




P+ 1 1 0 0 0 0 0 0 0 0

Pminus 0 0 0 0 1 1 0 0 0 0

O+ 0 1 0 0 0 0 0 0 1 0

Ominus 0 0 1 0 0 0 0 0 0 1

N+ 0 0 0 0 0 0 1 1 0 0

Nminus 0 0 1 1 0 0 0 0 0 0

I

II

III

IV

V

VI

PPNOPNNPN

NPO

NPP

NOP

NNPONP PNP

PNO

PNN

PONPPO

OON

POOONN

POPONO

OOPNNO

OPPNOO

OPONON

PPPOOONNN

U lt 0

U = 0

U gt 0











Ud

D6

D5

D1

D2

D3

D4

A

N

QA3

QA1

QA2

QA4

C1

C2

O

B C

V＄1

V＄2

+

minus

(a)

Ud

D6

D5

D1

D2

D3

D4

A

N

QA3

QA1

QA2

QA4

C1

C2

O

B C

V＄1

V＄2

+

minus

(b)


I

II

III

IV

V

VI

PPNOPNNPN

NPO

NPP

NOP

NNPONP PNP

PNO

PNN

PONPPO[OON]

POO[ONN]

POP[ONO]

OOPNNO

OPPNOO

OPONON

PPPOOONNN

U lt 0

U = 0

U gt 0

(a)

I

II

III

IV

V

VI

PPNOPNNPN

NPO

NPP

NOP

NNPONP PNP

PNO

PNN

PONPPOOON

POOONN

POPONO

OOP[NNO]

OPP

[NOO]

OPO[NON]

PPPOOONNN

U lt 0

U = 0

U gt 0

(b)








Ud

D6

D5

D10

D11

D12

D17

D18

D1

D2

D3

D4

D7

D8 D14

D13

D15

D16

D9

C1 +

+C2

O

D19

D20

Q1

Q2

N

Tra2

Trb2

Trc2

Tra1 Trb1 Trc1

QA2

QA3

QA4

QB1

QB2

QB3

QB4

QC1

QC2

QC3

QC4

A B C

QA1

+

minus

O






















I

II

III

IV

V

VI

PPNOPNNPN

NPO

NPP

NOP

NNPONP PNP

PNO

PNN

PONPPOOON

POOONN

POPONO

OOPNNO

OPP

NOO

OPONON

OOONNN

PPP

1

23

4

6

12

3456

1 2

3 45 6

5










119872 =1198791

21198792

21198793

21198793

21198792

21198791

2

1198721 =1198793

21198791

21198792

21198792

21198791

21198793

2

1198722 =1198792

21198793

21198791

21198791

21198793

21198792

2

(1)





A

B

C


Tb

Tc

T1

4

T2

2

T3

2

T1

2

T3

2

T2

2

T1

4

(a)

A

B

C


T2

2

T3

2

T1

2

T1

2

T3

2

T2

2

(b)

A

B

C


T1

2

T2

2

T3

2

T3

2

T2

2

T1

2

(c)


A

B

C


T1

4

T2

2

T3

2

T1

2

T3

2

T2

2

T1

4

Ta

Tb

Tc

(a)

A

B

C


T1

2

T2

2

T3

2

T3

2

T2

2

T1

2

(b)


DS5202 ACMC (EV1048)DS1007


PC


NPC inverter

PWM generator

R-L load

Signalprocessing


Oscilloscope







The fault occurs

Uao (V)

Uab (V)

200６

grid

500６

grid

10ＧＭgrid t (ms)

(a)


Ia (A)

1

grid

10ＧＭgrid t (ms)

(b)

The fault occurs

V＄ (V)

100６

grid

t (ms)500ＧＭgrid

V＄1

V＄2

(c)


V＄ (V)

100６

grid

t (ms)500ＧＭgrid

V＄1

V＄2

(d)




7 Conclusion











Acknowledgments


References




























RoboticsJournal of




VLSI Design



Shock and Vibration







Journal of



Volume 2018



Volume 2018


Journal of




SensorsJournal of



RotatingMachinery





Propagation






Hindawi


Advances in

Multimedia





P+ 1 1 0 0 0 0 0 0 0 0

Pminus 0 0 0 0 1 1 0 0 0 0

O+ 0 1 0 0 0 0 0 0 1 0

Ominus 0 0 1 0 0 0 0 0 0 1

N+ 0 0 0 0 0 0 1 1 0 0

Nminus 0 0 1 1 0 0 0 0 0 0

I

II

III

IV

V

VI

PPNOPNNPN

NPO

NPP

NOP

NNPONP PNP

PNO

PNN

PONPPO

OON

POOONN

POPONO

OOPNNO

OPPNOO

OPONON

PPPOOONNN

U lt 0

U = 0

U gt 0











Ud

D6

D5

D1

D2

D3

D4

A

N

QA3

QA1

QA2

QA4

C1

C2

O

B C

V＄1

V＄2

+

minus

(a)

Ud

D6

D5

D1

D2

D3

D4

A

N

QA3

QA1

QA2

QA4

C1

C2

O

B C

V＄1

V＄2

+

minus

(b)


I

II

III

IV

V

VI

PPNOPNNPN

NPO

NPP

NOP

NNPONP PNP

PNO

PNN

PONPPO[OON]

POO[ONN]

POP[ONO]

OOPNNO

OPPNOO

OPONON

PPPOOONNN

U lt 0

U = 0

U gt 0

(a)

I

II

III

IV

V

VI

PPNOPNNPN

NPO

NPP

NOP

NNPONP PNP

PNO

PNN

PONPPOOON

POOONN

POPONO

OOP[NNO]

OPP

[NOO]

OPO[NON]

PPPOOONNN

U lt 0

U = 0

U gt 0

(b)








Ud

D6

D5

D10

D11

D12

D17

D18

D1

D2

D3

D4

D7

D8 D14

D13

D15

D16

D9

C1 +

+C2

O

D19

D20

Q1

Q2

N

Tra2

Trb2

Trc2

Tra1 Trb1 Trc1

QA2

QA3

QA4

QB1

QB2

QB3

QB4

QC1

QC2

QC3

QC4

A B C

QA1

+

minus

O






















I

II

III

IV

V

VI

PPNOPNNPN

NPO

NPP

NOP

NNPONP PNP

PNO

PNN

PONPPOOON

POOONN

POPONO

OOPNNO

OPP

NOO

OPONON

OOONNN

PPP

1

23

4

6

12

3456

1 2

3 45 6

5










119872 =1198791

21198792

21198793

21198793

21198792

21198791

2

1198721 =1198793

21198791

21198792

21198792

21198791

21198793

2

1198722 =1198792

21198793

21198791

21198791

21198793

21198792

2

(1)





A

B

C


Tb

Tc

T1

4

T2

2

T3

2

T1

2

T3

2

T2

2

T1

4

(a)

A

B

C


T2

2

T3

2

T1

2

T1

2

T3

2

T2

2

(b)

A

B

C


T1

2

T2

2

T3

2

T3

2

T2

2

T1

2

(c)


A

B

C


T1

4

T2

2

T3

2

T1

2

T3

2

T2

2

T1

4

Ta

Tb

Tc

(a)

A

B

C


T1

2

T2

2

T3

2

T3

2

T2

2

T1

2

(b)


DS5202 ACMC (EV1048)DS1007


PC


NPC inverter

PWM generator

R-L load

Signalprocessing


Oscilloscope







The fault occurs

Uao (V)

Uab (V)

200６

grid

500６

grid

10ＧＭgrid t (ms)

(a)


Ia (A)

1

grid

10ＧＭgrid t (ms)

(b)

The fault occurs

V＄ (V)

100６

grid

t (ms)500ＧＭgrid

V＄1

V＄2

(c)


V＄ (V)

100６

grid

t (ms)500ＧＭgrid

V＄1

V＄2

(d)




7 Conclusion











Acknowledgments


References




























RoboticsJournal of




VLSI Design



Shock and Vibration







Journal of



Volume 2018



Volume 2018


Journal of




SensorsJournal of



RotatingMachinery





Propagation






Hindawi


Advances in

Multimedia



Ud

D6

D5

D1

D2

D3

D4

A

N

QA3

QA1

QA2

QA4

C1

C2

O

B C

V＄1

V＄2

+

minus

(a)

Ud

D6

D5

D1

D2

D3

D4

A

N

QA3

QA1

QA2

QA4

C1

C2

O

B C

V＄1

V＄2

+

minus

(b)


I

II

III

IV

V

VI

PPNOPNNPN

NPO

NPP

NOP

NNPONP PNP

PNO

PNN

PONPPO[OON]

POO[ONN]

POP[ONO]

OOPNNO

OPPNOO

OPONON

PPPOOONNN

U lt 0

U = 0

U gt 0

(a)

I

II

III

IV

V

VI

PPNOPNNPN

NPO

NPP

NOP

NNPONP PNP

PNO

PNN

PONPPOOON

POOONN

POPONO

OOP[NNO]

OPP

[NOO]

OPO[NON]

PPPOOONNN

U lt 0

U = 0

U gt 0

(b)








Ud

D6

D5

D10

D11

D12

D17

D18

D1

D2

D3

D4

D7

D8 D14

D13

D15

D16

D9

C1 +

+C2

O

D19

D20

Q1

Q2

N

Tra2

Trb2

Trc2

Tra1 Trb1 Trc1

QA2

QA3

QA4

QB1

QB2

QB3

QB4

QC1

QC2

QC3

QC4

A B C

QA1

+

minus

O






















I

II

III

IV

V

VI

PPNOPNNPN

NPO

NPP

NOP

NNPONP PNP

PNO

PNN

PONPPOOON

POOONN

POPONO

OOPNNO

OPP

NOO

OPONON

OOONNN

PPP

1

23

4

6

12

3456

1 2

3 45 6

5










119872 =1198791

21198792

21198793

21198793

21198792

21198791

2

1198721 =1198793

21198791

21198792

21198792

21198791

21198793

2

1198722 =1198792

21198793

21198791

21198791

21198793

21198792

2

(1)





A

B

C


Tb

Tc

T1

4

T2

2

T3

2

T1

2

T3

2

T2

2

T1

4

(a)

A

B

C


T2

2

T3

2

T1

2

T1

2

T3

2

T2

2

(b)

A

B

C


T1

2

T2

2

T3

2

T3

2

T2

2

T1

2

(c)


A

B

C


T1

4

T2

2

T3

2

T1

2

T3

2

T2

2

T1

4

Ta

Tb

Tc

(a)

A

B

C


T1

2

T2

2

T3

2

T3

2

T2

2

T1

2

(b)


DS5202 ACMC (EV1048)DS1007


PC


NPC inverter

PWM generator

R-L load

Signalprocessing


Oscilloscope







The fault occurs

Uao (V)

Uab (V)

200６

grid

500６

grid

10ＧＭgrid t (ms)

(a)


Ia (A)

1

grid

10ＧＭgrid t (ms)

(b)

The fault occurs

V＄ (V)

100６

grid

t (ms)500ＧＭgrid

V＄1

V＄2

(c)


V＄ (V)

100６

grid

t (ms)500ＧＭgrid

V＄1

V＄2

(d)




7 Conclusion











Acknowledgments


References




























RoboticsJournal of




VLSI Design



Shock and Vibration







Journal of



Volume 2018



Volume 2018


Journal of




SensorsJournal of



RotatingMachinery





Propagation






Hindawi


Advances in

Multimedia



Ud

D6

D5

D10

D11

D12

D17

D18

D1

D2

D3

D4

D7

D8 D14

D13

D15

D16

D9

C1 +

+C2

O

D19

D20

Q1

Q2

N

Tra2

Trb2

Trc2

Tra1 Trb1 Trc1

QA2

QA3

QA4

QB1

QB2

QB3

QB4

QC1

QC2

QC3

QC4

A B C

QA1

+

minus

O






















I

II

III

IV

V

VI

PPNOPNNPN

NPO

NPP

NOP

NNPONP PNP

PNO

PNN

PONPPOOON

POOONN

POPONO

OOPNNO

OPP

NOO

OPONON

OOONNN

PPP

1

23

4

6

12

3456

1 2

3 45 6

5










119872 =1198791

21198792

21198793

21198793

21198792

21198791

2

1198721 =1198793

21198791

21198792

21198792

21198791

21198793

2

1198722 =1198792

21198793

21198791

21198791

21198793

21198792

2

(1)





A

B

C


Tb

Tc

T1

4

T2

2

T3

2

T1

2

T3

2

T2

2

T1

4

(a)

A

B

C


T2

2

T3

2

T1

2

T1

2

T3

2

T2

2

(b)

A

B

C


T1

2

T2

2

T3

2

T3

2

T2

2

T1

2

(c)


A

B

C


T1

4

T2

2

T3

2

T1

2

T3

2

T2

2

T1

4

Ta

Tb

Tc

(a)

A

B

C


T1

2

T2

2

T3

2

T3

2

T2

2

T1

2

(b)


DS5202 ACMC (EV1048)DS1007


PC


NPC inverter

PWM generator

R-L load

Signalprocessing


Oscilloscope







The fault occurs

Uao (V)

Uab (V)

200６

grid

500６

grid

10ＧＭgrid t (ms)

(a)


Ia (A)

1

grid

10ＧＭgrid t (ms)

(b)

The fault occurs

V＄ (V)

100６

grid

t (ms)500ＧＭgrid

V＄1

V＄2

(c)


V＄ (V)

100６

grid

t (ms)500ＧＭgrid

V＄1

V＄2

(d)




7 Conclusion











Acknowledgments


References




























RoboticsJournal of




VLSI Design



Shock and Vibration







Journal of



Volume 2018



Volume 2018


Journal of




SensorsJournal of



RotatingMachinery





Propagation






Hindawi


Advances in

Multimedia
















I

II

III

IV

V

VI

PPNOPNNPN

NPO

NPP

NOP

NNPONP PNP

PNO

PNN

PONPPOOON

POOONN

POPONO

OOPNNO

OPP

NOO

OPONON

OOONNN

PPP

1

23

4

6

12

3456

1 2

3 45 6

5










119872 =1198791

21198792

21198793

21198793

21198792

21198791

2

1198721 =1198793

21198791

21198792

21198792

21198791

21198793

2

1198722 =1198792

21198793

21198791

21198791

21198793

21198792

2

(1)





A

B

C


Tb

Tc

T1

4

T2

2

T3

2

T1

2

T3

2

T2

2

T1

4

(a)

A

B

C


T2

2

T3

2

T1

2

T1

2

T3

2

T2

2

(b)

A

B

C


T1

2

T2

2

T3

2

T3

2

T2

2

T1

2

(c)


A

B

C


T1

4

T2

2

T3

2

T1

2

T3

2

T2

2

T1

4

Ta

Tb

Tc

(a)

A

B

C


T1

2

T2

2

T3

2

T3

2

T2

2

T1

2

(b)


DS5202 ACMC (EV1048)DS1007


PC


NPC inverter

PWM generator

R-L load

Signalprocessing


Oscilloscope







The fault occurs

Uao (V)

Uab (V)

200６

grid

500６

grid

10ＧＭgrid t (ms)

(a)


Ia (A)

1

grid

10ＧＭgrid t (ms)

(b)

The fault occurs

V＄ (V)

100６

grid

t (ms)500ＧＭgrid

V＄1

V＄2

(c)


V＄ (V)

100６

grid

t (ms)500ＧＭgrid

V＄1

V＄2

(d)




7 Conclusion











Acknowledgments


References




























RoboticsJournal of




VLSI Design



Shock and Vibration







Journal of



Volume 2018



Volume 2018


Journal of




SensorsJournal of



RotatingMachinery





Propagation






Hindawi


Advances in

Multimedia



A

B

C


Tb

Tc

T1

4

T2

2

T3

2

T1

2

T3

2

T2

2

T1

4

(a)

A

B

C


T2

2

T3

2

T1

2

T1

2

T3

2

T2

2

(b)

A

B

C


T1

2

T2

2

T3

2

T3

2

T2

2

T1

2

(c)


A

B

C


T1

4

T2

2

T3

2

T1

2

T3

2

T2

2

T1

4

Ta

Tb

Tc

(a)

A

B

C


T1

2

T2

2

T3

2

T3

2

T2

2

T1

2

(b)


DS5202 ACMC (EV1048)DS1007


PC


NPC inverter

PWM generator

R-L load

Signalprocessing


Oscilloscope







The fault occurs

Uao (V)

Uab (V)

200６

grid

500６

grid

10ＧＭgrid t (ms)

(a)


Ia (A)

1

grid

10ＧＭgrid t (ms)

(b)

The fault occurs

V＄ (V)

100６

grid

t (ms)500ＧＭgrid

V＄1

V＄2

(c)


V＄ (V)

100６

grid

t (ms)500ＧＭgrid

V＄1

V＄2

(d)




7 Conclusion











Acknowledgments


References




























RoboticsJournal of




VLSI Design



Shock and Vibration







Journal of



Volume 2018



Volume 2018


Journal of




SensorsJournal of



RotatingMachinery





Propagation






Hindawi


Advances in

Multimedia




The fault occurs

Uao (V)

Uab (V)

200６

grid

500６

grid

10ＧＭgrid t (ms)

(a)


Ia (A)

1

grid

10ＧＭgrid t (ms)

(b)

The fault occurs

V＄ (V)

100６

grid

t (ms)500ＧＭgrid

V＄1

V＄2

(c)


V＄ (V)

100６

grid

t (ms)500ＧＭgrid

V＄1

V＄2

(d)




7 Conclusion











Acknowledgments


References




























RoboticsJournal of




VLSI Design



Shock and Vibration







Journal of



Volume 2018



Volume 2018


Journal of




SensorsJournal of



RotatingMachinery





Propagation






Hindawi


Advances in

Multimedia





Acknowledgments


References




























RoboticsJournal of




VLSI Design



Shock and Vibration







Journal of



Volume 2018



Volume 2018


Journal of




SensorsJournal of



RotatingMachinery





Propagation






Hindawi


Advances in

Multimedia




RoboticsJournal of




VLSI Design



Shock and Vibration







Journal of



Volume 2018



Volume 2018


Journal of




SensorsJournal of



RotatingMachinery





Propagation






Hindawi


Advances in

Multimedia


Documents

Fault-Tolerant Control Strategy for Neutral-Point …downloads.hindawi.com/journals/jcse/2018/5126404.pdfonly to open circuit fault and short circuit fault of outer switches. When