FE8113 - High Speed Analog to Digital Converters, Final Report

FE8113

High Speed Analog to Digital Converters

Final Report

Ivar Løkken, 26.04.2006

Ivar Løkken Side 1 05.05.2006


1 Introduction This report is the end product of the PhD-level course “FE8113 – High Speed Analog to Digital Converters” at the Circuits and Systems group at NTNU. The intention of the course has been to give the students a detailed insight into advanced Analog to Digital Converter (ADC) design and modelling, with special emphasis on modern and state of the art techniques. The focus has been on the pipeline ADC architecture and application of digital signal post-processing to overcome its inherent limitations. This is a popular research field in modern ADC design. The report is, like the course, divided into three main parts. The first part deals with the analog to digital conversion fundamental properties. Although this may seem basic, a thorough understanding of the fundamentals in analog to digital conversion is absolutely necessary to understand modern ADC design. It begins by explaining the processes of sampling and quantization and provides an overview of different quantization models. During these chapters, the reader will be given insight into aliasing and quantization distortion, the argument for dithering as well as the background for the infamous additive noise model. Next, ADC non-idealities and related performance numbers will be reviewed. To be able to read and interpret ADC specifications and performance data, one must be familiar with a range of quality figures and also what they will mean exactly in terms of non ideal behaviour. The second part will begin by introducing the pipeline ADC, the architecture around which this course has been focused. Its mode of operation will first be explained and next an overview will be given of the construction of the pipeline stage, including an explanation of digital redundancy and the 1.5-bit approach. Next, stage non-idealities, which limit the practical performance of pipeline ADCs, will be reviewed. This will give the reader insight into what challenges are found in designing high-speed, high-resolution converters. That prompts the introduction of gain error calibration and gain calibration techniques which is a key topic of the course. The principles of gain error calibration are reviewed together with the three different fundamental approaches; foreground calibration, background calibration and calibration with parallel reference ADC. Finally, to conclude the report, some state of the art techniques are presented. These include some proposed improvements to the gain error calibration schemes and an approach to eliminate the OTA in the pipeline stage. Finally, state of the art performance is presented, taken from very recent publications. This will provide the reader with insight in today’s cutting edge technology and performance limits. It is my hope that this report will give the reader an overview of modern ADC design and as such pass on some of what I’ve learned in this course. Ivar Løkken, 26.04.2006



1 INTRODUCTION ....................................................................................................................................... 2 2 SAMPLING AND QUANTIZATION ....................................................................................................... 7

2.1 SAMPLING............................................................................................................................................. 7 2.2 QUANTIZATION..................................................................................................................................... 9

2.2.1 Bennett’s additive noise approximation ........................................................................................ 10 2.2.2 The characteristic function method and dithering ........................................................................ 12 2.2.3 Quantization distortion; a deterministic approach ....................................................................... 16

3 ADC NON IDEALITIES .......................................................................................................................... 20 3.1 SAMPLING TIME UNCERTAINTY – JITTER. ............................................................................................ 20 3.2 MEASUREMENT INACCURACY............................................................................................................. 23

3.2.1 Offset and gain error..................................................................................................................... 23 3.2.2 Static non-linearity........................................................................................................................ 24 3.2.3 Noise.............................................................................................................................................. 26 3.2.4 Dynamic errors ............................................................................................................................. 28

3.3 PERFORMANCE NUMBERS ................................................................................................................... 30 4 THE PIPELINE ADC ............................................................................................................................... 35

4.1 MODE OF OPERATION.......................................................................................................................... 35 4.2 IMPLEMENTATION OF THE STAGE........................................................................................................ 36

4.2.1 Stage ADC..................................................................................................................................... 36 4.2.2 Stage DAC..................................................................................................................................... 40

4.3 STAGE NON-IDEALITIES ...................................................................................................................... 41 4.3.1 Limited OTA gain.......................................................................................................................... 41 4.3.2 Parasitic capacitance.................................................................................................................... 41 4.3.3 Noise.............................................................................................................................................. 42 4.3.4 Capacitance mismatch .................................................................................................................. 43

5 GAIN ERRORS AND GAIN ERROR CALIBRATION ....................................................................... 45 5.1 GAIN ERROR AND ITS CONSEQUENCES ................................................................................................ 45 5.2 THE CONCEPT OF GAIN ERROR CALIBRATION ...................................................................................... 47 5.3 APPROACHES TO GAIN ERROR CALIBRATION....................................................................................... 49

5.3.1 Digital foreground calibration...................................................................................................... 49 5.3.2 Digital background calibration..................................................................................................... 50 5.3.3 Calibration with parallel reference ADC...................................................................................... 52

6 NEW CALIBRATION TECHNIQUES .................................................................................................. 57 6.1 MEMORY EFFECTS AND MEMORY EFFECTS CALIBRATION ................................................................... 57 6.2 TWO CHANNEL BACKGROUND CALIBRATION ...................................................................................... 60 6.3 CALIBRATION OF STAGE DAC NON-LINEARITY .................................................................................. 62

7 COMPARATOR DITHERING ............................................................................................................... 64 8 OTA-LESS, COMPARATOR BASED STAGE DAC............................................................................ 65 9 PUSHING THE FOM – STATE OF THE ART PERFORMANCE..................................................... 66 10 SUMMARY................................................................................................................................................ 72



Part I: ADC Fundamentals

Analog-to-digital (AD) conversion consists of transforming a continuous-time and continuous amplitude, or analog signal, into a discrete-time and discrete amplitude, or digital signal. The resulting limited rate number representation enables storage, processing and transmission of the signal with much more flexibility than when in its analog form. Almost all AD-converters (ADCs) digitize the signal in the form of pulse code modulation (PCM). This is a straightforward discretization of time and amplitude by measurement. The signal is measured at fixed intervals in time. This process is known as sampling and the measurements as samples. Then, each sample is allocated a number representing its amplitude. This is known as quantization. Usually the numbers define an equally spaced amplitude grid where the value of the current input sample is allocated to the closest defined number. This is called as linear PCM (LPCM). Alternatives to PCM for digitizing do exist, including sigma-delta modulation, pulse-width modulation and vector quantization, but will not be treated in this report. In this first part of the report, we will begin by reviewing sampling and quantization and the very fundamental limitations of AD conversion. Then, we will look at practical limitations to measurement accuracy and how these affect the result. In essence, there are two fundamental forms of non-idealities in AD conversion; time-inaccuracy and amplitude measurement inaccuracy. However these, especially the latter, have a variety of sources and manifestations and we will categorize and interpret them, creating the necessary framework needed to understand practical ADC design.


2 Sampling and quantization

2.1 Sampling Sampling is the process of evaluating a continuous time signal at discrete instants in time. The sampling theory is the single most fundamental theory in digital signal processing and was attributed to Nyquist and Shannon, although publications by Wittaker and Kotelnikov were also very important in its development [1]-[4]. If your continuous time input signal is given as x(t), sampling is to take measurements at discrete time instants tn=nT, where n is the integer sampling index variable and T is the sampling period. Often, the sampling period is preferred expressed in terms of the sampling frequency fs=1/T. For a sinusoid, we then get:

( ) cos(2 ) [ ] cos 2ns

fx t A ft x n x A nf

π π⎛ ⎞

= → = = ⎜ ⎟⎝ ⎠

(1)

For a sampled sinusoid, the frequency is often described in terms of the normalized angular frequency, in radians per sample. This is given by:

02

s

ffπω = (2)

And the output can be written

0cos( )nx A nω= . (3)

Figure 1: Sampling of a continuous-time signal x(t).

As can be seen from (3), no distortion has been added to the signal. However, one will find that a whole range of input signals will produce identical outputs. By using (1), one will find that:

( ) ( )0( ) cos 2 2 coss nx t A ft k f t x A nπ π ω= + ⋅ → = , 0, 1, 2....k = ± ± (4)


This is known as the aliasing property. To generalize this, we first look at the sampling process in a slightly different way. From the description and Fig. 1, it is evident that sampling is equivalent to multiplying the input signal with dirac pulses at all multiples of nT, that is:

( ) ( ) ( )( )n sn n

x x t t nT x nT t nTδ δ∞ ∞

=−∞ =−∞

= ⋅ − = −∑ ∑ (5)

We can then apply the fourier transform to this expression to get the frequency domain equivalent:

( ) ( ) ( ) ( )s n sn n

X f FT x X f FT t nT X f nfδ∞ ∞

=−∞ =−∞

⎧ ⎫= = ∗ − = −⎨ ⎬⎩ ⎭∑ ∑ (6)

The result in (6) is identical to the discrete time fourier transform (DTFT). As can be seen, the output spectrum will consist of infinitely many “copies”, or aliases, of the input spectrum, each centred on multiples of the sampling frequency. This is shown in Fig. 2.

X(f)

f

X(f)

ffsfs/2 3fs/2 2fs fsfs/2 3fs/2 2fs-fs/2 -fs/2

1 2 3

Figure 2: Spectrum of x(t) (left) and corresponding x[n] (right) For the sampled spectrum we have numbered the shown aliases 1, 2 and 3. It is instrumental to realize that any signal energy found in the region of alias 1, i.e. / 2sf± will be copied to every other alias from -∞ to ∞ when it is sampled. Just like any signal energy in any alias from -∞ to ∞ will be copied to alias 1. Hence, for any signal to be uniquely reconstructed from sampling, it must be constrained to one alias range of / 2sf± . The signal must be band-limited to half the sampling frequency, also called the Nyquist frequency. Within this range, sampling leads to no distortion. The practical implication of this for ADC design is twofold: 1) The sampling frequency must be at least twice that of the highest frequency that will be sampled. 2) Unwanted energy outside the alias range must be removed to avoid unwanted aliasing (alias-distortion). This is called antialiasing of alias-filtering. Usually, the desired alias is no. 1 from the figure and the antialias filter is thus a lowpass filter. It should however be noted a signal limited to within the range [ ]/ 2,( 2) / 2s snf n f+ for any odd n, can be uniquely reconstructed from sampling at sf . This is called subsampling and often used in modulated radio-type applications.


2.2 Quantization Quantization is the process of mapping the amplitude of the signal to a finite set of levels. If the mapping is done sample by sample, x is mapped to a set of values yi, i ∈ l , where the index set l is a set of integers. This is called a scalar quantizer. If the levels are equally spaced, the quantizer is uniform, if not it is non-uniform. Alternatively an input vector x of length N can be mapped to a set of output vectors yi , i ∈ l , where x and all yi ∈ ℜN . This is called an N-dimensional vector quantizer. In this document we will only be concerned with uniform scalar quantizers, which are found in most ADC applications. A B-bit mid-thread uniform scalar quantizer is shown in figure 3. This is a quantizer where

-1- i iy y = ∆ for all i, x is mapped to yi when ]/ 2, / 2 i ix y y∈ − ∆ + ∆ and -1 -1-2 ..., -1,0,1....2 -1B Bi = . If x exceeds this range, the quantizer is in overload and will truncate

the output signal. The value ∆ is referred to as the quantization step size.

Figure 3: The uniform scalar quantizer

As can be seen, the quantization error is a non-linear deterministic function of x. Since such functions are very difficult to analyze for all but the simplest input, several approximations and statistical methods have been introduced. We will review some of the most important of these.


2.2.1 Bennett’s additive noise approximation In his classic paper [5], Bennett showed that the quantization process can be approximated as an additive noise source under certain conditions. This is still the most used method even today, but it is often used without attention being paid to the conditions themselves. What Bennett showed was that the quantization error would be equivalent to a noise source independent of the input and distributed equally between ]- / 2, / 2∆ ∆ if:

- The quantizer does not overload. - The quantizer has a large number of levels. - The step-size ∆ is small compared to the input signal range.

Bennett further proved that this approximation would be asymptotically exact for a Gaussian input distribution when ∆→0.

e

e

Figure 4: Bennett’s additive noise model.

Since the distribution of the error is equal, its probability density function (PDF) can be written as:

( ) ( )1 , -

2 20 , otherwise

ee

f e e∆

∆ ∆⎧ < ≤⎪= Π = ∆⎨⎪⎩

(7)

∆Π is the normal notation for a rectangular window given by the right hand part in (7).

Using this, we find that the mth moment of e[n] is:

( )/ 2

/ 2

1m m meE e e f e de e de

∞ ∆∆

−∞ −∆

⎡ ⎤ = ⋅ = ⋅⎣ ⎦ ∆∫ ∫ (8)

For the first two moments, error mean and power, (8) gives:

[ ] 0E e = (9) 2

2 2

12eE e σ ∆⎡ ⎤ = =⎣ ⎦ (10)


Furthermore, Bennett showed that if, in addition, the probability distribution of pairs of input samples is given by a smooth PDF, i.e. that ( )x xf , where [ ]1 2 x Tx x= , is a continuous function, then the error samples will be orthogonal. In other words:

[ ] 0 , 0n n kE e e k+⋅ = ≠ (11) This means that the error autocorrelation function and the power spectral density (PSD) will be given by:

[ ]2 , 0

[ ]0 , otherwise

ee n n k

kR k E e e

σ∆

+

⎧ == ⋅ = ⎨

⎩ (12)

The PSD is defined by the DTFT of the autocorrelation function, here normalized to the sampling frequency fs:

( ) 2 2

2 1[ ] [ ] s

j fkfj f e

e e eks s

S e DTFT R k R k ef f

ππ σ−∞∆

=−∞

= = =∑ (13)

What we have is in other words a spectrally white error with power 2

eσ . This is very familiar results for anyone who has dealt with digital signal processing or data converter design.

⇔

1P =∆

2ˆ e

es

Sf

σ=

Figure 5: Quantization error probability function and power spectral density

For a B-bit quantizer, the total number of levels is 2B and the maximum level random input is given by ( )12B x− ∆

Π . The ratio of maximum signal power to maximum noise power, or the signal to quantization noise ratio (SNQR) is hence given by:

( )2

2

2212

212

10 log 10 log 6.02 [dB]B

x

e

SNQR Bσσ

⋅∆

∆

⎛ ⎞⎛ ⎞ ⎜ ⎟= ⋅ = ⋅ ≈ ⋅⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠

(14)

For a maximum level sinusoid, with peak-to-peak amplitude of 2B ⋅∆ , the SNQR is:

( )2

2

228

212

10 log 10 log 6.02 1.76 [dB]B

x

e

SNQR Bσσ

⋅∆

∆

⎛ ⎞⎛ ⎞ ⎜ ⎟= ⋅ = ⋅ ≈ ⋅ +⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠

(15)

This is well known as the “6dB per bit” rule.


It must be emphasized that the conditions are of paramount importance when using this model. The quantization error is as mentioned a deterministic non-linear function of x, and the error distribution may vary significantly from the approximation in cases where the conditions are not met. A comprehensive study of the validity of the additive noise model in terms of input statistical properties, can be found in the thesis of Marco [6].

2.2.2 The characteristic function method and dithering The analysis of quantizer error moment dependence was first introduced by Widrow [7]. It is based on the recognition that quantization, rounding an input range ±∆/2 to a fixed value, is equivalent to area sampling of the input PDF within that range, also called a quantizer bin. The probability of a given discrete output level yi is equal to the probability of the input x being within ±∆/2 of that level and the output PDF will be given by:

( )/ 2

/ 2

( ) ( )i

y xi i

f y y i f x dxδ∆+∆∞

=−∞ ∆−∆

= − ∆∑ ∫ (16)

Figure 6: Midread quantizer in the amplitude domain (a) and the PDF-domain (b) This is equivalent to sampling after convoluting the input PDF with a rectangular window of width ∆:


[ ] ( )( ) ( )y xi

f y f y y iδ∆= ∆ ⋅Π ∗ ⋅ − ∆∑ (17)

The input PDF has in other words been area sampled with quantization-“frequency” φq=1/∆. This is intuitive when looking at Fig. 6, which shows the input and output in the PDF domain and the signal domain. The fourier transform of the output PDF, also called the characteristic function (CF), is then given by:

( ) ( )( )( ) ( ) sincy y x q qi

u FT f y u i u iφ φ∆

Ψ = = Ψ − ⋅ ∆ −∑ (18)

Similar to the sampling theorem, Widrow’s quantization theorem consequently states that if

( )x uΨ =0 for u > φq/2, the input CF can be fully retrieved from the output CF and therefore the input PDF from the output PDF. The output CF will merely be a product of the input CF and the CF of a uniform distribution (the sinc-function). A convolution of the input PDF with a uniform PDF equals white, additive noise to the input. Unfortunately, no real-world input signals have such a characteristic function as this would require an infinite amplitude span. Those that come closest are large Gaussian-like distributions, as indicated by the findings that led to Bennett’s additive noise model. However, we can also use the characteristic function to look at the conditional independence in any given statistical moment of the output. Using the definition of the mth statistical moments, we find that it can be found by differentiating the characteristic function at the origin:

( )0

( )2

m mym m

y m

u

d ujE Y y f y dyduπ

∞

−∞ =

Ψ⎛ ⎞⎡ ⎤ = = ⎜ ⎟⎣ ⎦ ⎝ ⎠∫ (19)

If we now impose a condition; that the input CF is of such nature that its mth derivative is zero at all integer multiples of the quantization-“frequency” φq:

( )( )( ) sinc0, for i 0

q

mx

m

u i

d u udu

φ=

Ψ ⋅ ∆= ≠ (20)

Then we find, using the previously shown expression for ( )y uΨ in (18), that the mth moment of the quantizer output is given by:

( ) ( )( )

( ) ( )

2

0

0

2 2

0

sinc

2

sinc

2

2 2 2 1

m

m mxm

m

um m i im

xm i i

i

l m l

l

d u ujE Ydu

m d u d uji du du

E xml l

π

π

=

−

−=

−⎢ ⎥⎣ ⎦

=

Ψ ⋅⎛ ⎞⎡ ⎤ = ⎜ ⎟⎣ ⎦ ⎝ ⎠

Ψ⎛ ⎞⎛ ⎞= ⎜ ⎟⎜ ⎟⎝ ⎠ ⎝ ⎠

⎡ ⎤⎛ ⎞ ∆⎛ ⎞ ⎣ ⎦= ⎜ ⎟⎜ ⎟ +⎝ ⎠⎝ ⎠

∑

∑

(21)


Solving (21), one will find that if (and only if) the condition in (20) holds, that the mth derivative of the input CF is zero at all integer multiples of the quantization-“frequency”, then the mth moment of y=x+e is equal to the mth moment of x plus a constant, i.e. an error that in this moment is input-independent and with uniform PDF. Of course, since the source signal x is arbitrary, we won’t know if the requirement in (20) holds. However, the input of the quantizer can be forced to meet it regardless of source by applying dithering [8]. In this case the quantizer input is given by w=x+v, as shown in Fig. 7, with the conditional PDF

( )| ( )|, ( , )w x x v xf w x f w x+= . (22)

Figure 7: Dithered quantizer Since the dither is assumed completely independent of the source signal x, it can be found using some calculus (see [8]) that:

[ ] ( )( ) ( )y v xk

f y f f y y kδ∆= ∆ ⋅Π ∗ ∗ ⋅ − ∆∑ (23)

( ) ( ) ( )( )( ) sincy x q v q qi

u u i u i u iφ φ φΨ = Ψ − ⋅Ψ − ⋅ ∆ −∑ (24)

Looking at (24), we see that we can now apply the same condition as for the undithered case, but to the dither signal instead of the input:

( ) ( )( )sinc0 , 0

q

mv

m

u i

d u ufor i

duφ=

Ψ ⋅= ≠ (25)

If this holds, the mth output moment will be given by:

( ) ( )( )

( )

2

0

0 02 2

0 0

( ) sinc

2

( ) sinc( ) ( ) 2

2 2 2 1

r

m mv xm

m

u

m i m imv x

i m ii u

l r lmm r

r l

d u u ujE ydu

m d u uj d ui du du

E vm rE x

r l l

π

π

=

−

−= =

−⎢ ⎥⎣ ⎦−

= =

Ψ ⋅ Ψ ⋅⎛ ⎞⎡ ⎤ = ⎜ ⎟⎣ ⎦ ⎝ ⎠

Ψ ⋅⎛ ⎞ Ψ⎛ ⎞= ⎜ ⎟⎜ ⎟⎝ ⎠ ⎝ ⎠

⎡ ⎤⎛ ⎞ ⎛ ⎞ ∆⎛ ⎞ ⎣ ⎦ ⎡ ⎤= ⎜ ⎟ ⎜ ⎟⎜ ⎟ ⎣ ⎦+⎝ ⎠⎝ ⎠ ⎝ ⎠

∑

∑ ∑

(26)


Since the dither and input signals are assumed statistically independent, E[vk]⋅E[xl]=0 for any k and l. Solving (26), it is seen that if the condition in (25) holds, the mth moment of y equals the sum of the mth moment of x, the mth moment of v and a constant. In other words the error for this moment will be additive and uniform. A dither signal consisting of the sum of N independent rectangular PDF (RPDF) sources of width ±∆/2, often called an Nth order dither source, will have the characteristic function:

( )( ) sinc Nv u uΨ = ∆ (27)

It will thus meet the condition of (25) for the N first derivatives and make the N first error moments uniform and input-independent. Inserted in (26), Nth order dither for N≥2 gives:

[ ] [ ] E y E x= (28)

( ) 22 2 1

12

NE y E x

+ ∆⎡ ⎤ ⎡ ⎤= +⎣ ⎦ ⎣ ⎦ (29)

This leads to the error mean and variance:

[ ] 0E e = (30)

( ) 22 1

12

NE e

+ ∆⎡ ⎤ =⎣ ⎦ (31)

For the case where the requirement in (25) is not met, calculation of the error moments is non-trivial. Fig.8 shows a figure of the simulated first to third error moments as functions of the input level with N=0 (no dither), N=1 (RPDF dither) and N=2 (triangular PDF (TPDF) dither). Since TPDF dither gives an input independent mean, meaning no distortion, and an input-independent noise power, meaning no noise power modulation, it is often viewed to be the ideal dither. Of course dither of higher order also have this property, but the noise penalty is greater as seen from (31).


-6 -4 -2 0 2 4 6-0.5

0

0.5

Firs

t erro

r mom

ent

No dither

-6 -4 -2 0 2 4 6-0.5

0

0.5RPDF dither

-6 -4 -2 0 2 4 6-0.5

0

0.5TPDF dither

-6 -4 -2 0 2 4 60

0.05

0.1

0.15

0.2

0.25

Sec

ond

erro

r mom

ent

-6 -4 -2 0 2 4 60

0.05

0.1

0.15

0.2

0.25

-6 -4 -2 0 2 4 60

0.05

0.1

0.15

0.2

0.25

-6 -4 -2 0 2 4 6-0.2

-0.15

-0.1

-0.05

0

0.05

0.1

0.15

x

Third

erro

r mom

ent

-6 -4 -2 0 2 4 6-0.2

-0.1

0

0.1

0.2

x-6 -4 -2 0 2 4 6

-0.2

-0.1

0

0.1

0.2

x Figure 8: Simulated first to third error moments with no dither, RPDF dither and TPDF dither.

2.2.3 Quantization distortion; a deterministic approach As mentioned in the introduction to quantization, the deterministic quantizer error is difficult to find. For simple input signals like sinusoids however, it can be analyzed, which enables estimation of harmonic distortion. The output spectrum of the quantizer We have now seen that the input under certain conditions can be modelled as a statistically independent additive noise source. We have also seen that by using dither the input can be forced to meet these conditions for any given amount of error moments. It will however also be beneficial to be able to calculate the output spectrum to see if the theoretical errors are of practical interest given a specified SNQR-requirement. Studies on the output spectral properties of non-dithered quantizers with sinusoid input have been shown by Blachman [9] and Mather [10].

2.2.3.1 The continuous case If we look at the quantization error in Fig.3, we can clearly see that it is correlated with the signal. It is a deterministic function of the input, if we assume no-overload operation; a sawtooth signal. Since the output and quantization error is a function of the input, we can describe the out signal in the no-overload region as:


( ) ( )( ) ( ) ( ) ( )Y t Q X t X t e X t= = + (32) If we apply a Fourier series to the sawtooth signal e, we get:

( ) ( )1

sin 2 ( )( ) ( 1)n

n

n X te X t

nππ

∞

=

= −∑ (33)

For simplicity ∆ is normalized to 1. If we assume the input signal to be a sinewave signal with amplitude A, this gives:

( )1

sin 2 sin(2 )( ) sin(2 ) ( 1)n

n

n A ftY t A ft

nπ π

ππ

∞

=

⋅ ⋅= ⋅ + −∑ (34)

We can rewrite this in terms of Bessel-functions and get the output expression as a sum of harmonics:

( )(2 1)1 1

( 1)sin(2 ) 2 (2 ) sin (2 1)2n

pn p

Y A ft J n A p ftn

π π ππ

∞ ∞

−= =

−= ⋅ + ⋅ ⋅ −∑ ∑ (35)

Where Jp(x) is a p-th order Bessel function of the first kind. We can see that we have a spectrum consisting of only odd harmonics. To find the SNQR, we find the power of the first harmonic, i.e. 1 sin(2 )A ftπ⋅ and divide it by the power of all other harmonics, i.e. ( )( )(2 1) sin 2 1 2 , 2,3...pA p ft pπ− ⋅ − = ∞ .

21

2(2 1)

2

2

(1)1

2

(2 1)1 2

10 log

( 1)2 (2 ) 10 log

( 1)2 (2 )

pp

n

n

n

pn p

ASNQRA

A J n An

J n An

ππ

ππ

∞

−=

∞

=

∞ ∞

−= =

⎛ ⎞⎜ ⎟⎜ ⎟= ⋅⎜ ⎟⎜ ⎟⎝ ⎠⎛ ⎞⎛ ⎞−⎜ ⎟+ ⋅⎜ ⎟⎜ ⎟⎝ ⎠= ⋅ ⎜ ⎟

⎛ ⎞−⎜ ⎟⋅⎜ ⎟⎜ ⎟⎝ ⎠⎝ ⎠

∑

∑

∑ ∑

(36)

The maximum SNQR as function of number of bits is shown in table 1 and compared to Bennett’s 6dB per bit rule for sinusoid input.


Table 1: SNQR for sinusoid input Number of bits B Maximum amplitude Amax SNQR SNQR Bennett 2 1 13.30 13.80 3 3 19.52 19.82 4 7 25.59 25.84 5 15 31.65 31.86 6 31 37.70 37.88 7 63 43.76 43.90 8 127 49.82 49.92 9 255 55.87 55.94 10 511 61.93 61.96 If the input signal consists of multiple sinusoids, e.g.:

1 2( ) sin(2 ) sin(2 )X t A f t B f tπ π= ⋅ + ⋅ (37) One can calculate, repeating the steps (32) to (35), that intermodulation product #pq will have the amplitude:

( ) ( )1 1

( 1) (2 ) (2 )n

pq p qn p

A J n A J n Bn

π ππ

∞ ∞

= =

−= ⋅ ⋅∑ ∑ . (38)

2.2.3.2 The sampled case In an AD-conversion, the signal is sampled before being quantized. Thankfully, since sampling is a linear process, one can change the order of sampling and quantization, i.e. sample the quantized output as given by (35) for the sinusoid case:

( ) ( )0 (2 1) 01 1

( 1)sin 2 (2 ) sin (2 1)n

pn p

Y A n J n A p nn

ω π ωπ

∞ ∞

−= =

−= ⋅ + ⋅ ⋅ −∑ ∑ (39)

As we can see, since harmonics are produced for all p up to infinity, they will produce aliasing. For instance, if the input frequency is 4MHz and the sampling frequency 48MHz, the 7th harmonic at 28KHz will fold around fs/2 to 20KHz, overlapping the 5th harmonic. The 13th harmonic and 19th harmonic also fold to 20KHz, However, if the input frequency is 4.1MHz, the 7th harmonic at 28.7MHz will fold down to 19.3MHz, while the 13th harmonic folds to 18.7MHz and the 19th to 18.1MHz. If it is 4.001MHz, the 7th harmonic folds to 19.993MHz, the 13th harmonic to 19.987MHz and the 19th harmonic to 19.981MHz. Thus, the ratio between the input frequency and the sampling frequency will determine the final spectrum. If it is a simple integer, the spectrum will be discrete, if it is close to an integer, the alias components will be close together and it will look white.


0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 x 10 7

-250 -200 -150 -100

-50 0

Frequency [Hz]

Amplitude [dB]

Quantization spectrum, f=4MHz, fs=48MHz

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 x 10 7

-300 -250 -200 -150 -100

-50 0

Frequency [Hz]

Amplitude [dB]

Quantization spectrum, f=4.1MHz, fs=48MHz

Figure 9: Quantization spectrum, f=4MHz (top) and f=4.1MHz (bottom), fs=48MHz

Figure 9 shows the output spectrum of two different sampled and quantized input sinusoids. In the first case, the input frequency is 4MHz and the sample frequency 48MHz. We see that the spectrum consists of the expected odd harmonics, but also folding products between f and fs. These fall at 48±n⋅4 and we will thus see components at both even and odd multiples of f. When the ratio between f and fs is an integer, this is expected. In the second example, the input frequency is 4.1MHz. We then see that we get a lot more intermodulation products, due to the folding and intermodulation of an infinite number of harmonics with multiples of fs, the discrete components are at multiples of 0.1MHz or the distance to the nearest integer ratio. With an input of 4.001MHz, alias components will be found at all multiples of 0.001MHz and the spectrum will look almost white.


3 ADC non idealities The basic AD conversion system consists of three functional blocks. The first block is the antialias-filter to remove unwanted energy in the alias region. The next one is the sample-and-hold amplifier (S/H). This block samples the input signal at the sampling instant tn and holds this sampled value until the next sampling instant tn+1. This enables the entire sampling period between tn and tn+1 to be used for the measurement and quantization process. The next block, which does this and produces the output data, is usually referred to as the ADC, even though all three constitute the AD conversion system.

Figure 10: Basic B-bit AD conversion system

In this chapter, we will look at the basic error mechanisms in each stage and how to specify basic performance requirements for the system.

3.1 Sampling time uncertainty – jitter. In the process of sampling, one of the fundamental performance limitations is sampling time deviations, also called jitter. The sampling instant is determined by a clock generator, usually a voltage-controlled crystal oscillator. This will always have a certain variance in frequency, determined by its design and the circuitry in which it is employed. Jitter is usually categorised in two forms; white jitter and sinusoid jitter. White jitter is simply random deviations in the clock crossover instant, caused by noise sources in the system. It is treated as a uniformly distributed and spectrally white process with a given variance. The second is deterministic, sinusoid jitter. The output frequency from a VCXO is voltage modulated, and ripple in the supply lines and capacitive coupling from signal or power supply lines can often cause a sinusoid variation of the sampling frequency. This will cause modulation distortion, as we will later see. Even though jitter distortion is inferred during the process of sampling (or in the case of digital-to-analog conversion, reconstruction), it is treated as a continuous-time phenomenon. The sampling instant deviation is continuous - hence the error resulting from it is also continuous. This is illustrated in fig.11. The correct sampling instant is at time tn, but because of jitter it is displaced to tn+j. Consequently, the measured amplitude is not X, but X+εj, where εj is the jitter error.


Figure 11: Sampling time deviation and resulting amplitude error.

First, we will assess the white jitter case [11]. The instantaneous error resulting from a jitter amplitude j will be given by:

( )j

x tjt

ε ∂=

∂ (40)

We assume the jitter to be randomly distributed with variance 2

jσ . For a maximum-level sinusoid input signal with amplitude normalized to 1 and frequency f, the slope will be given by:

( ) ( )( )( ) sin 2 2 cos 2x tx t ft f ftt

π π π∂= → = ⋅

∂ (41)

To find the average error variance, we multiply the jitter variance with the average variance of the slope, i.e.:

( )( )2

22 2

0

2 2 2

1 2 cos 22

2

j j

j

f ft dt

f

π

εσ σ π ππ

σ π

= ⋅ ⋅

= ⋅ ⋅ ⋅

∫ (42)

When the input amplitude is normalized to 1, the signal power 2 1 2sσ = , thus we can calculate the ratio 2 2/

js εσ σ and, using the “6dB per bit”-rule, find the corresponding resolution. Figure 12 shows the resolution vs jitter standard deviation as a fraction of the input frequency f. For 14-bit resolution, j fσ must be less than 1·10-5. For 100kHz input signal, this means less than 100ps jitter standard deviation, for 1MHz input signal less than 10ps and for 100MHz input signal less than 0.1ps. To design a clocking system with less than 0.1ps standard deviation is exceedingly difficult and jitter is a major obstacle in design of ADCs combining high speed and high resolution.


Figure 12: Resolution from white jitter error noise power.

As mentioned previously, jitter can also be sinusoid, in which case it does not raise the noise-floor of the converter, but generates sideband distortion. This can easily be shown by viewing the now deterministic jitter process j(t) as added phase-modulation in the original signal [12]-[13]:

( )( )( ) cos iy t A t j tω= ⋅ +⎡ ⎤⎣ ⎦ (43)

If we assume sinusoidal jitter with frequency ωj and amplitude J seconds peak-to-peak we get:

( )( ) ( )

12

1 12 2

( ) cos sin( )

cos( ) cos cos( ) sin( ) sin cos( )

i j

i i i i i j

y t A t J t

A t J t A t J t

ω ω

ω ω ω ω ω ω

⎡ ⎤= +⎣ ⎦

= ⋅ − ⋅ (44)

Assuming ( )1<<iJω (44) approximates to:

1 14 4( ) cos( ) sin(( ) ) sin(( ) )i i i j i i jy t A t J t J tω ω ω ω ω ω ω⎡ ⎤≅ ⋅ + − + +⎣ ⎦ (45)

As we can see, the jitter has created modulated sidebands at ji ωω ± . The level of the sidebands relative to the signal is given by:

⎟⎠⎞

⎜⎝⎛⋅=

4log20 i

jJR ω dB (46)

Since there are two sidebands, the total RMS jitter noise is given by 2/iJω and thus


, 20 log2

ij rms

JR ω⎛ ⎞= ⋅ ⎜ ⎟⎝ ⎠

(47)

By looking at the approximation above it is seen that we here extract only the first order modulation products, while there actually are more, i.e. at ji nωω ± , n=1,2,3…. This is generally a sufficient approximation since the first order products are dominating. If one wants to find the amplitude of the other sidebands as well, one can solve (44) using Bessel functions:

( ) ( )( ) ( )

1 12 2

12

( ) cos( ) cos cos( ) sin( ) sin cos( )

cos ( )

i i i i i j

n i i j

y t A t J t A t J t

A J J n t

ω ω ω ω ω ω

ω ω ω∞

−∞

= ⋅ − ⋅

= +∑ (48)

We see that (48) will contain all modulation sidebands that are produced by the phase-modulation.

3.2 Measurement inaccuracy Ideally, the quantization process maps the analog input to a discrete set of levels corresponding to equidistant differences in the continuous input level. In reality however, this process is realized with analog circuits that have limited accuracy. This will lead to deviations from the ideal input-output transfer function and will cause output distortion. Additionally, analog circuits will introduce noise. To determine and quantify the requirements for these non-ideal effects is crucial to be able to design an ADC with a given resolution. After the requirements have been specified and quantified, fulfilling them will be an analog design challenge.

3.2.1 Offset and gain error With an ideal transfer characteristic, the centre of the zero output bin, that is where both the quantized output level and the quantization error is zero, should be at an input level of zero. This can be seen from fig.3. Any deviation from this level is referred to as ADC offset and is usually normalized to ∆ (∆ is also often referred to as a least significant bit, or LSB). This is shown in fig.13. It can be seen from the figure that if the offset is more than ∆/2, the wrong output code will be produced. It should be noted that static offset will not produce any distortion, since it is just a shift of the input-output transfer curve, which is still the quantized version of a straight line, but it can decrease the effective quantizer input range.


Figure 13: ADC offset

The gain error is the same, but for the maximum level output code. Gain error is also specified after compensating for offset. This means the gain error is the error in the distance between the center of the zero bin and the center of the maximum bin, as shown in fig.14.

Figure 14: ADC gain error

3.2.2 Static non-linearity One of the most important performance factors for an ADC is signal distortion. In many applications, low distortion is of utmost importance. The distortion is often explicitly specified, as we will look at later, and one of its sources is static non-linearity. The ideal step-size of the ADC transfer characteristic is ∆, however due to limited analog accuracy, it will in practise deviate from this. The deviation of step i is often referred to as the differential non-linearity (DNL) in i, or in other words:


( ), 1 , 1( ) y i i y i iDNL i x x− → → += − − ∆ (49) The sum of DNL from step 0 to step m is called the integrated non-linearity (INL) in m:

0( ) ( )

m

iINL m DNL i

=

= ∑ (50)

An example of DNL and INL is shown to the left in figure 15. If a line is drawn between each INL(m), one can define the INL as a continuous function of the input. It then gives the deviation in the interpolated, continuous input-output characteristics from the ideal straight line and therefore the non-linearity, disregarding quantization distortion, as function of the input.

Figure 15: INL and DNL as function of input

If:

( ) , for all m2

INL m ∆≤ . (51)

Then the transition point will be within / 2m∆ ± ∆ for all m. In other words, each transition point is uniquely located within its bin. Thus, sweeping the input from minimum to maximum level will excite all output codes once and only once. This is usually referred to as monotonicity, and any ADC fulfilling (51) is guaranteed to be monotonic. To calculate the resulting distortion the continuous INL-function INL(x), it can be decomposed into a sum of harmonics using the fourier series. Assuming the INL-function is symmetrical, which will usually be the case since ADCs uses differential signal paths, the INL can be expressed:

21

( ) cos(2 )k xk

INL x a k tω∞

=

= ∑ . (52)


In (52), a2k is the amplitude of the 2·kth harmonic. Then the resulting continuous output function will be given by:

21

sin( ) cos(2 )c x k xk

y a t a k tω ω∞

=

= ⋅∑ . (53)

Note that in (53), the distortion from quantization is disregarded as yc is the output from the continuous (interpolated) transfer function. Similarly, for multi-tone input signals, the intermodulation spectrum can be estimated using:

( ) ( )1 2 2 1 21

sin( ) sin( ) cos(2 ) cos(2 )c x x k x xk

y a t t a k t k tω ω ω ω∞

=

= + ⋅ +∑ . (54)

3.2.3 Noise In an ADC implementation, thermal and flicker noise from amplifiers, resistors and so on will add to the quantization noise. Generally, we can assume the “analog” noise to be statistically independent of the quantization noise. Hence:

2 2 2 2jtot e aεσ σ σ σ= + + (55)

In (55), 2

eσ is the quantization error noise variance, 2jεσ is the jitter noise variance and 2

aσ is the total analog noise variance. When we have all the noise sources accounted for, we can calculate the total signal to noise ratio (SNR):

2

2 2 210 logj

s

e a

SNRε

σσ σ σ

⎛ ⎞⎜ ⎟= ⋅⎜ ⎟+ +⎝ ⎠

(56)

The analog noise contribution must be calculated for the specific circuit in question. Normally, noise models for each component are used and it is assumed that each noise source is statistically independent, so their variance can be summarized. Table 2 shows the standard noise models for the most normal components [14]:


Table 2: Noise models for some standard components [14] Element Noise models

2 4v kTRσ =

R 2 4i

kTR

σ =

2 2v dkTrσ =

dD

kTrqI

=

dD

kTrqI

= 2 2i DqIσ =

2

22( )

B Ci B

KI Iq If f

σβ

⎛ ⎞= + +⎜ ⎟⎜ ⎟

⎝ ⎠

2 142v b

m

kT rg

σ⎛ ⎞

= +⎜ ⎟⎝ ⎠

Mosfet (active region)

2 243i mkT gσ ⎛ ⎞= ⎜ ⎟

⎝ ⎠

2v

ox

KWLC f

σ =2 2 14

3vm ox

KkTg WLC f

σ ⎛ ⎞= +⎜ ⎟⎝ ⎠

Simplified model for low frequencies

2vσ

2iσ

2iσ

In table 2, 2

vσ is noise voltage variance and 2iσ is noise current variance. Unless otherwise

indicated, the noise sources are assumed spectrally white and Gaussian distributed. Table 3 shows the related characteristic parameters.

Table 3: Constants for models in table 2 Symbol Parameter Unit k Boltzman’s constant (1.38·10-23) J/k T Temperature k q Charge C rD Diode incremental resistance Ω ID Diode current A IB BJT base current A rb BJT series base resistance Ω gm Transconductance Ω-1 IC BJT collector current A β(f) BJT current gain, IC/IB WL MOS gate width and length m2 Cox MOS gate oxide capacitance µF/m2 K Device constant (see [14])


Of course, if the total noise contribution from a circuit is to be calculated, one must transform the different noise contributions to total output (or input) referred noise. Since noise sources are treated like normal sources and are assumed independent of each other, this can be accomplished through normal circuit theory and superposition. On a final note, it should be mentioned that capacitors and inductors do not generate noise, but accumulate noise from other sources. Figure 16 shows a resistor with noise coupled to a capacitor. Since the input noise has a white PSD the total integrated output noise power 2

_v capσ will be:

2_

142 2v cap

kTkTRRC C

πσπ

⎛ ⎞⎛ ⎞= =⎜ ⎟⎜ ⎟⎝ ⎠⎝ ⎠

(57)

2 4v kTRσ =

C

2_v capσ

Figure 16: RC-circuit with noise source

Similarly, for an inductor, one can find the noise current variance to be:

2_i ind

kTL

σ = (58)

Generally, we find that the analog SNR will increase with increased bias currents as well as increased capacitance. This, of course, opposes the desire to design circuits with low power-consumption.

3.2.4 Dynamic errors Sections 3.2.1 to 3.2.3 have covered constant or static distortion effects. In addition, there will be dynamic errors related to incomplete settling, digital feed-through etc. These effects are especially critical in high-speed ADC design where the time available for conversion is very small. The dynamic errors are mostly related to the sample and hold amplifier that must settle to a constant, and correct, level before the subsequent converter (comparators) determines the sequence of zeros and ones corresponding to this level1. Figure 17 shows an overview of dynamic behaviour of an S/H amplifier [15]. Its operation is usually divided into two modes or phases; the tracking phase and the hold phase. During the 1 It should be noted that jitter is in reality also a dynamic error in the S/H, but it is treated seperatly because of its different nature in being a time-error and not an amplitude-error.


tracking phase, the S/H must track the input voltage to be “ready” to take a sample. Then, at the sampling time instant tn, it goes from tracking mode to hold mode, holding the output at the value of the sample it’s just taken and thus enabling the ADC to find the corresponding digital value. The output of the S/H will need some time to settle to the sample level, this is called settling time. It is important that the output settles completely, within the required accuracy, before going to tracking mode again, otherwise the ADC will not get the correct sample value. There will usually also be an error in the hold value due to circuit imperfections like switch charge injection and droop in the holding element.

Figure 17: S/H amplifier, sample and hold step [15]

Non-idealities in S/H circuits include:

- Settling time: The time the output uses not settle to the required accuracy after a sample is taken and the hold mode is initiated. This limits the minimum hold mode time and consequently the maximum sampling frequency.

- Acquisition time: The time the S/H output uses before tracking the input signal to a required accuracy in tracking mode. This limits the minimum tracking mode time and consequently the maxiumum sampling frequency.

- Aperture time: Time from hold “command” until the sample value is taken. Variance in aperture time is the same as jitter.

- Hold mode droop: Loss of level in hold mode due to circuit imperfections, e.g. hold capacitor leakage. Limits the maximum hold mode time and consequently the minimum sampling frequency.

- Noise due to signal feed-through in hold mode and S/H amplifier noise. - Hold mode errors due to circuit imperfections such as charge injection.

To calculate the effects of dynamic errors in terms of distortion requires knowledge of the actual S/H implementation and is beyond the scope of this report. However, in general all errors should be well below the LSB-level, or in other words the voltage difference


corresponding to ∆. As is evident from fig.17, all dynamic errors except the droop will increase when the sampling frequency and input frequency increases, limiting the achievable accuracy of very high speed ADCs. S/H amplifiers with very fast settling and acquisition time also requires much current, increasing the circuit’s power consumption.

3.3 Performance numbers In sections 3.1 and 3.2, various ADC non-idealities have been introduced. These will all degrade the achievable accuracy and/or speed of the converter. Still, we need numbers to quantify and specify these non-idealities. In this section we review some key ADC performance values. We have already introduced SNQR, which can be approximated by the “6dB per bit”-rule. Thus we know that for a certain desired accuracy, the ADC must quantize the input to a certain number of bits. If increased accuracy is required, the quantization must be finer. This is straightforward, but to design a circuit that can uniquely resolve a very large number of input levels is not, especially if it has to run at a very high speed. To estimate the necessary complexity from the SNQR is thus very important for optimizing the design. We have also introduced the SNR, which is the signal power divided by the total noise power, including all analog and digital noise sources. In the discussion of static linearity, we mentioned distortion as an important performance factor. The distortion is usually calculated using the quantity of total harmonic distortion (THD). The THD is defined as the signal power divided by the power of all harmonic components, that is at k·fs, k=2,3,4… Usually, to limit the complexity of the calculation, k is limited to a maximum of 6-10. In other words:

( )

( )

2

2

22

2

sig

sig

sig

sig

f fj f

ef f s

f k fKHDj f

ek f k f

S e df

THDS e df

δπ

δδ

π

δ

σσ

= −

= −

= ⋅ −

= = ⋅ −

= =∫

∑ ∫ (59)

Where K usually is 6-10 and δ is an arbitrarily small number usually limited by the resolution of the spectral transformation. THD is usually given in percent or sometimes dB referred to the signal power. Also, the quantity THD+N is often used. This is the total noise and distortion power. When measuring noise only, the range sigk f δ⋅ ± must be removed from the output spectrum, THD+N includes all spectral power except of course the signal itself.

2

2 2s

n HD

THD N σσ σ

+ =+

(60)


The ratio between signal power and THD+N is often referred to as the signal to noise and distortion ratio (SNDR). The SNDR gives the total resolution of the converter. SNDR is measured in dB and thus given by:

2

2 210 log s

n HD

SNDR σσ σ

⎛ ⎞= ⋅ ⎜ ⎟+⎝ ⎠

(61)

Sometimes, the SNDR is expressed in the equivalent number of bits according to the “6dB per bit”-rule. This measure is called the effective number of bits (ENOB):

[dB]6.02

SNDRENOB = (62)

Often, the distortion spectrum can be dominated by one large harmonic component. In this case, the value of the dominating component might be more interesting than the THD. The spurious free dynamic range (SFDR) is defined as the ratio between the signal power and the power of the largest harmonic component. In other words:

2

2_ max

10 log s

HD

SNDR σσ

⎛ ⎞= ⋅ ⎜ ⎟⎜ ⎟

⎝ ⎠ (63)

Where HD_max is the single harmonic component with the largest power:

( )2_ max max , 2,3... sig

sig

f k fj f

ef k f

HD S e df kδ

π

δ

= ⋅ −

= ⋅ −

⎛ ⎞⎜ ⎟= =⎜ ⎟⎝ ⎠

∫ (64)

Due to increasing dynamic errors, the accuracy of an ADC decreases with increasing input frequency, meaning they can not maintain their full resolution up to the nyquist-frequency. The effective resolution bandwidth is defined as the frequency where the ENOB is reduced by 0.5 bits. The final performance metric we will mention is the figure of merit (FOM). As mentioned, high resolution and/or high speed will often result in an increase of the power consumption. FOM is a measurement on how efficiently the design is at utilizing its supplied power, or in other words its power to performance ratio. The FOM is defined as:

sup

2 2ENOBin

PFOM

f=

⋅ ⋅ (65)

Here, fin is the effective resolution bandwidth and Psup is total supplied power. Then the unit of the FOM will be energy (in joule) per conversion step (J/cs) and the lower the number is, the better. Given a certain FOM, one can calculate the relation between input bandwidth, accuracy and power consumption, as shown in fig.18 for a FOM of 1pJ/cs. Current state of the art for FOM is in the range of 0.25/0.5pJ/cs [16].


Figure 18: Resolution vs. input bandwidth and power consumption, FOM=1pJ.


[1]: E. T. Whittaker: "On the Functions Which are Represented by the Expansions of the Interpolation Theory," Proc. Royal Soc. Edinburgh, Sec. A, vol.35, pp.181-194, 1915 [2]: H. Nyquist: "Certain topics in telegraph transmission theory," Trans. AIEE, vol. 47, pp. 617-644, Apr. 1928. [3]: V. A. Kotelnikov: "On the carrying capacity of the ether and wire in telecommunications," Material for the First All-Union Conference on Questions of Communication, Izd. Red. Upr. Svyazi RKKA, Moscow, 1933 (Russian). [4]: C. E. Shannon: "Communication in the presence of noise", Proc. Institute of Radio Engineers, vol. 37, no.1, pp. 10-21, Jan. 1949. [5]: W. R. Bennett: “Spectra of Quantized Signals”, Bell Systems tech journal, vol. 27, pp. 446-472, July 1948. [6]: D. Marco: “Asymptotic Quantization and Applications to Sensor Networks”, Ph.D. thesis, The University of Michigan, 2004. [7]: B. Widrow “A Study of Rough Amplitude Quantization by Means of Nyquist Sampling Theory”, Sc.D. thesis, Dept. of Electrical Engineering, Massachusetts Institute of Technology, June 1956. [8]: S.P. Lipshitz, J. Vanderkooy, R.A. Wannamaker: “Quantization and Dither; A Theoretical Survey”, JAES Volume 40, Number 5, pp. 355-375; May 1992. [9]: N.M. Blachman: “The Intermodulation and Distortion due to Quantization of Sinusoids”, IEEE Trans. on Acoustics, Speech and Signal Processing, vol. ASSP-33, no.6, pp.1417-1426, December 1985. [10]: R.C. Maher: “On The Nature of Granulation Noise in Uniform Quantization Systems”, Journal of the Audio Engineering Society, Volume 40, no.1-2, pp. 12-20, January/February 1992 [11]: R. van der Plassche: “CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters”, 2nd edition, chapter 1.10, pp. 21-25, Kluwer Academic Publishers, ISBN 1-4020-7500-6, 2003 [12]: J. Dunn: “Jitter: Specification and Assessment in Digital Audio Equipement”, AES Convention Paper 3361, October 1992. [13]: I. Løkken: “FE8114: High Resolution Audio DACs – Final Report”, ch.2.1, pp. 6-7, NTNU, August 2005. [14]: D.A. Johns, K.Martin: “Analog Integrated Circuit Design”, ch.4.3, pp.199, John Wiley & Sons, ISBN 0-471-14448-7, 1997. [15]: R. van der Plassche: “CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters”, 2nd edition, chapter 2.6.24, pp. 101, Kluwer Academic Publishers, ISBN 1-4020-7500-6, 2003 [16]: A. Vinje: FE8113 presentation slides, ISSCC2006 presentation, March 2006. http://www.iet.ntnu.no/courses/fe8113/Slides/Lecture10.ppt


Part II: The Pipeline ADC and Gain

Error Calibration In recent years, the pipeline ADC has become the most popular architecture for medium to high speed and medium to high resolution AD conversion. Its low stage complexity makes it area and power efficient and by pipelining the multiple stages, high throughput can be achieved. Since there is gain in multiple stages, the high sensitivity for gain error and mismatch has limited the achievable resolution to 10-12 bits, and even then it has relied on high accuracy, high power analog circuitry. However, recent advanced in digital calibration and correction techniques have pushed the state of the art for pipeline converters forward by a great amount and they can now achieve resolution up to 14-16 bits as well as very good FOM numbers. Recent development and research in pipeline ADC calibration techniques has been the main focus of this course and will be summarized in the following chapter. It will begin with an introduction to the architecture, its manner of operation and its shortcomings and critical areas. Then, we will go on to see how digital calibration can be employed to combat these shortcomings, increasing resolution and improving FOM.


4 The pipeline ADC

4.1 Mode of operation The pipeline ADC uses multiple stages to reduce the circuit complexity. A B-bit ADC will have to resolve 2B unique levels. By instead cascading N stages of K bits each, where K<<B, complexity is reduced to N·2K. For instant a cascade of B 1-bit stages could be employed, meaning that each of the B stages would only have to resolve two levels. In most cases, the stages are 1.5 bits, for reasons which later will become apparent. The functionality of the pipeline ADC is shown in fig.19.

STAGE1

STAGE2

STAGEN

+

X

Y

ADC DAC

y=x-e

+-

G

x

G·ee

x-e1 G·e1-e2 GN-1·eN-1-eN

1/G1 1/GN-1

Figure 19: Pipeline ADC functionality schematic

The data is sampled in to stage 1 with an S/H (not shown) and converted to digital using a K-bit internal ADC. Then, the output is converted back to analog using a K-bit DAC. The input is subsequently subtracted from the DAC output, ideally resulting in an analog representation of the first stage quantization error. The error is scaled up by G=2K to span the entire full scale range of the next stage. The stage residue output is then sampled into the second stage. This stage converts the error from the first stage and passes its own over to the third stage. Its output is scaled by 1/G to compensate for the gain from stage 1. As can be seen, the resulting output Y, normalized to the input X, will be given by:


( ) ( ) ( )11 1 2 11

1

1 1...

1

NN NN

NN

Y X e G e e G e eG G

X eG

−−−

−

= − + ⋅ − + + −

= − (66)

This means that ideally, only the error from the last stage will be present at the output, scaled down by GN-1. With N K-bit stages, this means the output will be:

( 1)

12 NK NY X e−= − (67)

Which means the resolution is K(N-1) bits higher than for a single K-bit stage.

4.2 Implementation of the stage The stage in the pipeline ADC has to perform four basic operations. First, it needs to do a K-bit AD-conversion of its input to get the digital result y. Then it needs to find the analog quantization error e by subtracting the input from the output. For this, y must be converted back to the analog domain. Thirdly, it needs to multiply e by a factor G in the analog domain. And finally, the input to the next stage must be sampled. The first operation is performed by a low-resolution sub-ADC, typically a FLASH converter consisting of comparators. The last three operations are usually performed by a discrete time switched capacitor multiplying DAC.

4.2.1 Stage ADC The low resolution stage ADC is typically a FLASH-converter like shown in fig.20. The FLASH ADC is very suitable for low resolution and high speed due to its parallel architecture and simplicity. For a K-bit implementation it divides the reference full-scale voltage into 2K levels corresponding to the quantization steps using 2K-1 resistors. It then directly compares the input level to each of these using an identical number of comparators. For the ith comparator, the output is hence given by:

22

refi ref K

i Vc sign V

⋅ ⋅⎛ ⎞= − +⎜ ⎟

⎝ ⎠ (68)

So, if the input voltage is between e.g. quantization step 7 and 8, the 7 lowest comparators will output a ‘1’ and the rest a ‘0’. This code, where the number of ‘1’s corresponds to the output number, is called thermometer code. This is converted to normal binary code using a small logic circuit. The problem with the FLASH ADC is the large number of resistors and comparators needed if the number of bits K is high. It will then have a large area and power consumption as well as a high capacitive input load. Also, the resistor string will have to be very accurately calibrated to produce all the unique quantization steps if ∆ is very small compared to the full-scale reference.


Decoderthermometer

tobinary

+

-

+

-

+

-

INv

+refV

−refV

R

R

R

0D1D2D

1KD −

Comparators

CLK

N=(2K-1)

1c

1Nc −

Nc

Figure 20: FLASH ADC functional diagram

Of course, the stage ADC in the pipeline converter only has to resolve very few bits, so the FLASH architecture is very well suited. One major implementation issue is that since any error from the first stage is multiplied throughout the pipeline chain, the stage ADC needs a linearity performance equivalent to the full resolution of the pipeline converter. Its INL performance needs to be very good and the accuracy of the reference voltage division and the comparators thus needs to be extremely high. This is even the case if the stage is 1-bit. Although the stage ADC per se can then not have INL, any transition offset will translate to an error at the input of the next stage and it will result in INL for the pipeline as a whole. This can however largely be eliminated by simple use of digital redundancy and error correction, as pioneered by Lewis [1]. We will show this for the 1-bit stage case. For a normal 1-bit stage, the output is given by:

0 , 01 , 0

xy

x<⎧

= ⎨ ≥⎩ (69)

In (69), digital ‘0’ represents the negative reference voltage and ‘1’ the positive2. Then, the analog output from the first stage, 2·e1=2·x-y1·ref, as a function of the input will be as shown in fig.21. Since this is the input to the subsequent stage, its output y2 will be ‘0’ when e1 is less than zero and a ‘1’ when e1 is more than zero.

2 In other words, a sign-magnitude binary representation where 000…0 is the maximum negative value and 111...1 is the maximum positive value.


x

2·e1

2ref−

2ref refref−

ref−

2ref−

2ref

ref

y1:

y2:

Y:

0 0 0 1 1

0 1 1 0 1

00 01 01 10 11

offset

Figure 21: Residue and digital output, two pipelined 1-bit stages.

As can be seen, the offset in the first stage ADC directly translates to a DNL error in the total output Y. Thus, the accuracy of the first stage ADC must be given by the full INL requirement of the entire pipeline converter. The accuracy of the second stage must be half that of the first, since the second stage output error is totally multiplied with 1/2 (see fig.19). Now, we replace the first stage with a three-level stage, or 1.5 bit stage, where the output is given by:

00 , / 401 , / 4 / 410 , / 4

ref

ref ref

ref

x VV xy V

x V

< −⎧⎪ − ≤ <= ⎨⎪ ≥⎩

(70)

The second stage is still a 1-bit stage given by (69). The recombination is done with a full adder and the resulting output and residue will then be as shown in fig.22.


x

2·e1

4ref−

4ref

2ref−

2ref refref−

ref−

2ref−

2ref

ref

y1:

y2:

Y:

00 00 01 01 10 10

0 1 0 1 0 1

00 01 01 10 10 11

offset

Figure 22: Residue and digital output, pipeline 1.5-bit stages.

Now we see that the presence of offset does not affect the total output Y since the recombination with y2 cancels the error. As can be seen from studying the figure, the transition of y1 from ‘01’ to ‘10’ can be anywhere between 0 and Vref/2 without it affecting the total output. Hence, offset of up to ±Vref/4 is cancelled. This can be extended to all stages in the pipeline by cascading 1.5-bit stages and full adders, as long as the last stage is symmetrical around zero. This is shown in fig.22.

X

Y

1.5-bitstage

1.5-bitstage

backend1.5-bitstage

1 1/2 1/4 1/2N-1

Figure 23: Pipeline ADC with 1.5-bit stages and error correction


Using the topology in fig.23, stage ADC design is trivial, since it only needs an offset of less than ±Vref/4. Since the backend output, and error, is scaled down a great deal, this is not as critical.

4.2.2 Stage DAC The second core component of the pipeline stage is the stage DAC. The output of this DAC should ideally be G·e=G·(y-x). The subtraction and multiplication can be accomplished with a single switched capacitor circuit, often dubbed the multiplying DAC (MDAC). Its mode of operation is shown in fig.24.

inVoutV

+

+-

-

A

Cf

Cf

Cr

Crrefy V⋅

+

-outV+

-

xv +

xv −

Figure 24: MDAC mode of operation; a) Sampling phase, b) Feedback phase.

In the sampling phase, the differential input is coupled over the capacitors Cf and Cr, charging these to the input voltage. The size of these capacitors is determined by the given requirements for kT/C-noise (lower with large capacitors), acquisition time (faster with small capacitors) and mismatch (smaller with large capacitors). The stored charge at the end of the sampling phase is given by:

( ) ( )( ) ( )

Cr Cf in CM r f

Cr Cf in CM r f

Q Q V V C C

Q Q V V C C

+

−

+ = − ⋅ +

+ = − ⋅ + (71)

Next, in the feedback phase, the feedback capacitors Cf are coupled to the output, while Cr are coupled to either of the references, depending on the stage-ADC decision y (-1, 0 or 1).

( ) ( ) ( ) ( )( ) ( ) ( ) ( )

ref x r out x f in CM r f

ref x r out x f in CM r f

y V v C V v C V V C C

y V v C V v C V V C C

+ + + + +

− − − − −

⋅ − ⋅ + − ⋅ = − ⋅ +

⋅ − ⋅ + − ⋅ = − ⋅ + (72)

This leads to a charge redistribution:

( )out outref r out f in r f

V Vy V C V C V C CA A

⎛ ⎞ ⎛ ⎞⋅ + ⋅ + + ⋅ = ⋅ +⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠

(73)

Assuming Cf=Cr and solving (73) for the output we get:


( ) ( )12 22 21out in ref in ref

AV V y V V y VA

A

⎛ ⎞⎜ ⎟

= ⋅ − ⋅ ⋅ = ⋅ − ⋅ ⋅⎜ ⎟ +⎜ ⎟+⎝ ⎠

(74)

If the amplifier open-loop gain A is infinite, (74) simplifies to:

12 22out in refyV V V e⎛ ⎞= ⋅ − ⋅ = ⋅⎜ ⎟

⎝ ⎠ (75)

Thus we have the desired output to pass on to the next stage. Since this voltage is available at the end of the feedback phase, the subsequent stage should end its sampling phase as the current stage ends it feedback phase. The stage DACs are thus coupled with opposite clock phases from one stage to the next, using non-overlapping clocks, and hence also functions as S/H ampliers with the sampling phase and feedback phase corresponding to the tracking phase and hold phase from section 3.2.4 respectively.

4.3 Stage non-idealities In this chapter, we will treat non-idealities in the pipeline stage. Since pipeline converters in most practical implementations uses 1.5-bit stage ADCs with digital error correction, we will focus on the stage DAC. We will look at parasitic capacitance, noise, capacitor mismatch and gain errors. The section about gain error will be elaborated and lead the subsequent chapter on gain error calibration techniques, a central topic in the course.

4.3.1 Limited OTA gain The input-output relation of the stage DAC is given by (74). It can be rewritten in terms of an ideal term and a gain error term Ge:

( )2 , 2out in ref e e

AV V y V G GA

= ⋅ − ⋅ ⋅ =+

(76)

Thus, limited OTA open loop gain will produce a static gain error. If Ge=1 there is no gain error, but with e.g. 40dB OTA gain, Ge=0.980. Gain error and its consequences will be treated in detail in chapter 5.

4.3.2 Parasitic capacitance Often, the input parasitic capacitance of the amplifier is significant compared to the sampling capacitance. In this case, the transfer function will be affected by it. Figure 25 shows the stage DAC with the parasitic capacitance included in the schematics [2].


inVoutV

+

+-

-

A

Cf

Cf

Cr

Crrefy V⋅

+

-outV+

-

xv +

xv −

Figure 25: Stage DAC with parasitic capacitance; a) Sampling phase, b) Feedback phase. Repeating the analysis in (71) to (74) for this case, we now get:

( ) 12 , 11

fout in ref

r f p

CV V y V

C C CA

β

β

⎛ ⎞⎜ ⎟

= ⋅ − ⋅ ⋅ =⎜ ⎟+ +⎜ ⎟+⎜ ⎟

⎝ ⎠

(77)

With no parasitic input capacitance, β=1/2 and (77) equals (74). From (77) it is apparent that parasitic input capacitance will increase the gain error caused by limited OTA open loop gain. For instance, if β=1/3 and A=40dB, then Ge=0.968, compared to 0.98 in 4.3.1.

4.3.3 Noise The noise consideration consists of two parts, the OTA noise and the sampling capacitance kT/C-noise. The former will be noise added to the output in the feedback phase. The latter is sampling value noise than will be passed to the output when the sampling capacitance charge is sampled. Figure 26 shows a noise equivalent circuit for the stage DAC to calculate the noise in the feedback phase [2], which is when the output is sampled to the next stage. The input current noise is neglected since the input nodes are high impedance.

outV2niσ

Figure 26: Stage DAC noise model


The noise gain will be given by the transfer function of the circuit in fig.26:

2

2

2

1/11

no

ni

A

σ βσ

β

⎛ ⎞⎜ ⎟

= ⎜ ⎟⎜ ⎟+⎜ ⎟⎝ ⎠

(78)

Assuming a single-stage, single-pole, load-compensated OTA, one can use the Mosfet noise model for the input transistors from tab.2 and the kT/C analysis from section 3.2.3 to find the output noise with a given load capacitance CL:

2 4 1/2 13 1no

L

kTC

A

π βσ

β

= ⋅ ⋅ ⋅+

(79)

The factor 2 is due to the two input transistors in a differential system acting as two independent noise sources. Referred to the input of the MDAC, the noise expression must be divided by the squared closed loop MDAC gain from (77) and becomes.

2

2_

4 1/ 22 1 13 1 1

1/ 2 13 1

n OTAL

L

kTC

A AkTC

A

π βσ

β βπ β

β

⎛ ⎞⎜ ⎟

= ⋅ ⋅ ⋅ ⎜ ⎟⎜ ⎟+ +⎜ ⎟⎝ ⎠

= ⋅ ⋅ ⋅+

(80)

For the sampling, the input kT/C-noise in the differential system will be:

2_ / 2n kT C

r f

kTC C

σ = ⋅+

(81)

We can assume these noise sources to be uncorrelated and the total input referred noise variance to be 2 2

_ _ /n OTA n kT Cσ σ+ . Thus, for a given input referred noise requirement, both minimum sampling capacitance and load capacitance can be calculated from the above.

4.3.4 Capacitance mismatch As we have seen from the previous two sections, the reference capacitor and feedback capacitor have been assumed equal. However, in reality one can not design capacitors with perfect matching, there will always be a spread in the capacitance due to layout, oxide thickness gradients etc. If we use Cf as a reference and assume a mismatch ∆Cr, the resulting charge distribution error will be given by:


e ref rQ V C= ⋅∆ (82) The resulting sample voltage error will be:

ref re

f r

V CV

C C⋅∆

=+

(83)

Remembering that the gain in each stage is 2, we can refer this error to the LSB-level and find the resulting DNL for the ith stage:

12

rref

f r

refN i

CVC C

DNL V+ −

∆⋅

+= (84)

In (84), i=1 for the first stage, 2 for the second and so forth. If the variance is assumed to be determined completely by oxide thickness variation, the mismatch will be given by

C k C∆ = ⋅ where k is a process related constant [2], meaning that the DNL will improve by the square root of the sampling capacitance size. This suggests the use of large sampling capacitors, as does kT/C-noise, but that of course increases acquisition time and power consumption. However, there exist digital algorithms, so called dynamic element matching (DEM), that can decorrelate the mismatch error from the input, converting the distortion to noise, and furthermore if desired noise shape it [3].


5 Gain errors and gain error calibration

5.1 Gain error and its consequences As we have seen, different non-idealities in the pipeline stage can lead to a gain error in the multiplying DAC. We can write its transfer function in terms of an ideal one plus a gain error Ge as shown in section 4.3.1.

( )2out in ref eV V y V G= ⋅ − ⋅ ⋅ (85) As we have also seen, sources of gain errors will be limited OTA open-loop gain A, enhanced by input parasitic capacitance, and reference/feedback capacitance mismatch. If the gain error is to be minimized by analog design, one needs an OTA with high open-loop gain, which combined with fast settling and low noise will require lots of power. One also needs large sampling capacitances to minimize mismatch and the affects of parasitics on β, which would further increase the power consumption necessary to maintain satisfactory settling performance. The gain error can be translated to peak DNL similarly to the capacitance mismatch. As can bee seen from the transfer function in fig.27 [4], the output error is obviously maximum at maximum output voltage. The maximum output error will be given by:

( )1out ref eV V G∆ = ⋅ − (86)

x

2·e1

4ref−

4ref

2ref−

2ref refref−

ref−

2ref−

2ref

ref

Figure 27: Stage DAC transfer function with gain error.


The resulting peak DNL for the ith stage will then be given by:

( )

1

1

2

ref e

refN i

V GDNL V

+ −

⋅ −= (87)

However, gain error will also lead to an increase in the quantization noise level. As can be seen from fig.19, if the analog stage gain is not correct, the error contributions from e1, e2… will not cancel out at the output. There will be leakage of quantization noise from each stage to the output. For convenience, we will in the following analyze this for one stage only, assuming all stages except the first to make up an ideal backend ADC. The analysis can easily be expanded to the rest of the stages. A block diagram of a pipeline converter with gain error is shown in fig.28. The stage ADC is modelled as adding a (quantization) error e1 and the backend similarly as an error souce ebe. Note that the scaling is now normalized to the backend input level, as opposed to the input X in section 4.1, to more easily see the relation to the stage transfer function. It should be noted that the difference between fig.28 and fig.19/23 is only a question of output normalization. In a practical implementation, the normalization is to the LSB, since the output is on integer form, hence the scaling will be 2N for the first stage, 2N-1 for the second etc.

backendStage 1

Ge_1

2

Y

X

Vout_1_idealVin_be

e1

2- ebe

Figure 28: Model for analysis of first stage gain error.

From fig.28, the output is found to be:

[ ] ( )1 _12 2 1be eY X e e G= ⋅ + + ⋅ ⋅ − (88) If Ge_1=1, (88) then of course equals


[ ]2 beY X e= ⋅ + . (89)

We see that the first stage quantization noise then cancels out as expected. But reverting to (88), we see that the quantization error from the 1.5-bit first stage is visible at the output multiplied by ( )_12 1 eG⋅ − . If we for arguments sake accept Bennett’s additive noise model even for a 1.5-bit stage (although this is obviously not very accurate), we get, disregarding the backend noise:

( ) ( )2

1 22 2_1 _1

110 log 10 log [dB]1/ 3 1

x

e e

SNQRG

σσ

⎛ ⎞⎛ ⎞⎜ ⎟= ⋅ = ⋅⎜ ⎟⎜ ⎟ ⎜ ⎟−⎝ ⎠ ⎝ ⎠

(90)

So, for a leakage noise contribution of e.g. less than -70dB, Ge_1 must be better than 0.9991. This is obviously almost impossible to achieve through analog design alone, a check of (76) should confirm that. To get higher than 10-12 bit resolution in a pipeline ADC, it needs digital gain error calibration.

5.2 The concept of gain error calibration Now that we have established the reasons for and consequences of gain error in pipeline ADCs, and shown that it is very difficult and power consuming to circumvent through analog design, we will look at the principle of digital gain error calibration. Conceptually, it’s very simple, as shown in fig.29. We simply add a digital scaling factor to the backend output before recombination and as such cancel out the first stage gain error.

backendStage 1

Ge_1

2

Y

X

Vout_1_idealVin_be

e1

2- ebe

l1

Figure 29: Principle of gain error calibration


As we can see, a calibration coefficient l1 is added to the digital backend output. Now, the output will be given by:

[ ] ( )1 1 _1 12 2 1be eY X e l e G l= ⋅ + ⋅ + ⋅ ⋅ − ⋅ (91) Now, if the calibration coefficient equals 1/Ge_1, (91) will simplify to:

[ ]12 beY X e l= ⋅ + ⋅ (92) And the first stage quantization noise error due to the gain error has been cancelled. A small penalty is paid, because the backend quantization error will be scaled by l1, which will be slightly larger than 1 (this is evident from looking at the gain error expression in (76)). This must be considered when designing the backend. This can be expanded to a chosen number of stages simply by adding more calibration coefficients like shown in fig.30. Then, for cancellation of each stage leakage, l1 must be given by 1/Ge_1, l2 by 1/Ge_2 and so forth, which can easily be found by doing the analysis in (91)-(92) on the basic expression from (66), including the gain error and calibration coefficients.

X

Y

Calibrated backend

Stage 1 Stage 2 backendGe_1 Ge_2

l2l1

222

Figure 30: Principle for calibration of several stages.

This all seems very simple. The problem however, is that the gain errors are analog quantities and may also be time varying due to OTA gain drift with temperature and aging. The main challenge in pipeline gain calibration is actually to measure the gain errors and so be able to determine the calibration coefficients. Various techniques have been proposed and these constitute a significant part of the curriculum in the course. They are generally divided into three fundamental principles or approaches that will be reviewed in the following sections.


5.3 Approaches to gain error calibration The approaches to gain error measurement and calibration can be divided into three basic principles: Foreground calibration, background calibration and measurement with a parallel ADC.

5.3.1 Digital foreground calibration In digital foreground calibration [5], the ADC is taken out of operation for the calibration process. A digital test signal Ts is added to the input of the stage DAC and to the digital stage output while the analog input is set to zero as shown in fig.31.

backendStage 1

Ge1

Y

e1

2- ebe

2

l1

Ts

Processing

Figure 31: Principle of forground calibration

Now, assuming no offset, e1 is zero and the output will be given by:

_1 1 12 2s s e beY T T G l e l= ⋅ − ⋅ ⋅ ⋅ + ⋅ (93) If l1=1/Ge_1, the first two terms will be zero and the only energy on the output is the small backend error. Hence, by applying a large energy (full swing) test signal and adjusting the calibration coefficient until the output energy is minimized will eliminate the gain error. This can be done at a fixed interval to compensate for drift. However, the problem is that the converter must be taken out of operation for the calibration process. This is in many cases not acceptable as it will lead to missing data. Many applications will not tolerate data loss.


5.3.2 Digital background calibration This problem is eliminated when using digital background calibration [2], [6]-[10]. In this case a test signal is applied to the stage DAC under operation, as shown in fig.32. The test signal must of course be relatively small compared to the input signal, so the input range available for the signal is not compromised too significantly. Now, the output signal will be given by:

[ ] ( ) ( )1 1 _1 1 _1 12 2 1 1be e s eY X e l e G l k T G l= ⋅ + ⋅ + ⋅ ⋅ − ⋅ + ⋅ ⋅ − ⋅ (94) Now, the test signal is included in the output if there is a gain error. If the last term is zeroed out, the gain error is eliminated. However, also present on the output is the unknown input signal and first stage and backend quantization errors. To be able to measure the last term alone, it must be extracted digitally from the output data.

backendStage 1

Ge_1

Y

X

e1

2- ebe

2

Ts

k

k -

l1

Figure 32: Principle of digital background calibration

To be able to do this, one must employ a test signal that is uncorrelated with the input signal and quantization errors. In other words, the digital test signal Ts should be a random noise source. Then, the expectance value sE T X⋅ equals zero and the same also applies for the test signal multiplied with the quantization errors since the test signal is independent of the first stage quantizer and dithers the backend quantizer. Hence, from (94) we get:


[ ] ( ) ( )

( ) ( )

1 1 _1 1

_1 1

2_1 1

2_1 1

2 2 1

1

1

1

s be s e s

s e s

e s

e s

E Y T E X e l T E e G l T

E k T G l T

E k G l T

k G l E T

⎡ ⎤⋅ = ⋅ + ⋅ ⋅ + ⋅ ⋅ − ⋅ ⋅⎣ ⎦

⎡ ⎤+ ⋅ ⋅ − ⋅ ⋅⎣ ⎦

⎡ ⎤= ⋅ − ⋅ ⋅⎣ ⎦

= ⋅ − ⋅ ⋅ ⋅

(95)

This is the power of the test signal scaled by the gain error, exactly what we want to make zero by adjusting l1. So if we can extract this term, we can adjust the calibration coefficient until it is minimized. This is done using a correlator, as shown in fig.33. The correlator is simply a multiplier-accumulator (MAC) that sums multiplication values of Y and Ts over a long period, called the block length BL. The output of the correlator is given by:

( )1

L

sBL

C Y TB

= ⋅∑ (96)

And it is obvious that:

, s LC E Y T B→ ⋅ → ∞ (97)

backendStage 1 Ge_1

2

Y

X

Vout_1_idealVin_beTs

l1

k

Correlator

C

Figure 33: Test signal extraction using correlator

So, we can measure the correlator output C over a long block length and adjust l1 to minimize it. Of course, for each adjustment of l1, a new measurement must be made, so the adjustment of the calibration coefficient follows the gradient of the correlator output, it is adjusted in the direction that made the current error energy smaller than the last.


The main problem with background gain calibration is that for the calibration to be accurate, i.e. for (97) to be asymptotically correct, the block length must be very, very long. The calculation of the required block length for a given accuracy is tedious and will not be reviewed in this document (see [2] for details), but can for even a modest 10-12 bits resolution be found to be several million samples. Of course, if the test signal scale factor k is small, the last term in (95) is small, and it takes the system longer time to converge, so this will be a trade-off between shorter block length and larger useable input range. A much used value for 1.5-bit stages is k=1/4, which will constrain the input range as seen by the in-out relation in fig.34, with the test signal as a random variable of maximum width 1/4.

X

2e1

4ref−

4ref

2ref−

2ref refref−

ref−

2ref−

2ref

ref

Figure 34: Stage transfer function with test signal, k=1/4.

So in summary, background calibration allows for continuous operation, but works very slowly. Especially if there is a sudden change in gain error, e.g. due to a sudden temperature change, the ADC will use a long time to recalibrate and regain its calibrated SNDR. It will also use very long time from start-up until good coefficients are found and thus good SNDR achieved. A recently patented method [11] however solves the latter issue by upon start-up initializing a separate foreground calibration routine and then switch to background calibration when the start-up sequence is completed.

5.3.3 Calibration with parallel reference ADC The third approach tries to overcome both the problem with foreground calibration having to take the ADC out of operation and the problem with the slow convergence of the background calibration. Here, the method is simply to use a very accurate parallel ADC to measure the gain error of the main ADC [11]-[12] as shown in fig.35. Of course, this parallel “support-ADC” will need very high resolution, since it is to measure a very small error and moreover


has to have only negligible gain error itself. However, since calibration needs to be done only once in a while, it can run very, very slowly and still use little power.

Y

X%

e%

Figure 35: Error calibration with reference ADC

The principle is shown in fig.35. The input is routed to the main ADC, running at full speed, as well as a reference ADC running at a much lower sampling rate. The output from the reference ADC is assumed to be a very accurate representation of X, due to the high resolution of the reference converter. The main output is subtracted from this to produce an error estimate e% . The gain error calibration filter is then adjusted to minimize e% . The advantages of this approach are obvious. The main ADC can be run continuously and the error is computed on the fly, at the reference ADC sampling rate, and needs not to be accumulated over a long block length as for the background calibration. The reference ADC can be a high resolution ADC, e.g. a sigma-delta converter, operating at a very low rate for low power consumption. The disadvantage is however as obvious as the advantage. The reference ADC, having to be very accurate, will use a lot of chip area, increase analog design complexity and generally create significant analog overhead. However, if neither pauses in operation or long convergence time is acceptable, it is at present the best alternative.


[1]: S.H.Lewis: "Optimizing the Stage Resolution in Pipelined, Multistage Analog-to-Digital Converters for Video-Rate Applications", IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing, vol.39, pp.516-523, August 1992. [2]: J.Bjørnsen: “Design of a High-Speed, High-Resolution Analog to Digital Converter for Medical Ultrasound Applications”, PhD thesis, NTNU, ISBN 82-471-6989-4, 2005. [3]: I.Løkken: “FE8114: High Resolution Audio DACs – Final Report”, ch.6: “The DAC and Dynamic Element Matching”, pp. 64-72, NTNU, August 2005. [4]: A.Vinje: “Digital Background Calibration”, FE8113 lecture presentation, 2006. [5]: U-K.Moon, B-S.Song: “Background Digital Calibration Techniques for Pipelined ADC’s”, IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, Vol. 44, No. 2, pp.102-109, February 1997. [6]: E.Siragusa, I.Galton: “A Digitally Enhanced 1.8-V 15-bit 40-MSample/s CMOS Pipelined ADC”, IEEE Journal of Solid-State Circuits, Vol. 39, No. 12, pp 2126-2138, December 2004. [7]: J.Ming, S.Lewis: “An 8-bit 80-Msample/s Pipelined Analog-to-Digital Converter With Background Calibration”, IEEE Journal of Solid-State Circuits, Vol. 36, No. 10, pp 1489-1497, October 2001. [8]: J.Keane et.al: “Background Interstage Gain Calibration Technique for Pipelined ADCs”, IEEE Transactions on Circuits and Systems-I: Regular Papers, Vol. 52, No. 1, pp 32-43, January 2005. [9]: J.Li, U-K.Moon: “Background Calibration Techniques for Multistage Pipelined ADCs With Digital Redundancy”, IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, Vol. 50, No. 9, pp 531-538, September 2003. [10]: K.El-Sanakry, M.Sawan: “A New Digital Background Calibration Technique for Pipelined ADC”, Proceedings of the 2004 International Symposium on Circuits and Systems, 2004. ISCAS '04, Vol.1, pp I.5-I.8, 23-26 May 2004. [11]: J.Bjørnsen: “Method and apparatus for start-up of analog-to-digital converters”, US Patent no.6.970.120, November, 2005. [11]: J.P.Keane et.al: “Digital Background Calibration for Memory Effects in Pipelined Analog-to-Digital Converters”, IEEE Transactions on Circuits and Systems I: Regular Papers: Accepted for future publication, Volume PP, Issue 99, pp 1-15, 2005. [12]: Y.Chiu et.al: “Least Mean Square Adaptive Digital Background Calibration of Pipelined Analog-to-Digital Converters”, IEEE Transactions on Circuits and Systems-I: Regular Papers, Vol.51, No.1, pp 38-46, January 2004.



Part III: Modern Techniques and

Current State of the Art In this part, we will take a look at some modern techniques and the state of the art in modern ADC design. It was important for the course to be up to date with the current advances in technology and this last part reflects this. The gain calibration techniques shown in part II do have shortcomings in terms of either speed or overhead. Modern research tries to overcome these shortcomings. We will look at the two-channel background calibration scheme which promises much faster convergence time. Also, the gain error calibration does not include non-linearity in the stage DAC transfer function, which will be a source of harmonic distortion in the pipeline ADC. Since the ADC systems are mostly fully differential designs, third harmonic distortion is most prominent, and expansion of the gain error calibration to correct for these will be introduced. We will also look at another secondary effect called the memory effect and calibration of this. Also, we have seen that high ADC performance demands fast OTAs with high gain and low noise. These circuits are very power consuming and uses most of the supply current in modern ADC systems. In today’s world of portable and battery operated electronics, good power efficiency is more important than ever before and the OTA is a major focus in this regard. A recently proposed scheme to remove the OTA from the pipeline stage altogether will be presented. It is currently at an early research stage, but looks very promising. Finally, some recent state of the art publications will be introduced to give the reader a feeling of where the current limitations are in terms of resolution, speed and FOM.


6 New calibration techniques As we have seen from the previous chapter, gain error calibration has fundamental limitations. Foreground calibration requires halts in operation, background calibration adapts very slowly and parallel ADC calibration generates significant analog overhead. In addition secondary effects like memory effects [1] and higher order distortion limit the accuracy even of perfectly calibrated converters. Recent techniques have however been introduced to try to overcome these shortcomings. We will look specifically at calibration of memory effects [1], the two-channel background calibration [2], which provides faster convergence than the basic background calibration routine, and calibration of non-linear stage DAC transfer functions [3]-[4].

6.1 Memory effects and memory effects calibration In high resolution converters, correction of direct gain errors may not be sufficient. A secondary effect, known as the memory effect, can then result in distortion that is significant [1]. Memory effects are due to capacitance dielectric absorption and relaxation, a phenomenon caused by charge being trapped in the dielectric and slowly being released over time. If a capacitor is charged to an initial voltage Vinit at t=0, then discharged from t=0 until t=t0 by shorting its terminals and then left floating, it should at any time 0ft t> ideally have zero charge and zero terminal voltage. However, due to dielectric absorption, charge remains in the dielectric and this will then gather back on the plates when the capacitor floats (relaxation), producing a non-zero output voltage:

0

ln fC init

tV k V

t⎛ ⎞

= ⋅ ⋅ ⎜ ⎟⎝ ⎠

(98)

In (98), k is a process dependent constant. For simplicity, we rewrite this as C initV Vγ= ⋅ where γ is given by (98). This is shown in fig.36, of course greatly exaggerated for illustrational purposes.


initVγ ⋅

Figure 36: Capacitor output voltage change due to dielectric absorption/relaxation

If one look at the operation of the stage DAC from fig.24, it is evident that this will affect the output voltage. At the end of the previous feedback phase, the feedback capacitors Cf are charged to [ 1] [ 1]out xV n v n− − − and the reference capacitors Cr to [ 1] [ 1]ref xy V n v n⋅ − − − . Repeating the steps (71)-(74), including the dielectric absorption/relaxation, we can then easily find that:

( )[ ] 2 [ ] [ ] [ 1] [ 1]out in ref e f out r e refV n V n y V n G V n G y V nγ γ= ⋅ − ⋅ ⋅ + ⋅ − + ⋅ ⋅ ⋅ − (99) Since Cf and Cr are identical type capacitors, we can assume f rγ γ γ= = . If we take the z-transform of (99), this gives:

( ) 1 1( ) 2 ( ) ( ) ( ) ( )out in ref e out e refV z V z y V z G V z z G y V z zγ γ− −= ⋅ − ⋅ ⋅ + ⋅ ⋅ + ⋅ ⋅ ⋅ ⋅ (100) After rearranging, (100) becomes:

1

1( ) 2 ( ) ( )1out in e ref eV z V z G y V z G

zγ −= ⋅ ⋅ − ⋅ ⋅−

(101)

Including this new term in the model for the first stage, and knowing that y=x+e we get the structure in fig. 37 as a model for the first stage.


backendStage 1

Ge_1

2

Y

X

e1

2- ebe

1

11 zγ −−

Figure 37: Model for analysis of first stage gain error and memory effects

Also the input S/H (“stage 0”) will have memory effects, but in this case, only the first term in (101) will be included in the output expression as it has no stage ADC. Expanding the model above to include stage 0, 1...N-1 (the final stage has no stage DAC), the output expression can be derived recursively since the stages operates successively in a pipeline (see [1] for details) and becomes:

1

1_ 10

_1 11 11

0

1( ) ( ) ( ) 1 ( )1 1

N

e l NNil

i e l beN Ni l i

k kk k i

GzY z X z E z G E z

z z

γ

γ γ

−

−−=

− −− −= =

= =

⎡ ⎤⎛ ⎞⎢ ⎥⎜ ⎟−⎢ ⎥⎜ ⎟= + ⋅ ⋅ − +⎢ ⎥⎜ ⎟− −⎜ ⎟⎢ ⎥⎝ ⎠⎣ ⎦

∏∑ ∏

∏ ∏ (102)

In (102), ( )iE z is the quantization error stage of i at time instant n. The first term of (102) can be seen to add a linear filtering operation to the output, introducing high frequency poles. The second term is the leakage or distortion component, dependent on previous output decisions and hence the input data. The third term is the backend quantization error. It should be noted that only memory effects from the second stage onwards contribute to the nonlinearity term (for N=1 the expression in the parenthesis cancels out to 1), so unlike for regular gain errors, where the first stage dominates, the second stage is the dominant source of memory effect nonlinearity. The memory effects can be eliminated expanding the normal gain error coefficients to include filters as shown in fig.38 for second stage elimination. The reader is recommended to go through the maths for the one-stage and two stage example to illustrate (102) and the calibration filter routine. The algorithms for measuring the effects will be the same as before, with [1] opting for the parallel ADC approach.


backendStage 1

4

Y

X

e1

2Ge_1

- ebe

11

11 zγ −−

Stage 2

e2

-1

2

11 zγ −−

2Ge_2

2

1

1

eG 2

1

eG

12

121z

zγ

γ

−

−−

Figure 38: Calibration of first and second stage gain error and memory effects

6.2 Two channel background calibration To reduce the long convergence time in background calibration, two channel calibration techniques have been proposed [2]. This principle is shown in fig.39.

SADC SDAC

+ BEAD

Processing

SADC SDAC

+ BEAD

X+

X-

Ts_1

Ts_2

2·Ge

2·Ge

Y

Y+

Y-

2

2

l1

l1

+

+

Figure 39: Principle for two channel background calibration

The idea is simple. Two identical ADCs process the input signal with opposite phase, denoted X+ and X-. The output Y is simply given by:


Y Y Y+ −= − (103)

The two test signals on the other hand, are uncorrelated. Thus, when extracting the gain error coefficient, we can simply sum the positive and the negative part and we have eliminated the signal component from the expression. If we assume the structure from fig.32, we get for the positive and the negative part:

[ ] ( ) ( )1 1 _1 1 _1 _1 12 2 1 1be e s eY X e l e G l k T G l+ + + += ⋅ + ⋅ + ⋅ ⋅ − ⋅ + ⋅ ⋅ − ⋅ (104)

[ ] ( ) ( )1 1 _1 1 _ 2 _1 12 2 1 1be e s eY X e l e G l k T G l− − − −= ⋅ + ⋅ + ⋅ ⋅ − ⋅ + ⋅ ⋅ − ⋅ (105)

This gives the sum:

( ) ( ) ( )1 _1 _ 2 _1 11be be s s eY Y e e l k T T G l+ − + −+ = + ⋅ + ⋅ + ⋅ − ⋅ (106) Now, the only term needed to be correlated away is the very small backend error. Hence, this algorithm will very quickly converge. Of course, equations (104)-(106) requires for the two channels to be perfectly matched, which can not be achieved in practice, but still, the disturbing component in the output expression will be many orders of magnitude smaller than for the single channel approach. If the mismatch is 1%, cancellation will be 99%. Looking at fig.39, it looks as if the complexity is being doubled by using this approach. This is however not the case. Remember that this is basically a differential system. The number of comparators is doubled and the digital logic is a little more complex, but the stage DAC, which is by far the largest and most power consuming component, is about the same since differential design can be employed. With some additional digital circuitry, one can also calibrate the P-channel and N-channel separately [2].

P-channelADC

N-channelADC

Ge-filter

Ge-filter

+

Σ

Σ

X+

X-

Y+

Y-

Y

Corr

Ts_1

Ts_2

Ts_1

Ts_2

Figure 40: Conceptual implementation, two channel calibration


6.3 Calibration of stage DAC non-linearity In addition to static gain error as reviewed in chapter 5.1, the stage DAC transfer function may also suffer from non-linearity. This means that the gain error is dependent on the input level, in other words that the gain error is a function of the input, Ge(x). This is a direct result of non-linearity in the OTA. A stage DAC transfer function with nonlinear gain error is shown in fig.41. Since we are here dealing with differential OTAs, we can assume the distortion to be symmetric. This means the transfer function non-linearity will consist of odd functions of the amplifier input, i.e. that the transfer function is given by g1x+g3x3+g5x5… Furthermore, it is for normal OTAs likely to be dominated by output compression and consequently the cubic term dominates, while higher order distortion will be negligible [3]. This means the linear and non-linear gain error can be approximated fairly precisely through the first and third order components only. It will certainly be more precise than only the linear term.

x

2·e1

4ref−

4ref

2ref−

2ref refref−

ref−

2ref−

2ref

ref

Figure 41: Stage DAC transfer function with non-linear gain error.

Since the distortion is a result of output compression, the third order term can be modelled at the output of the stage just like the linear gain error. Fig.42 shows the cubic distortion component appended to the stage model from fig.28.


backendStage 1

g1

2

Y

X

Vout_1_ideal

Vin_be

e1

2- ebe

g3^3

Figure 42: Model for analysis of first stage gain error including third order nonlinearity term

The calibration of this is conceptually quite straightforward, as shown in fig.43. As can easily be found with the basic analysis from chapter 5.1, the errors will cancel if l1=1/g1 and l3= 1/g3.

backendStage 1

g1

2

Y

X

Vout_1_ideal

Vin_be

e1

2- ebe

g3^3

l1

l3 ^3

Figure 43: Conceptual calibration of first and third order nonlinearity error

However, implementation of cubic distortion calibration is rather complex. First of all, it requires the computation of the digital cube in the output filter. This will require a lot of


computations and, if the converter is running at very high speed, it will contribute greatly to digital complexity and power consumption. Furthermore, if using background calibration, the third order term will be very small, and thus take very long to correlate out on the output. The l3-component will thus converge even slower than the l1-component.

7 Comparator dithering As we have seen in previous chapters, the dither signal is applied to the DAC scaled by a factor k. Usually in 1.5-bit systems, k=1/4. This is achieved through a separate dither capacitor, as shown in fig.44.

+

+-

-

A

Cr

CrinV+

-outV+

-

Cf

Cf

VCMs refT V⋅

+

-

Cd

Cd

Figure 44: Stage DAC including dither capacitor This means that there in reality will be mismatch between the dither capacitor and the other capacitors, which leads to an error in the dither gain and consequently an error in the calibration result. Furthermore, if k=1/4, the dither capacitor Cd is only one fourth the size of the reference and feedback capacitor. To get good enough matching with such a small capacitor, it might be that the other capacitors have to be made bigger than kT/C-requirements dictate. This would lead to an increase in power consumption. These problems can be relieved by comparator dithering, or randomly varying the comparator threshold level [2]. The noise is now added at the input of the stage ADC, rather than the output, but as can be seen from fig.31, the stage equivalent will be the same.

inV

outVsT

4thV ∆−

4thV ∆+

Figure 45: Comparator dithering

Of course, there may also be deviations in the threshold voltages, leading to similar errors, but these do not depend on matching of such small unit sizes.


8 OTA-less, comparator based stage DAC From the analysis of non-idealities in previous chapters, we have seen that many practical limitations are given by the stage OTA. Its open-loop gain determines the gain error and memory effect, its input noise largely decides the SNR and its bandwidth largely determines the settling behaviour. To design OTAs with good performance for all these parameters is difficult and often results in large power consumption. Furthermore, with new deep submicron processes, the supply voltage has scaled down much faster than the threshold voltage, making it more and more difficult to design OTAs. Especially high-gain is difficult to achieve in modern technologies, since the low voltages hampers the use of cascode transistors. In [5] an approach is suggested where the OTA is removed altogether, and replaced with comparators and current sources. This principle is shown in fig.46. The figure shows two successive stage DACs, one in the feedback phase and one in the sampling phase. As can be seen, the configuration and operation of the stage DAC is otherwise identical.

+

-

outVCr

refy V⋅

+

-

Cf

1I

2ICr

Cf

1I

2I

SCMVCMV

Stage 1 DACfeedback phase

Stage 2 DACsampling phase

CMV

xV

2inV

Figure 46: Stage DACs using comparators and current souces.

In the sampling phase, the input voltage is sampled onto the capacitors Cf and Cr, as seen for the second stage. Next, when the stage shifts to the feedback phase, the output Vout is momentarily reset to ground to ensure Vx starts below the common-mode. This ensures the comparator output is zero at the start of the feedback phase. Then, the current source I1 is turned on and Vx increases as a ramp towards VCM while Vout increases towards Vin. Due to the charge redistribution, Vx will reach VCM as Vout reaches Vin. When Vx passes VCM, the comparator changes decision and I1 is turned off. Because of comparator delay, there will be an overshoot, which is compensated for by the smaller I2. This is turned on, VX sinks towards VCM and once it passes it, the comparator turns off again, this time with a much smaller overshoot due to the slower voltage ramp. At this instant, the output voltage equals the sampling phase input voltage and is sampled onto the next stage through the switch seen for the second stage in fig.46. A timing diagram of Vx and Vout is shown in fig.47. The I1-phase can be seen as coarse detection and the I2 phase as fine detection. This is necessary to ensure fast operation (fast voltage ramp) and good accuracy (little over- or undershoot).


Figure 47: Comparator based stage DAC in feedback phase

While a regular OTA switch cap stage forces the common mode voltage to enable input voltage detection, the comparator based stage detects it. This is a more energy efficient approach. The critical component now is the comparator, since it needs high gain and very low delay to minimize undershoot at the sampling instant. However, unlike OTAs, comparators can be cascaded to achieve high gain. They are thus much easier to implement in low-voltage processes. This approach is at an early stage, but promises a high potential for improving FOM. In [5], a 10-bit, 8MHz test ADC in 0.18µm CMOS is reported to achieve 0.3pJ/cs without any power optimization or stage scaling.

9 Pushing the FOM – state of the art performance In this final chapter of the report, we will take a brief look at some recently published examples to give the reader a feeling of the current state of the art. This should provide the reader with a notion of where the cutting edge technology is at the moment. First, we will look at a 1GS/s, 11b time-interleaved ADC in 0.13µm CMOS [6]. This architecture uses N time interleaved sub ADCs each running at 1/N of the sampling rate. The architecture is specially optimized to eliminate effects of mismatch between the channels and it uses a multi-channel error correction algorithm. The basic architecture and some performance measurements are shown in fig.48.


Figure 48: Architecture and performance data, 1GS/s, 11b ADC [6]

The converter achieves 58.6dB peak SNR and 55dB peak SNDR for 9.1ENOB performance. The effective resolution bandwidth is 400MHz with SNDR then at 52dB. The converter is implemented fully in 0.13µm CMOS running of 1.2V and 2.5V supplies and its 250mW power consumption means a FOM of 0.5pJ/cs. The ADC presented in [7] is a realization in 90nm operating from a single 1.2V supply. This ADC operated without gain error calibration and presents the state of the art of what’s possible with conventional approaches. Its performance is achieved using a carefully designed two-stage Miller-compensated OTA with 65dB open-loop gain.

Figure 49: Architecture and performance measurements, 100MS/s, 10b, 90nm ADC [7]


As can be seen, the first stage is 2.5-bit (5-level) and designed the most accurate. The rest of the stages are scaled by 0.25, meaning they use 0.25 times the sampling capacitance for lower area and power consumption. As is now known, the first stage is of course the most critical. The achieved SNR is 58.5dB with a dynamic range of more than 65dB. Totally, noise and distortion limits the resolution to 9.3 ENOB. The effective resolution bandwidth is 100MHz and the sampling frequency programmable over a range of 25-120MS/s. The FOM is 0.5pJ/cs. In the low-power segment, an ADC published in 2006 [8] achieved a figure of merit of 0.3pJ/cs in 0.18µm CMOS using a special power saving technique called opamp current reuse. This circuit uses an N-channel input stage OTA for the first two stages and a P-channel input stage OTA for the two last. As such, two and two stages can use stacked OTAs and hence share the same bias current. Also, when the N-channel DACs from stages 1 and 2 sample the input, the P-channel OTAs serve as their active load to boost the gain. The opposite is the case when stages 3 and 4 sample. This principle is shown in fig.50.

Figure 50: Opamp current reuse principle [8]

This converter is realized in 0.18µm and operates at 10 bits and 50MS/s. The ENOB is 9.2 bit and 8.8 bit for 1MHz and 20MHz input respectively. SFDR is 70dB and power consumption a mere 18mW, meaning the FOM is around 0.3pJ/cs. This is achieved without digital calibration and shows that smart analog design can also go a long way. In the high resolution segment however, gain error calibration is now a necessity. The publication in [9] shows a 15-bit, 40MS/s Pipeline ADC realized in 0.18µm CMOS. It uses 9-level stages with dynamic element matching and real-time background gain calibration to achieve 90dB SFDR. The architecture is shown in fig.51.


Figure 51: Architecture, 15-bit gain-calibrated ADC [9].

The gain error calibration (GEC) logic is a normal background calibration routine like we analyzed in section 5.3.2, where a test signal is inserted and extracted in real-time at the output using a correlator as shown in fig.33. As can be seen from fig.51, the first three stages have GEC and dynamic element matching, using an algorithm called DAC Noise Cancellation (DNC). Dynamic element matching has not been reviewed in this report, for a general analysis the reader is referred to [10] and for specifics on the DNC algorithm to [9]. The application of GEC and DNC improves the performance tremendously. Without gain error calibration, only 70dB SFDR can be achieved despite a well dimensioned analog design that uses more than 340mW. With post processing enabled, the SFDR increases to 90dB. The SNR is 72dB across the entire nyquist band. Total digital power consumption is at 51mW only a fraction of the analog consumption. To achieve this performance from analog optimization alone would be almost impossible and require many times higher area and power consumption.

Figure 52: Power spectum with gain error calibration disabled (left) and enabled (right) [9].


[1]: J.P.Keane et.al: “Digital Background Calibration for Memory Effects in Pipelined Analog-to-Digital Converters”, IEEE Transactions on Circuits and Systems I: Regular Papers: Accepted for future publication, Volume PP, Issue 99, pp 1-15, 2005. [2]: J.Li, U-K.Moon: “Background Calibration Techniques for Multistage Pipelined ADCs With Digital Redundancy”, IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, Vol. 50, No. 9, pp 531-538, September 2003. [3]: J.Keane et.al: “Background Interstage Gain Calibration Technique for Pipelined ADCs”, IEEE Transactions on Circuits and Systems-I: Regular Papers, Vol. 52, No. 1, pp 32-43, January 2005. [4]: B.Murmann, B.E.Boser: ”A 12-bit 75-MS/s Pipelined ADC Using Open-Loop Residue Amplification”, IEEE Journal of Solid-State Circuits, Vol. 38, No. 12, pp2040-2050, December 2003. [5]: T.Sepke et.al: “Comparator-Based Switched-Capacitor Circuits for Scales CMOS Techniques”, ISSCC2006, Session 12, Paper 12.4, pp. 220-221, February 2006. [6]: S. Gupta et.al: “A 1GS/s 11b Time-Interleaved ADC in 0.13µm CMOS”, ISSCC2006, Session 31, Paper 31.6, pp. 576-577, February 2006. [7]: G.Geelen et.al: “A 90nm CMOS 1.2V 10b Power and Speed Programmable Pipelined ADC with 0.5pJ/Conversion-Step”, ISSCC2006, Session 12, Paper 12.1, pp. 214-215, February 2006. [8]: S.T.Ryu, B.S.Song, K.Bacrania: “A 10b 50MS/s Pipelined ADC with Opamp Current Reuse”, ISSCC2006, Session 12, Paper 12.2, pp. 216-217, February 2006. [9]: E.Siragusa, I.Galton: “A Digitally Enhanced 1.8-V 15-bit 40-MSample/s CMOS Pipelined ADC”, IEEE Journal of Solid-State Circuits, Vol. 39, No. 12, pp 2126-2138, December 2004. [10]: I.Løkken: “FE8114: High Resolution Audio DACs – Final Report”, ch.6: “The DAC and Dynamic Element Matching”, pp. 64-72, NTNU, August 2005.



Summary

As a review of the course FE8113 – High Speed Analog to Digital Converters, this report has attempted to summarize the key points of the course content. Focus has been on writing a report that can give the reader a good understanding of ADC fundamentals, implementation limitations, the case for gain error calibration and an overview of the state of the art; - exactly what my own objectives were for taking the course. As a consequence, emphasis has not been on details and implementation specifics from the various publications in the curriculum, but rather on a complete and general understanding of the various topics and challenges. To write this report has been a very instructive process as it has been necessary to break down the curriculum and then rebuild it in a unified manner. Different authors use different notations and different models for illustration. To create a report that gives a coherent presentation of the course topics, and not just loose excerpts from different publications, has thus been challenging task, advancing my own understanding of the subjects. It is my hope that the report has managed to communicate this and that the reader after reading it will get an overview and an understanding of the topics it treats and an insight into the challenges of modern ADC design.

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FE8113 - High Speed Analog to Digital Converters, Final Report