Fermi lab TM-1079

0818.000

A MICROPROCESSOR BASED MADC TEST FACILITY

K. Seine

December 1981

1. Introduction

A new multiplexed ADC was designed and constructed back in 19791 •

However, because of budgetary constraints and manpower shortage, we

had not produced any beyond five units. Recently, we constructed

fifteen units, and we will build twenty-five or forty-five more units.

Each units has 192 connections at the input. If there are some

faulty connections, how can we detect and locate them quickly and

efficiently? How can we adjust the offset and gain on the ADC fast

and without frustration? These questions motivated the author to

implement a microprocessor based test facility. A graphic display

greatly eases pains in adjusting the offset and gain of the ADC.

The author thinks this is only the first generation, and he

intends to try and improve it through experience.

2. Test Method

2.1 Basic Check

The MADC units are assembled by an outside subcontractor.

When the units are delivered, the following basic functions are

checked out.

1. Check and adjustment on power supply voltages.

2. Check and troubleshoot on controls and displays.

3. Check on one of four MUX cards.

4. Check and adjustment on amplifiers and sample/hold.

5. Rough adjustment on ADC.

After the basic functional check, the units can be locally

and remotely controlled, and they can digitize and display analog

signals at least on a few channels with a moderate accuracy.

2.2 Basic Tests

Prior to computer aided tests, we document several

characteristics, i.e., (~) rough linearity, (2) DC common mode

rejection, (3) AC common mode rejection, and (4) channel cross

talk.

The amplifier has been properly adjusted and it performs well

with reasonably accurate offset, gain and common mode rejection.

The sample/hold and the ADC have been adequately adjusted. The

unit as a whole appears to be functioning and it produces

reasonable readings. We are now ready to do computer aided tests.

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2.3 Computer Aided Tests

The first thing that comes across our mind is that there are

many physical connections through the input arrangement, i.e.,

connectors, cables and MUX cards. There are sixty-four

differential channels each of which has Hi, Lo, and shield, and

therefore we deal with at least 192 connections. If there is

something wrong with any one of these connections, how can we

detect and locate it quickly and efficiently?

Another thing is how can we adjust the offset and gain on the

ADC?, and how can we know whether the ADC performs as it is

specified or not? In order to answer these questions, the author

introduced a graphics display. When the operator adjusts the

offset and gain, he can watch and tell how much the linearity

curve changes as he turns the potentiometer. When he finishes

with the adjustment, he can watch and tell how good the linearity

is on the graphic display.

2.3.1 Channels and their interaction tests

A channel should be properly selected and isolated from

other channels. A signal should come through the channel and

it should be accurately digitized. On our test facility, we

implemented two test programs, i.e., MINTSl and MINTS2.

Fig. 2.1 shows how to run the MINTS! program on a CRT

terminal. First, the operator makes certain whether Source B

on an input switching unit has normal polarity or not. He

then specifies a channel group and a reference value. The

input switching unit connects only one channel to the

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reference and ties the other channels to ground during a

cycle. It switches from one channel to another as the cycle

advances from one to another. As it is shown in the figure,

Channel O is selected in Cycle 1, Channel 1 in Cycle 2,

Channel 2 in Cycle 3, etc •••• , and it continues until Channel

15 is selected in Cycle 16. In this test, only the selected

channel should have the voltage. If unselected channels have

some voltage, there may be miswiring or short circuits. Or,

if the selected channel does not have the voltage, there may

be open wires or ground short circuits. If the operator

selects the other channel groups, he can test all of the

sixty-four channels.

Figure 2.2 shows how to run the MINTS2 program on a CRT

terminal. Differing from the previous program, this program

allows the operator to specify the channel pattern. In the

figure, an alternate pattern (AAAA in Hex) is selected. By

manipulating the channel pattern, the operator can further

diagnose the problem that has been found in the previous test.

2.3.2 Input protection test

The input circuit of all of the channels has to be

protected from accidental application of a high voltage. Each

one of the connections that are needed for the sixty-four

differential channels is protected by two diodes and a series

resistors. For the test, we use a mechanical switch box and a

power supply instead of the programmable input switching unit

and the DAC. Figure 2.3 shows how to run the MINTS2 program

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for this particular test. The operator specifies the channel

group, and he can put an arbitrary number on the channel

pattern and reference, such as FFFF or XXXX. In the figure,

each pair of the input wires of the sixteen channels are

connected to a common voltage (Ecm in Figure 2.3). When

Ecm=+lOV, the amplifier is in a linear range and it can reject

the voltage that is commonly applied to the Hi and Lo wires of

the channels. Therefore, all the readings are nearly zero.

When Ecm is increased to +lSV, the amplifier is in saturation

and the input to the multiplexer is approaching the supply

voltage. All the readings shown resulted from the imbalance

between Hi and Lo connections. When Ecm is increased to +17V,

protection diodes start to conduct. We repeat these with E cm in negative voltages. If all the readings that have been

taken are reasonably small, we deduce that all the protection

circuits function properly.

2.3.3 Linearity tests

A graphic display greatly eases pains in adjusting the

off set and gain of the ADC and allows us to examine the entire

linearity curve at a glance.

(1) Linearity (Regular)

The operator invokes a command file called MLNTS2 on his

terminal. He then enters type of linearity, channel number

and delay. He selects 'Linearity (Regular)' by entering RLA.

In a second or so, the graphic display will have a picture

like the ones shown in Fig. 2.4. The horizontal axis shows

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the reference voltage in a linear scale, and the vertical axis

shows the different between reference and ADC reading. There

are twenty-one data points starting from -lOV up to +lOV.

Figure 2.4(a} shows a curve when gain is too high. A half

turn adjustment on the gain potentiometer gives us a curve

like the one shown in Fig. 2.4(b). If the operator selects

repeat mode, the program repeats digitization and updating of

display. Therefore, he can adjust the gain potentiometer as

he watches how much the linearity curve is affected. He can

do the same thing with the offset adjustment. With this

graphic display, we now feel that we have a search light in

the dark.

(2) Linearity (Differential)

After invoking a command file called MLNTS2, the operator

selects 'Linearity (Diff.}' by entering DFL. In a second or

so, the graphic display will have a picture like the one shown

in Fig. 2.5. The horizontal axis shows the reference voltage

in a binary scale, and the vertical axis shows the difference

between reference and.ADC reading. There are twenty-four data

points, i.e., -10.24, -5.12, -2.56,----0----, 2.555, 5.115 and

10.235 (V), or 100000000000, 110000000000, 111000000000,

------------, 000000000000, --------, 000111111111,

001111111111 and 011111111111 (Binary) •

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3. Hardware

3.1 Microcomputer and Peripherals

We purchased card cages, chassis parts, a power supply and

cards in order to construct a Multibus-based microcomputer shown

in Fig. 3.1. Monolithic Systems' MSC8004 Z80A based CPU board is

the heart of the computer. There ae 32K byte on-board RAM and 32K

byte off-board RAM. The Z80A communicates with TEC501 terminal

via on-board serial I/0 interface. A home made disk control board

handles two double sided disk drives, Shugart Associates' SASSO.

Matrox Electronic Systems' MSBC-512 graphic control board, which

has a resolution of 256x256, drives Shibaden's VM904U video

monitor. Kinetic Systems' 5110 interface board drives Kinetic

Systems' 3908 crate controller.

3.2 MADC Test Setup

A CAMAC crate based test setup is shown in Fig. 3.2. Analog

Devices' DAC1136K high resolution 16 bit DAC is housed in a

chassis. It is optically isolated from the digital environment at

the input, and it is buffered by Analog Devices' 234K chopper

stabilized amplifier at the output. The chassis has its own power

supply, which can be left on for stable output. The input

switching unit has 16 solid state, sing.le pole-double throw

swiches, which connect the MADC channels to either Source A or

Source B. Source B can be selected to either Norm or B=-A. When

it is selected to B=-A, Source B will have the reversed polarity

of and the same amplitude as Source A. The unit is also optically

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isolated from its controller and is self-powering. This unit is

replaced with a mechanical switch box when the input protection

test is carried out. All of the controller cards that reside in

the CAMAC crate are home made, except the crate controller.

4. Software

4.1 System Software

COOS (Cromemco Disk Operating System) is the disk operating

system. It is a single-user, single-task operating system for

disk file management. COOS occupies memory from Location 0

through lOOH as well as approximately BK bytes of memory above the

user area {High Memory). CDOSGEN allows COOS to be built around

the user's particular hardware configuration and software needs.

It supports up to 64K bytes of memory in lK blocks and any

combination of up to four 8" and 5" disk drives. COOS utility

programs are (1) BATCH, (2) DUMP, (3) INITIALIZE, (4) STATUS, (5)

WRITE SYSTEM, (6) TRANSFER, (7) SCREEN EDITOR, and (8) TEXT

EDITOR.

FORTRAN IV is a comp!ete implementation of ANSI standard

FORTRAN X3.9--1966, except that there is no complex data type and

that specification statements must appear in a specific order.

The FORTRAN IV Compiler produces relocatable code and FORTRAN

program modules can be linked with the code produced by the

relocatable assembler.

Z80 MACRO Assembler is a two pass assembler which reads

source code from a disk file, assembles it, and produces listings

and an object file either in relocatable or in Intel hex format.

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LINK, relocating linker/loader, loads and links separately

assembled modules as desired at run time. These modules may

include FORTRAN library routines as well as those generated by the

FORTRAN compiler. The linked machine code can then be saved in a

disk file for execution.

DEBUG allows machine language programs to be traced,

disassembled and patched, and it allows the operator to establish

break points, display and alter the zao registers, and initiate

normal or step by step program execution.

4.2 Program Example

All of our test programs are written in FORTRAN IV.

MINTS2.FOR is shown as a program example in Fig. 4.1. There are

many subprogram calls in this program. However, in order to

illustrate how parameters are passed between ttte main program and

a subprogram, a subprogram named Cl26DA is shown in Fig. 4.l(b).

The subprogram call is made at one line below Line 110 of the main

program. The subprogram has two parameters, i.e., ICDI and ICDO.

ICDI and ICDO are passed by (HL) and (DE) respectively, between

the main program and the subprogram.

At the end of the program, the operator is allowed to

intervene and select a mode. He has four choices, i.e., (1) C

(Continue) repeats another cycle with the same parameters, (2) N

(New) starts another cycle with new parameters, (3) R (Repeat)

repeats the number of cycles specified, and (4) S (Stop) stops the

execution of program. The author has found this feature is

convenient and useful, and he is in the habit of using this

~ -

feature in any program that he writes.

5. Conclusion

Computer aided tests on the MADC units have just begun, and our

present implementation is far from being complete. We intend to try

and improve it by learning from experience. One thing that we know

right from the start is that we have an input switching unit for 16

channels but not for 64 channels. We ought to construct one soon.

6. Acknowledgement

I am grateful to Timothy Gierhart and Richard Klecka for their

efforts on the construction of the test facility. Thanks are also due

Walter Knopf for his contribution of CDOS and utility programs to the

test facility.

References

1. A New Multiplexed ADC Unit, K. Seino, TM-931, 1979.

2. MSC8004 user's Manual, Monolithic Systems Corp., 1978.

3. 32K-128K Dynamic RAM Board Manual, Central Data Corp., 1980

4. MSBC-512 Graphic Display Board Manual, Matrox Electronics, 1978.

5. Model 5110 Multibus Adapter Manual, Kinetic Systems Inc., 1980.

6. Model 3908 Crate Controller Manual, Kinetic Systems Inc., 1979.

7. SASS0/851 OEM Manual, Shugart Associates, 1977.

8. Series 500 Terminal Manual, TEC Inc., 1978.

- lQ -

9. CDOS Instruction Manual, Cromemco, Inc., 1978.

10. FORTRAN IV Instruction Manual, Cromemco, Inc., 1979.

11. Macro Assembler Instruction Manual, Cromemco, Inc., 1978.

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"l. I i'·I 7 5 l

.-.. ,,,. ..... " :NPU7 SVITCH UNl7 . SGl;RCE B = NORM 0 <YIN) :Y

SELE:T CHANNEL GROUP - 3 4 : ..!. " -El-!7E?. EC'EF.t:NC:E 1'.:AliGING FRON -~043 TO Zi.i-t7 < () 0 0

•:Y:I.E = . CHANi~EL ·:.ROiJP = J.

J. 4 ~ 0 7 - . ~

l ~ . Q >) o . av ·) . JD D . C 0 •. OG (; . 0 0 G 00 0. 0 0 Q G -~ :

1 • 0 0 D . C: 1} 0' (i 0 0 . G Q 0. 0 0 000 0. Q 0

3 ~ 10 d 12 13 14 1:;

\:YCLE = ' CHANNE!. CROUP = l . l ~ 3 4 5 6 7

J .00 s. sa O.uG 0.00 \) . 0 0 0.00 Ci . 0 0 0.00 C . G ·'.l a 00 0. 0 0 0.00 0.00 0.00 0. (i G -.01

9 10 11 12. 13 14 15

SYC:.E = 3 CHANNEL GROUP = .:. Q l z 3 4 5 : 7 :.oo 0.00 ii. 99 .00 () . 0 0 0.00 0 00 0.00 0.00 Ii. G G G. 0 Q 0.00 0. 0 0 0.00 0 00 G. 0 0 s 9 10 11 12. 13 14 15

CY Ci:.E = .. CHANNEL GROUP = .. a l z 3 4 5 6 7 0 00 () 00 0 00 9.99 .00 0.00 0.00 0.00 u. 0G - 01 - . Q 0 - 00 - 00 -.00 - o o -.00 s :; 10 11 12 13 14 15

CYCLE = s CHANNEL GROUP = l 0 l " 3 4 5 6 7 Q '() 0 0.00 0 . DD 0.00 9. 99 0 ' () 0 0.00 0.00 0.00 0. 1:, 0 0.00 0.00 0.00 0.00 o. oo ii. 0 0 a 9 10 11 12 13 14 15

CYCLE = 6 CHANNEL GROUP = l 'j l " 3 ... 5 6 7 0. 0 0 'J. 0 0 0.00 0.00 D.00 9. 9 9 0.00 o. a o : . () \} 0.00 ::i. 0 0 0.00 0. 0 0 ii.() 0 Q. 0 0 - 0-1 e 9 10 11 lZ 13 14 15

GYCLE = 7 CHANNEL GROUP = l Cr l " 3 4 5 & "T

- J 0 0 00 Q ' 0 0 o . o o il . Q 0 0.00 3. 99 0. 0 D G G J 0 . 0 (i () QQ \}. 0 (j 0.00 Q.00 Q.00 0. 0 0 2 9 : Q l l lZ 13 14 15

CYCLE = . CHANNEL GROUP = 0 l z 3 4 5 g 7 C.GO 0 . (){) o.co C.00 (}. 0 0 0 . 0 0 0.00 9. 9 ii (j. 00 0. 0 0 ii ' 0 0 0.00 0. 0 0 0.00 u.oo 0 . 0 0 5 v 10 li 12 13 14 15

FIG. 2.1 Channels and Their Interaction Test No. 1

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EN7EF. ·:HAl-!NEL PATTERN HI HEX · F. A A .A SELECT CHANNEL GROUP 1 2 3 4

[NTER ~EFE~ENCE -1043 THRU 2G47 2 0 Q D

Ci-!AHNEL -:;ROUP l

1 2 ~ 4 5 6 7 -9 .930 9.910 -9.980 9 . 9 2. 0 -9 985 9 . 915 -9.985 9. 9 io - ;i . s a o S.900 -S.965 9.SlG -9.985 9.910 -9.985 a.szo

" 9 l:l 11 11. l 3 14 ls

FIG. 2.2 Channels and Their Interaction 1Test No. 2

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;1 : rr .T' s.~ L

~NTER CHANNEL ?ATTERN IN HEI .F F F F. 5ELEC7 :HANNEL GROUP l Z 8 4 .l

ENTZ~ FE~EBENCE -Z04S THRU Z047 X X X X~

CriANNEi. ::;ROUP

Q ~ z - 005 - 005 - . 0 0 5 - cos - . 0 0 5 0.000 a 9 10

SELECT MCDE C N R 5 :C

CHANNEL GROUP : 1

J 095 l() s

8

l .105 . 10 ii 9

z .110 .lG5 10

SELECT MOCE : N R S C

CHANNEL ::.EOUP J.

J 1 z - 035 -.OZS - . 0 3 0 - } 3 \i - 030 - . G 3 G

i 3 1 o

E =+lOV cm 3 4 5

- . 0 0 5 - . 0 D 5 - . () 0 5 - OG5 - . 0 0 5 -.GOS

11 lZ 13

E =+15V cm 3 4 5 .110 . las .105 . 1() 5 .100 . l 0 5 11 U; 13

E =+17V cm

3 4 5 -.030 - 030 - . 0 z 5 -.030 -.030 - . 0 3 0

:;, l 12. 1 3

~

0.000 0.000

14

6 .105 .105 14

6 - 030 - . 0 3 0

14

FIG. 2.3 Input Protection Test

- 14 -

7 -.COS 0.000

l 5

7 .105 . ~ 0 s l 5

7 - . 0 ZS - 0 3 (}

15

>c xx x·x )( '-:..( ~;;( s r:t( t jz( ·:c t i 1 ~;&f : l

--U3 ·x l l : . l i : +·

+ 1 tJ )(

FIG. 2. 4

, .... ~

( IJ)

·-5~· (a) When Gain is too high.

I (REGULAR) ·'· i

c; ~~ + ..... ~

.L

I ~< '< ·~( ·L ·. · .. :· ·::~ YI': ~::: ·:.~· ' .. : ' .. : ··< ·:~

·tY +10 y (tf) .L _ .. , + (b) When Gain is proper.

-....·..!. !

J. {

\BNRY>i .,.

Graphic Display of Linearity (Regular) - 15-

+ I (DI FF' )

+ · ...... ,., ('.:--~~~~_,_~~~·:~(__:.;';~~:"+:'.·:~;:~::~~~¥"--+-~~..;--~~~~~~ ... "

":)t ..,

FIG. 2.5 Graphic Display of Linearity (Differential)

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I

'

MICROCOMPUTER

~

... ... INTERFACE ~ ... ,,

KS5110 '

GRAPHIC ~ ..... CONTROL

.; ... , ' MSBC-512

M u L T ... ~

DISK ~

I ' /

CONTROL .....

B u s

./ ..... ZSO CPU ~ ... ,

MSC8004 ...

32KRAM - ..... CDC ... ,

~ 8 1020. v

POWER SUPPLY -I!:~ ...... :...,____. P 0 I CP225

I I

I I I I I I I I I I I

I I I I I I

I I

~TO CAMAC CR ATE

..... ,

... ,

..... ,

J

0 o o o CD

=

VIDEO SHIBA

MONITOR DEN

VM-9 04U

=

DISK DRIVES SA85 0

D \.

TERMI TEC 5

NAL 01

FIG. 3.1 MICROCOMPUTER & PERIPHERALS

- 17 -

INPUT SWITCH I NG ~~----.

UNIT

16 BIT DAC

I\

DAC CONTROLLER

II\ 11\ 11\

,______

ISU CONTROLLER

\ I

MADC UNDER TEST

,,. COMAC CRATE -----"~-

,,. CRATE CONTROLLER ' KS 3908

/ FROM COMPUTER MADC ' INTERFACE CONTROLLER

FIG. 3.2 MADC TEST SETUP

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c C r.ttriC "INPL'T TEST N0.2 c ,.. I..------

K, SEINOr 9/11/81

,.. , .. , .. ~,..TFY C""nfEL p•rrrni-' "'-'• i... ~ t.'-'H ntti~n tt 1 l:J\Jlf uiANNEL GROUP Al-ID MC REFERENCE VALUE, C THE PROGRAM DIGITIZES A~UI Ir!SPLAYS A GROUP OF 16 CHANNELS WITH C THE SF'ECIFIED F'ARAn"CTEF:S, c --------c

c

F'f:GGRMI MINTS2 nrnrnsrn.~ ICHi'K 2 )1 IMREF( 2 )1 ICHFATC 2)1CHlJOL(16), IADR< 2) UIME~SION IC Ir~{ 8) f I CI DB( a) REALiS CYCL F:EAL CHVOL rnTEGrn C1N1R1S IlATA C1N1R1S/'C'r'N'1'R'1'S'/ DATA ICIDM011r213141516r7/ IIATA ICIDB/319110111112~13, 14115/

C INf'UT 0,t·Ef:A TION PAF:AXETERS c 30 um=N

\Jf:Im 5140) 40 FGFJi,;T( 2X1'ENTER CH~h'EL PATTERN IN HEX :')

CALL HEXIN( IHXI ) ICH~'AH 2 >=IHXI WRITE( 5150 >

50 FORfiAT(2X1'SELECT CHANNEL GROUP 1 2 3 + t') K'EAD\5160) ICHGRP

60 FORMAT<Il> lJRIT£(5170)

70 FORli;n 2X1'E.'t'T'"d: REITREHCE -2048 THRU 2(H7 :1 )

READ( 5180) IREF 80 FGRMAT(I5) C FOF:M CAXAC ADirRESSES 90 CALL CDREG<NAIIR1'010rl10>

CALL CDREG<NAIIR210101S10) CALL CDREG(NAIIR3r0r0r3r0)

C CONVCRT REFERENCE FROM 12 BIT TO 16 BIT USE 110 ICDI=IREF

CALL C126IIA( ICDI, ICDO > IDAF~EF( 2 >=ICflO

C SEh'D Rff !:AENCE TO DAC 120 CALL CFSA< 161NADR1 rIDAREF rGRSP) c snm CHANNEL PATTERN TO INPUT SWITCHING UNIT 130 CALL CFSA\161NADR31ICHF'AT1GR":>f') C DELAY 1 SEC 140 CALL DLYBOOOO>

GO TO !SO C INF'UT NUMBEF: OF CYCLES 150 w.r:rTEC 5, 160) 160 FGRMAT<2X1'ENTER NUMBER OF CYCLES:')

~:EAI~ 51170 l CYCL 170 PGRMAT<F16~0)

C CQhTINUE OR f;~PEAT FROM THIS POINT IF\ ICHGRP.EG~l) ICHNt2>=Z'SO' IF( ICHGRP ,EQ, 2 > !CHM( 2>=16tz' 80' lF\ 1CHGRP,EG.3) ICHHC2l=32tz'80' m ICHGRP ,EQ,4) ICHN( 2 l=+Btz'BO' DO 190 !=1116 CALL CFSAf 161HAI!F:2,JCHN,QRSf')

C IiELAY 30 MICRO SEC CALL DLYM3l

C GET DA TA FROK ADC CALL Cf SA( 0 r NAiiR21 IADR, GRSP) CHVOL{ I i=!AI1R( 2}

C CQNiJEF:T IT FF:Q~, iHTEGER TO REAL AtID THEN DIVID CHVOL< I i=CWJOL( I )/200 ICHH< 2 )=1CHi·H 2 Hl

190 CONTINUE c C PF~INTS RESULTS c 200 CALL SERAS

CALL SLfD( + ) ~RITE<S,210) ICh~P

210 FORM~H2Xr'CHti.lii-i'a GROUP ',Il) CALL SLFT~ 1 ) . WRITE<51220) ICIDA

220 FORMA H 6X 1SH1 r TX )) WF:ITE(51230) CHVOL

230 FGRMAn 2X1S( F8.3l/2Xr8<F8.3)) ~RITE(5i240) ICIDB

240 FGRXAH 6X12( I1 rTX ),6( I216X)) CALL SLFD< 2)

C DELAY 2 SEC CALL DLYB< 2000)

C CHECK MOI:E

c

m LMir.NE.R) GO TO 250 CYCL=CYCL-1 mcYCL.EQ,0) GO TO 250 GO TO 180

C SET MODE! C=CGNTINUEr N=NEW, -R--R£F'Et\Tr S--STOP c 250 260

270

280

WF:ITE( 51260) FORMAT(2Xr'SELECT MODE C N RS!') F:EAD< 5-, 270 ) U!D FORMAT( Al) IF(LMD,EQ,C) GO TO 180 If(LMD,EQ,N) GO TO 30 IF(LMD.EQ,R) GO TO 150 IF(LMD.EQ,S) GO TO 280 GO TO 250 STOP END

FIG. 4.1 (a) Program Example - Main Program - 19 -

F:OUTINE TO cmNERT 12 BIT MTA FOR 16 BIT DOC lh"E

FOF:MT: C126IiA( ICDirICDO>

ICDI <HU ICIIO (II£)

ENTRY C126DA . ' C126DA: PUSH .,..

Hf

PUSH LD me LD ,..., . ;>LH rot l\L ,..., . ;)LH

RL SLA RL ,..., . \JL..H

RL LD LD T111" J.m, LD POP F'OP Rt.I

BC A1(HU HL B1CHU A B A B A B • 11

B (DE),A ArB DE !DE>rA BC AF

;PUT IT IN A AHD B iFROli (HU

iSHIFT + TIIES

if'UT RESULT IN (DE>

FIG. 4.1 (b) Program Example - Subprogram

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