FIC MR055 MR056 - REV 0.2

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First International Computer,IncPortable Computer Group HW Department

Board name : MotherBoard Schematic

Version : 0.2

Manager Sign by: AVERY

Total confirm by: Adam ChoLAN Circuit check by: Audio Circuit check by:

1. Schematic Page Description :2. PCI & IRQ & DMA Description :3. Block Diagram :4. Nat name Description :5. Board Stack up Description :6. Schematic modify Item and History :7. power on & off & S3 Sequence :8. Layout Guideline :9. switch setting

Drawing by : Jason Hsu

MR055 / MR056

Initial Date : May. 04 , 2007

Confidential

Project :

Title 0.2

5FL.,NO.300,Yang Guang St.,NeiHu114 TAIPEI, TAIWAN ,ROC(886-2)8751-8751

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1 53Monday, August 27, 2007

MR055 / MR056Title

Size Document Number Rev

Date: Sheet of

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1. Title

IDSELAD17

CHIP CHIPPCIINTIRQAIRQBIRQCIRQD

REQREQ0 / GNT0

BUSMASTER

DMA ChannelDMA0 FIR (disable by default)

FLOPPY DISK

(Cascade)UnusedUnusedUnused

DeviceIRQ Channel DesciptionIRQ0

RTC

System timerKeyboard(Casacde)

Serial PortAUDIO / VGA / USBFLOPPY DISKLPT

ACPIFIR (Disable by default)CardbusPS/2 mouseFPUHDD

LAN / MODEM

CDROM

IEEE1394 (VIA VT6311S)(MODEM / LAN)ECP

AUDIO

(MODEM/LAN)

Mini PCI (Wireless LAN)AD27

3. Block Diagram4. Annotations

8. Merom Processor(1/2)

13. GM965 DDR2(3/6)

10. CPU Thermal

24. LCD CNN

11. GM965 Host(1/6) 31. PCIE GIGA LAN 88E8055

28. USB CNN

32. Transformer

38. MAX9789AETJ+

43. PMX

48. 3/5VDDA/M , PMU3/5V

CHIP

REQ1 / GNT1REQ2 / GNT2REQ3 / GNT3REQ4 / GNT4

IRQ1IRQ2IRQ3IRQ4IRQ5IRQ6IRQ7IRQ8IRQ9IRQ10IRQ11IRQ12IRQ13IRQ14IRQ15

DMA1DMA2DMA3DMA4DMA5DMA6DMA7

14. GM965 Power(4/6)33. PCIE Mini Card/ W-LAN

18. DDR2 SO-DIMM0

46. ACIN / BATIN / ADPOUT1

9. Merom Processor(2/2)

7. DDRII Layout Guideline

1. Schematic Page Description :MR055 / MR056 Schematic Ver:0.2

2. PCI & IRQ & DMA Description :

2. Schematic Page Description

5. Schematic Modify6. Timing Diagram

17. Clock Generator

12. GM965 DMI/Graph(2/6

26. SPI Rom / Reset

34. Robson / UMTS35. New Card

41. Screw Hole

44. Power Block Diagram*45. CPU Core Power

19. DDR2 SO-DIMM1

AD29 Lan (Realtek RTL8101L)LAN (Realtek RTL8101L)

LAN (Realtek RTL8101L)

LAN (Realtek RTL8101L)IRQE / GPIO2IRQE / GPIO3IRQE / GPIO4IRQE / GPIO5

PASS0CRISIS

20051228A

XXX

XX

X

X

X

27. HDD / ODD CNN

42. Blank

47. Charger / DCIN

15. GM965 Power(5/6)16. GM965 Ground(6/6)

20. ICH8M PCI/PCIE/DMI(1/4)

23. ICH8M Power/GND(4/4)22. ICH8M GPIO(3/4)21. ICH8M CPU/IDE/SATA(2/4)

30. DIP SW / LED / LID29. INT K/B / GP / SW CNN

39. HP / MIC IN JACK40. MDC CNN

50. 1.8VDDS/0.9VDDM/1.05V51. VDDCORE*52. MR055 Audio Board*(PA354)53. MR055 switch Xfer board* (GT2W)

49. 1.5VDDM / 1.2VDDM

25. CRT Port

37. Azalia ALC268GR- Codec36. Card Reader

Schematic Page Description 0.2

5FL.,NO.300,Yang Guang St.,NeiHu114 TAIPEI, TAIWAN ,ROC(886-2) 8751-8751

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Merom

P11~P16

P20~23

CORE

Processor

CPUIntelP45

P8~9

Crestline

P10

ThermalSensor

DMI

FSB

Mem_A Bus

3. Block Diagram :

P50VCCP(1.05VDDM)CPU

Lid Switch

Intel(G)MCH

IntelICH8M

P18

DDRII SODIMM0 (A)

DDRII SODIMM1 (B)P19

Mem_B Bus

PCIE

PCIE MINI CARD

Azalia

LPC BUS

Fan CNN P10

P21RTC Bat

P33

P29MAIN SW CNN/DIP SW

DDR2 533/667 MHz

DDR2 533/667 MHz

(667/800 MHz)

(x2/x4)

P26

P34

SIMP31,32

GIGA LAN88E8055

P32RJ-45

P30

P30LED

MDC P40

CLK SLG8SP512TTRP17

Brightness ControlP43

LCD

P25

CRT

P24

SPIROM

SPI BUS

PMX

P29 P29

P43

Int. KB

MB90F372

Glide Pad

P38

Azalia CodecP37

P39

MAX9789AAudio AMP

Mic In Headphone

ALC268

P39 P39

SPK

/ UMTSRobson

P34

HDDP27

P48

P27

ACIN

Battery Charger Battery CON

P43

P46

P50

1.05VDDM

Battery Voltage Sense

P48

P47

PMU3VPMU5V

P51

1.5VDDM

P49 P50P48

DCIN+ / DCIN

P47

VGA_VDD

DDR_0.9VDDM

1.8VDDS3VDDA5VDDA

CDROM

P46

3VDDM/5VDDM

P36

P36 SATA BUS

USB 2.0

P28

CardReader

REALTEK

P28

3 in 1

USB 2,3

RTS5158-GRUSB 0,1

PATA BUS

Block Diagram 0.2


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Voltage RailsDCIN

VCC_CORE

Primary DC system power supply

Core Voltage for CPU

3.3V switched power rail by SUSTAT_B#

PMU3V 3.3V always on power rail by LATCH or ACINPMU5V 5.0V always on power rail by LATCH or ACIN5.0V always on power rail by DCON5VDDA

3VDDS 3.3V power rail by PSUSC#5VDDS 5.0V power rail by PSUSC#3VDDM

5.0V switched power rail by SUSTAT_B#5VDDM

F

RInductorResistor

Q

ConnectorC

Fuse

=CN

Crystal and OscRP

D

UResistor PackArbitrary Logic Device

Diode

Part Naming Conventions

TransistorL

Y

Capacitor=====

====

Active Low signalNet Name Suffix# =

1.05VDDM

1.8V power rail for DDRII by PSUSC#0.9V DDRII Termination Voltage by SUSTAT_B#

1.8VDDS0.9VDDT_DDRII

3VDDA 3.3V always on power rail by DCON

4. Nat name Description :

1.5VDDM1.05V power rail for AGTL+ termination/Core for GMCH by SUSTAT_B#1.5V power rail for CPU PLL/DMI;PCIE;DDRII DLLs for GMCH/Core;PCIEfor ICH7m by SUSTAT_B#

Differential Impedance for Microstrip

55 ohm +/- 15%

100 ohm +/- 15%

PCIE Bus

Single End Impedance

85 ohm +/- 20%

95 ohm +/- 15%

70 ohm +/- 20%

100 ohm +/- 15%

SDVO

70 ohm +/- 20%

95 ohm +/- 15%DMI Bus

55 ohm +/- 15%

100 ohm +/- 15%

Host Bus

55 ohm +/- 15%

55 ohm +/- 15%

95 ohm +/- 15%

DDR2 Bus

55 ohm +/- 15%

95 ohm +/- 15%

90 ohm +/- 15%

DDR2 CLK

100 ohm +/- 15%

90 ohm +/- 15%

DDR2 Strobe

95 ohm +/- 15%

100 ohm +/- 15%

110 ohm +/- 15%

Lan

SRC Clock

95 ohm +/- 15%

110 ohm +/- 15%IEEE1394

55 ohm +/- 15%

100 ohm +/- 15%

Host Clock

100 ohm +/- 15%

50 ohm +/- 15%

USB

Differential Impedance for Stripline

55 ohm +/- 15%

55 ohm +/- 15%

LVDS

42 ohm +/- 15%

100 ohm +/- 15%

SATA

5. Board Stack up DescriptionPCB Layers

Layer 3

Solder Side,Microstrip signal LayerLayer 5Layer 6

Component Side, Microstrip signal Layer

Power Plane

Layer 1

Layer 4

Ground Plane

Stripline Layer(High Speed)

Layer 2Stripline Layer(High Speed)

Annotations 0.2


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6.Schematic modify Item and History :

1.425V~1.5V~1.575V

ICH8M: Integrated Gigabit LAN I/O

Crestline: I/O Voltage

Crestline:

VCC_DMI

VCCSUS1_05

Crestline: CRTICH8M: I/O

Merom: AGTL+ termination

VCCGLAN1_5

VCC_SM

Crestline:

VCCD_PEG_PLL

Crestline: Controller Link/ME voltage supply

Crestline: CRT

4.5A1.05VDDM 1.00V~1.05V~1.10V

Crestline:

VCC_AXM

LFM:VCC_CORE

1.5VDDM

1.425V~1.5V~1.575V

1.0A

ICH8M: Resume well I/O

Crestline:

VCCR_RX_DMI

Crestline: TV DAC

Voltage

1.7V~1.8V~1.9V

DDRII Terminator:

Express Card:

VCCSUS1_5

Crestline:

Crestline: Rx and I/O Logic for DMI

Merom PLL

VCCD_CRT

1.425V~1.5V~1.575V

HFM:

1.8VDDS:

44A

ICH8M: I/O

Crestline:

Crestline: PCI Express Based Graphics

Power Rail

VCCD_QDAC

1.3A

0.855V~0.9V~0.945V

24mA

Crestline:

Crestline: AGTL+ termination

VCC1_5_B

Crestline:

Crestline: Core chipset

VCCA_PEG_PLL

VCCA

0.9VDDT_DDRII:

VCCA_LVDS

TBD

1.5A

ICH8M:

Crestline:

0.8A

VCCA_SM_CK

VCC_PEG

VCC1_05

SO-DIMM:

Crestline:

+1.5V

TBD~TBD

320mA

VCC_DMI

VCC_AXG

VCCA_SM

VCCSATAPLL

VCC

VCC_TX_LVDS

0.9975V~1.05V~1.1025V

1.0375V~?~1.3000V

Crestline:

VCC1_5_A

VTT(VCCP)

Crestline:

3.1A

VCC_AXF

ICH8M: Integrated Gigabit LAN PLL

VCCA_DPLLB

ICH8M:

VCCP

Merom

ICH8M:

VCCD_LVDS

ICH8M: SATA PLL

Crestline:

VCCGLANPLL

VCCA_DPLLA

VCCCL1_05

Crestline: TV DAC

ICH8M:

Crestline: Clock I/O Voltage

ICH8M: ICH8 Core

VCCUSBPLL

Crestline:

ICH8M: DMI PLL

VCCA_MPLL

1.425V~1.5V~1.575V

Ball Name

130mA

1.25VDDM

Destination S0 Current

ICH8M: Controller Link

VCCDMIPLL

VCCD_HPLL

VCCD_QDAC1.425V~1.5V~1.575V

TBD

1.8VDDS:

Mini Card:

VCCCL1_5

VCC_SM_CK

ICH8M: USB PLL

Crestline:

VCCA_HPLL

VCCLAN1_05

VCCD_TVDAC

0.9975V~1.05V~1.1025V

60mA

HDD: SATA

Crestline: TV Out

Express Card:

Voltage

CH7307:

400mA

ICH7m:

3VDDSLan: Broadcom BCM4401

945GM: PCIE analog

Azalia Codec: ALC260

PMU3V

ODD: PATA

1.0A

EC: PMU08

Crestline: TV DAC

3.0V~3.3V~3.6V

2.5VDDM

Azalia MDC:

Flash ROM: BIOS

Card Reader: SD/MMC/MS

VCCA_DAC_BG

3.0V~3.3V~3.6V

4.75V~5.0V~5.25V

60mA

Crestline: TV Out

Destination

Azalia Codec: ALC260

KBC: KB3886

LCD:

VCCA_TVC_DAC

Audio AMP: G1420

2mA

3.0V~3.3V~3.6V

VCCA_TVB_DAC

3.0V~3.3V~3.6V

VCC_HV

5VDDM

VCCA_TVA_DAC

3VDDM VCCA_PEG_BG

Max: 1.0A ; R/W

CLK Generator: ICS954226

945GM: LVDS I/O

ICH7m: RTC

Crestline: CRT DAC

3.135V~3.3V~3.465V

4.75V~5.0V~5.25V

ICH7m:

VCCA_CRT_DAC

2.32V~2.5V~2.625V

3VDDA

2.375V~2.5V~2.625V

Crestline: H/VSYNC power

5VDDS

70mA

120mA

3.135V~3.3V~3.465V

Azalia MDC: For wake up

Azalia MDC:

VCC_SYNC

5V

Crestline: PCI Express Base Graphics

HDD: SATA

Power Rail

945GM: LVDS analog

ICH7m:

3.135V~3.3V~3.465V

USB: x 4 ports

ICH7m:

2.375V~2.5V~2.625V

Inverter:

2.0A

Crestline: HV buffer power

2.32V~2.5V~2.625V10mA

Mini Card:

Crestline: TV Out

945GM: CRT DAC

S0 Current

40mA

Max: 1.8A ; R/W: 900mA

Ball Name

Need Modify

Page22 RF_ON# change to RF_ONPage22 UMTS_ON change to UMT S_OFF#Page43 VOR0 change to VOR#

Schematic Modify 0.2


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Tsft_star_vcc(3ms max)

GMCHPWRGD

Tcpu_up

Tboot

Vccgmch

VidVcc-core

Tvccp_up

VID

Vccp

CLK_ENABLE#Tgmch_pwrgd

Vccp_UP

IMVP6 Power On Sequencing Timing Diagram

Tboot-vid-tr(100uS max)

Tcpu_pwrgd(3~20mS)IMVP4_PWRGD

CPU_UP

VbootVR_ON

PSUSC0

VDDM,VDDS

To ODEM and ICH4

PM_PWROK

From ODEM to CPUAGTL+_CPURST0

PMU5V/PMU3V

BATTERY ONLY POWER ON TIMING

DCON

To ICH4VDDA

CPU_PWRGD

To clock generator

VCCP/1.2VDDM

To ICH4

VR_ONVCORE_CPU

From ICH4PM_SLP_S30/S40/S50

SYS_PWROK

CK408_PWRGD0

From ICH4 to CPU

To ODEM/other PCI device

SUSTAT_B0

PCI_RST0

VCORE_ON

From ASIC_B0From ASIC_B0

PM_RSTRST0

MAINSW0_ICH

POWSW0

PM_VGATE

VRON_VCCP

H

From ASIC_B0

CPU_PWRGOOD

VR_ON

CK408_PWRGD0PM_VGATE

DCON

H

S3 SUSPEND AND RESUME TIMING

H

VCCP,1.2VDDM

SYS_PWROK

From ASIC_B0

H

To ICH4_M

H

From ICH4_M

1.5VDDS AND

H

PM_PWROK

SUSTAT_B0

VCORE_CPU

Generator

VDDM

PMU5V/PMU3V

PM_SLP_S40/S50

VRON_VCCP

PM_RSMRST0

H

DDR_PWRGD

To ODEM/otherPCI device

PCI_RST0

VDDA

From ODEM to CPU

To clock

VDDS

PSUSC0

ToICH4 and ODEM

From ICH4_M

VCORE_ON

PM_SLP_S30

POWSW0

From ICH4 to CPU

AGTL+_CPURST0

7. power on & off & S3 Sequence :

Tboot:10-100uS

-12%

t CPU_UP

-12%

Vccp_UPt

t BOOT

BOOT-VID-TRt

-12%

t MCH-PWRGD

t CPU_PWRGD

PSI#

VID

VR_ON

V CC-CORE

CCP

CC_MCH

CPU_UP

V

Vccp_UP

V

MCH_PWRGD

CLK_ENABLE#

IMVP6_PWRGD

20060117A - DATA FROM NO.16809Power On Sequencing Timing Diag ram

SFT_START_VCCt

t SFT_START_VCC Max = 3 ms

t BOOT Min = 10 us , Max = 100 us

BOOT-VID-TRt Max = 100 us

t CPU_PWRGD Min = 3 ms , Max = 20 ms

MCH-PWRGDt

t Vccp_UP

CPU_UPt

Min = 10 us , Max = 30 us



Timing Diagram 0.2


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Crestline DDRII Layout GuidelinesDDRII Signal Groups

Data

Group Signal Name

Control-to-Clock

Signal Group Minimum Length Maximum Length

Command-to-Clock

Strobe-to-Clock

Data-to-Strobe

Clock - 1.0"

Clock - 1.0"

Clock - 0.5"

Clock - 0.0"

Clock + 1.0"

Strobe - 220mils

8. Layout Guideline :

SA_DQ[63..0]/SB_DQ[63..0]SA_DM[7..0]/SB_DM[7..0]SA_DQS[7..0]/SA_DQS#[7..0]SB_DQS[7.. 0]/SB_DQS#[7..0]

SA_RAS#/SB_RAS#SA_BS[2..0]/SB_BS[2..0]SA_MA[13..0]/SB_MA[13..0]Address

SA_CAS#/SB_CAS#SA_WE#/SB_WE#

SM_CS#[3..0]ControlSM_CKE[3..0]SM_ODT[3..0]

Clock SM_CK[3..0]SM_CK#[3..0]

SA_RCVENOUT#/SB_RCVENOUT#FeedBackSA_RCVENIN#/SB_RCVENIN#

Length Matching and Length Formulas

Clock + 1.0"

Strobe - 180mils

CLK group : SM_CK[3..0],SM_CK#[3..0]

GMCH

P1

P1

L0

L0

L1

L1

L2

L2

S1

S1

SO-DIMM

Topology

Reference Plane

Single Ended Trace Impedance

Differential Mode Impedance

Differential Pair Point -to-Point

Ground

42 +/- 15%

70 +/- 20%

Nominal Trace Width Inner Layer : 7 milsOuter Layer : 8 mils

Outer Layer : 5 milsNominal CK to CK# Sp acing(edge to edge)

Inner Layer : 4 mils

Minimum Serpentine Spaci ng Inner Layer : 12 milsOuter Layer : 15 mils

Minimum Spacing to Other DDR2 Inner Layer : 16 milsOuter Layer : 20 mils

Minimum Isolation Spacing to non-DDR2 25 mils

Package Length Range - P1 1000 mils +/- 250 mils

Trace Length Limit - L0 Max = 50 mils (Escape)

Trace Length Limit - L1 Max = 500 mil s (Breakout)

Stub Length S1-Stub from via to SO-DIMM Max = 200 mils (Breakin)

MB Length Limits - L0 + L1 + L2 + S1 Min = 500 mils

Max = 4500 milsTotal Length - P1 + L0 + L1 + L2 + S1

Max = 4000 mils

Total Length for Channel A : X0Total Length for Channel B : X1

Maximim Via Count 2 (Per side)

SCK to SCK# Length Matching Match total length to within 5 mils

Clock to Clock Length Match(Total Length)

Match Channel A clocks to X0 +/- 20milsMatch Channel A clocks to X1 +/- 20mils

Breakout Exceptions (R educe geometriesfor GMCH break-out region)

Inner Layer : 4/12 mils to other DDR2Outer Layer : 5/15 mils to other DDR2

Max. breakout length is 500 m ils

Breakin Exception s (Reduce geometriesfor SO-DIMM break-in region)

CK to CK# spacing rule waived atconnector spacing of 15 mils toother DDR2Max. breakin length is 2 00 mils

Escape Breakout Breakin

4/4/12 7/4/16 8/5/15

Outer Layer : 5 mils

Inner Layer : 4 mils spacing allowe d

L1


55 +/- 15%

Max = 500 mil s (Breakout)

Max = 50 mils (Escape)


Point-to-Point with parallel termination

GMCH

Stub Length S1-Stub from via to SO-DIMM

MB Length Limits - L0 + L1 + L2 + S1 -From GMCH ball to SO-DIMM pad

Trace Length Limit - L1

Package Length P1


S1

Nominal Trace Width

Max = 200 mils (Breakin)

8/5/15

Breakout

3

Total Length - P1 + L0 + L1 + L2 + S1 -From GMCH die to SO-DIMM pad


Maximim Via Count

Minimum CTRL Trace Spac ing

7/4/16

Max. breakout length is 500 m ils

Min = 500 mils

25 mils

Topology

4/4/12

Max = 4500 mils


Minimum Spacing to Other DDR2

L2

Reference Plane

Escape

(CLK-1.0")

AA

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

Transmission Line Type Total Trace Length Normal Impedance Spacing (mils)

ADS# , BNR# , BPRI# , BR0# , DBSY# , DEFER# , DPWR# , DRDY# , HIT# , HITM# , LOCK# ,RS[2..0]# , TRDY# , RESET#.

Strip-line(Int. Layer)

Micro-strip(Ext. Layer)1.0 ~ 6.5 inch 55+/-15%

5 & 10 mils

FSB Common Clock Signal Layout Guide :

Normal Impedance

0.5 ~ 5.5 inch

Width & Spacing (mils)

55+/-15%

4 & 8 mils

DATA#[63..0]

FSB Source Synchronous Data Signal Routing Topology#1 :Signal Name

Strip-line

Total Trace Length

Signals NameDSTBP0#,DSTBN0#

Strobes associated with the group Strobe-to-Strobe Complement MatchingDATA#[15..0] , DINV0#

Signals Matching+/- 25 mils+/- 100 mils

DATA#[31..16] , DINV1# +/- 100 mils

+/- 100 mils

+/- 100 mils

+/- 25 mils

+/- 25 mils

+/- 25 mils

DATA#[47..32] , DINV2#

DATA#[63..48] , DINV3#

DSTBP1#,DSTBN1#

DSTBP2#,DSTBN2#

DSTBP3#,DSTBN3#

Strobes associated with the groupA#[16..3] , REQ#[4..0]

+/- 200 mils

ADSTB0#+/- 200 mils

Strobe to Assoc. Address Signal Matching

ADSTB1#A#[31..17]

+/- 200 mils

ADSTB#[1..0]

Signals MatchingSignals Name

Topology : PWRGOOD

CPU

L10.5" - 12" Strip-line

L1

Micro-strip

Transmission Line

0.5" - 12"

Topology : INTR , NMI , A20M# , DPSLP# , IGNNE# , INIT# , SMI# , STPCLK#

A#[32-39], APM#[0-1]:Leave escape routing on for future functionality

Zo=55ohm, 0.5" max for GTLREF, Space any other switchsignals away from GTLREF with a minimum of 25mils.

Should be connect to ICH8M and Crestline without T-ing(no s tub)

Rout to TP via and place gnd via w/in 100mi ls

Comp0,2 connect with Zo=27.4ohm, make tracelength shorter than 0.5" and width is 18mils.

Comp1,3 connect with Zo=55ohm, make tracelength shorter than 0.5" and width is 5mil s

XDP P/U & P/D

DINV#[3..0]

DSTBN#[3..0]

DSTBP#[3..0]

Transmission Line Type

Strip-line

Strip-line

Strip-line

0.5 ~ 5.5 inch

0.5 ~ 5.5 inch

0.5 ~ 5.5 inch

55+/-15%

55+/-15%

55+/-15%

Data-to-Data,Strobe-to-strobe Strobe-to-Data4 & 8 mils

4 & 8 mils

4 & 12 mils

4 & 12 mils

4 & 12 mils

4 & 12 mils

N/A

N/A

FSB Source Synchronous Data Length Variation and Strobe Matching Requirements :

FSB Source Synchronous Address Length Variation and Strobe Matching Requirements :

+/- 200 mils

*** No length matching requirements exist between ADSTB0# and ADSTB1#

55+/-15%Strip-line

55+/-15%

4 & 8 mils

FSB Source Synchronous Address Signal Routing :Transmission Line Type

4 & 8 mils

Signal NameStrip-line

Total Trace Length Normal Impedance

0.5 ~ 6.5 inch

Width & Spacing (mils)55+/-15%

Strip-line

Address#[31..3]

REQ#[4..0]

4 & 8 mils

0.5 ~ 6.5 inch

0.5 ~ 6.5 inch

0" - 3.0" Microstrip0.5" - 12"

L2

56 +/-5%Rtt

Topology : FERR#

Stripline

VCCP L1

0.5" - 12"L1

ICH8MCPURtt Transmission Line

0" - 3.0"

56 +/-5%

L2

ICH8M

Strip-lineL1

0.5" - 12"

Transmission Line

0.5" - 12" Micro-strip

L1CPU ICH8M

L4

VCCP

RttCPU IMVP6

VCCP

Rtt

L2+L1 L3 Strip-line

Rtt Transmission LineL2L1

Micro-strip75 +/-5%0.5" - 6.5"

75 +/-5%0.5" - 6.5"

0.5" - 6.5"

0.5" - 6.5"

0" - 3.0"

0" - 3.0"

0" - 3.0"

0" - 3.0"

L3 L4

Rtt

VCCP

Topology : THERMTRIP#

GMCH

L2

CPU ICH7m

RttL1 L4L3

Rtt

56 +/-5%

L1 L2

1" - 6" 0" - 3.0"

Strip-line0" - 3.0"

0" - 3.0"

Transmission LineL4

Micro-strip

L3

0" - 3.0"

1" - 12"

1" - 12" 1" - 6"

L1+L3

1" - 12"

1" - 12"

Rss

24 +/-5%

24 +/-5% 56 +/-5%

Micro-strip

Strip-lineL1

Strip-line

Transmission LineCPU

Topology : CPUSLP#

0.5" - 12"

1" - 6"

Transmission Line

0.5" - 12"

Topology : RESET#

Micro-strip

L1CPU

L1

L1

GMCH

GMCH

1" - 6"

Don't allow the GTLREF routing to create splits ordiscontinuities in the reference planes of the FSBsignals

H_PWRGD rise time :Max : 15ns

Processor ITP Signal Default Strapping When ITP-XDP &ITP700FLEX Dedbug Port Not Used.

TDI

TMS

TRST#TCK

TDO

54.9 OHM +/-5%

OPEN

VCCP

VCCP

GNDGND

NC

Within 2.0" of the CPU

Within 2.0" of the CPU

Within 2.0" of the CPUWithin 2.0" of the CPU

N/A

Signal Resistor Value Connect To Resistor Placement

54.9 OHM +/-5%

649 OHM +/-5%54.9 OHM +/-5%

Place C? close to the CPU_TEST4 pin.

Make sure CPU_TEST4 routing is reference to GNDand away from other nossy signale.

VCCP=1.05VDDM

0'' ~ 3''

Merom Processor (1/2) 0.2


C


MR055 / MR056Title


Date: Sheet of


H_A#[35..3]

H_A#[35..3]

XDP_TRST#

H_D#32H_D#33H_D#34

H_D#36H_D#35

H_D#38

H_D#40H_D#39

H_D#37

H_D#46

H_D#42

H_D#44

H_D#47

H_D#43

H_D#45

H_D#41

H_D#57

H_D#53

H_D#49

H_D#56

H_D#51

H_D#63

H_D#54

H_D#50

H_D#52

H_D#61H_D#62

H_D#58

H_D#55

H_D#59

H_D#48

H_D#60

H_D#23

H_D#31

H_D#1

H_D#10

H_D#13

H_D#21H_D#22

H_D#[63..0]

H_D#18

H_D#30

H_D#4

H_D#19

H_D#26H_D#27

H_D#0

H_D#5

H_D#[63..0]

H_D#7

H_D#11

H_D#14H_D#15

H_D#17

H_D#8

H_D#25

H_D#2

H_D#24

H_D#28

H_D#6

H_D#9

H_D#12

H_D#20

H_D#[63..0]

H_D#3

H_D#16

H_D#29

H_D#[63..0]

COMP0

COMP2

XDP_TCK

XDP_TDIXDP_TMS

H_A#13

H_A#28

H_REQ#1

H_A#7

H_REQ#4

H_A#8

H_A#21

H_A#6

H_A#12

H_A#25

H_A#23

H_A#16

H_REQ#3

H_A#29

H_A#22

H_A#26

H_A#10

H_REQ#[4..0]

H_A#5

H_A#31

H_A#20H_A#19

H_A#15

H_REQ#0

H_A#30

H_A#27

H_A#11

H_A#4

H_A#18

H_A#14

H_REQ#2

H_A#3

H_A#9

H_A#24

H_A#17

H_GTLREF

H_IERR#

XDP_TMS

XDP_TCKXDP_TDI

XDP_TRST#

H_A#32H_A#33H_A#34H_A#35

CPU_TEST4

COMP1

COMP3

XDP_BPM#5

XDP_BPM#5

1.05VDDM (9,11,14,15,17,21,23,50)

H_A#[35..3](11)

H_A#[35..3](11)

H_ADSTB#0(11)

H_ADSTB#1(11)

H_REQ#[4..0](11)

H_D#[63..0](11)

H_D#[63..0](11)

H_DSTBN#0(11)H_DSTBP#0(11)

H_DINV#0(11)

H_DSTBN#1(11)

H_DINV#1(11)H_DSTBP#1(11)

H_D#[63..0] (11)

H_D#[63..0] (11)

H_DSTBN#2 (11)

H_DINV#2 (11)H_DSTBP#2 (11)

H_DSTBN#3 (11)

H_DINV#3 (11)H_DSTBP#3 (11)

H_BNR# (11)

H_DBSY# (11)

H_LOCK# (11)

H_DRDY# (11)

H_HITM# (11)H_HIT# (11)

H_ADS# (11)

H_BREQ# (11)

H_PROCHOT#

H_A20M#(21)

H_IGNNE#(21)

H_STPCLK#(21)H_INTR(21)H_NMI(21)

H_SMI#(21)

H_CPUSLP# (11)H_PWRGD (21)

H_DPWR# (11)

H_DPRSTP# (12,21,45)H_DPSLP# (21)

H_CPURST# (11)

H_RS#2 (11)H_RS#1 (11)

H_INIT# (21)

H_RS#0 (11)

H_BPRI# (11)

H_TRDY# (11)

H_DEFER# (11)

CLK_CPU_BCLK (17)CLK_CPU_BCLK# (17)

H_THERMDA (10)

H_FERR#(21)

CPU_BSEL0(17)CPU_BSEL1(17)

PSI# (45)CPU_BSEL2(17)

PM_THRMTRIP# (12,21)

H_THERMDC (10)

1.05VDDM(9,11,14,15,17,21,23,50) 1.05VDDM

1.05VDDM

1.05VDDM

1.05VDDM

ADDR GRO

UP0

ADDR GRO

UP1

CONT

ROL

XDP/

ITP

SIG

NALS

H CLK

THERMAL

RESE

RVED

ICH

U8A

Merom Ball-out Rev 1a

N3P5P2L2P4P1R1

Y2U5R3W6U4Y5U1R4T5T3

W2W5Y4

J4

U2V4

M4N5T2V3B2C3D2

D22

L5L4K5M3N2J1

A6

H1

M1

V1

D3

A22A21

E2

AD4AD3AD1AC4

G5

F1

C20

E1

H5F21

A5

G6E4

D20

C4

B3

C6B4

H4

AC2AC1

D21

K3H2K2J3L1

C1F3F4G3

A3

D5

AC5AA6AB3

C7

A24B25

AB5

G2

AB6

W3AA4AB2AA3

F6

A[10]#A[11]#A[12]#A[13]#A[14]#A[15]#A[16]#

A[17]#A[18]#A[19]#A[20]#A[21]#A[22]#A[23]#A[24]#A[25]#A[26]#A[27]#A[28]#A[29]#

A[3]#

A[30]#A[31]#

RSVD[01]RSVD[02]RSVD[03]RSVD[04]RSVD[05]RSVD[06]RSVD[07]RSVD[08]

A[4]#A[5]#A[6]#A[7]#A[8]#A[9]#

A20M#

ADS#

ADSTB[0]#

ADSTB[1]#

RSVD[09]

BCLK[0]BCLK[1]

BNR#

BPM[0]#BPM[1]#BPM[2]#BPM[3]#

BPRI#

BR0#

DBR#

DBSY#

DEFER#DRDY#

FERR#

HIT#HITM#

IERR#

IGNNE#

INIT#

LINT0LINT1

LOCK#

PRDY#PREQ#

PROCHOT#

REQ[0]#REQ[1]#REQ[2]#REQ[3]#REQ[4]#

RESET#RS[0]#RS[1]#RS[2]#

SMI#

STPCLK#

TCKTDI

TDO

THERMTRIP#

THERMDATHERMDC

TMS

TRDY#

TRST#

A[32]#A[33]#A[34]#A[35]#

RSVD[10]

R5072K 1% 1/10W SMT0603 LR

C5100.1uF 10V 10% SMT0402 X5R LR(NU)

T211

R495 56 5% 1/16W SMT0402 LR

R5061K 1% 1/10W SMT0603 LR

T201

R49675 5% 1/16W SMT0402 LR

R504 27.4 1% 1/10W SMT0603 LR

R502 1K 5% 1/16W SMT0402 LR(NU)R505 54.9 1% 1/16W SMT0402 LR Sn

R463 649 1% 1/10W SMT0603 LR

R449 54.9 1% 1/16W SMT0402 LR Sn

R442 27.4 1% 1/10W SMT0603 LR

R436 54.9 1% 1/16W SMT0402 LR Sn(NU)

R450 54.9 1% 1/16W SMT0402 LR Sn

R456 54.9 1% 1/16W SMT0402 LR Sn

R443 54.9 1% 1/16W SMT0402 LR Sn

DATA GRP 0

DATA GRP 1

DATA

GRP

2DA

TA G

RP 3

MISC

U8B


R26U26AA1Y1

E22F24

J24J23H22F26K22H23

N22K25P26R23

E26

L23M24L22

M23P25P23P22T24R24L25

G22

T25N25

Y22AB24V24V26V23T22U25U23

F23

Y25W22Y23W24W25AA23AA24AB25

AE24AD24

G25

AA21AB22AB21AC26AD20AE22AF23AC25AE21AD21

E25

AC22AD23AF22AC23

E23K24G24

AF1

H25

N24

U22

AC20

E5B5D24

J26

L26

Y26

AE25

H26

M26

AA26

AF24

AD26

AE6

D6D7

C24

B22B23C21

D25

AF26

A26

C23 COMP[0]COMP[1]COMP[2]COMP[3]

D[0]#D[1]#

D[10]#D[11]#D[12]#D[13]#D[14]#D[15]#

D[16]#D[17]#D[18]#D[19]#

D[2]#

D[20]#D[21]#D[22]#D[23]#D[24]#D[25]#D[26]#D[27]#D[28]#D[29]#

D[3]#

D[30]#D[31]#

D[32]#D[33]#D[34]#D[35]#D[36]#D[37]#D[38]#D[39]#

D[4]#

D[40]#D[41]#D[42]#D[43]#D[44]#D[45]#D[46]#D[47]#

D[48]#D[49]#

D[5]#

D[50]#D[51]#D[52]#D[53]#D[54]#D[55]#D[56]#D[57]#D[58]#D[59]#

D[6]#

D[60]#D[61]#D[62]#D[63]#

D[7]#D[8]#D[9]#

TEST5

DINV[0]#

DINV[1]#

DINV[2]#

DINV[3]#

DPRSTP#DPSLP#DPWR#

DSTBN[0]#

DSTBN[1]#

DSTBN[2]#

DSTBN[3]#

DSTBP[0]#

DSTBP[1]#

DSTBP[2]#

DSTBP[3]#

GTLREF

PSI#

PWRGOODSLP#

TEST3

BSEL[0]BSEL[1]BSEL[2]

TEST2

TEST4

TEST6

TEST1

T191

R499 1K 5% 1/16W SMT0402 LR(NU)

AA

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

Place these inside socket cavity on L8(North side secondary)

Place C? Close To pinB26

Route VCCSENSE and VSSSENSE tracesat 27.4 ohms with 50mil spacing.Place PU and PD within 1 inch of CPU

ICCA=130mA, 20mils

HFMICC=41A

ICCP=4.5A,180mils

Place these inside socket cavity on L1(South side Primary)

Place these inside socket cavity on L8(North side secondary)

Place these inside socket cavity on L1(North side Primary)

Place these inside socket cavity onL8 (South side secondary)

Yonah Processor (2/2) 0.2


C


MR055 / MR056Title


Date: Sheet of


H_VID0 (45)H_VID1 (45)

H_VID3 (45)H_VID2 (45)

H_VID5 (45)H_VID4 (45)

H_VID6 (45)

VCCSENSE (45)

VSSSENSE (45)

VCORE_CPU(45)

1.05VDDM(8,11,14,15,17,21,23,50)

1.5VDDM(14,15,20,21,23,33..35,49)

VCORE_CPU

VCORE_CPU

1.05VDDM

1.5VDDM

VCORE_CPU

1.5VDDM

1.05VDDM

C477

10uF 6.3V 10%

SM

T0805 X5R

C2012X

5R0J106K

TDK

LR

C107

10uF 6.3V 10%

SM

T0805 X5R

C2012X

5R0J106K

TDK

LR(N

U)

C106

10uF 6.3V 10%

SM

T0805 X5R

C2012X

5R0J106K

TDK

LR

C475

10uF 6.3V 10%

SM

T0805 X5R

C2012X

5R0J106K

TDK

LR

C447

10uF 6.3V 10%

SM

T0805 X5R

C2012X

5R0J106K

TDK

LR(N

U)

C486

10uF 6.3V 10%

SM

T0805 X5R

C2012X

5R0J106K

TDK

LR(N

U)

C472

10uF 6.3V 10%

SM

T0805 X5R

C2012X

5R0J106K

TDK

LR

C458

10uF 6.3V 10%

SM

T0805 X5R

C2012X

5R0J106K

TDK

LR

C517

10uF 6.3V 10%

SM

T0805 X5R

C2012X

5R0J106K

TDK

LR

C96

10uF 6.3V 10%

SM

T0805 X5R

C2012X

5R0J106K

TDK

LR(N

U)

C110

10uF 6.3V 10%

SM

T0805 X5R

C2012X

5R0J106K

TDK

LR(N

U)

C441

10uF 6.3V 10%

SM

T0805 X5R

C2012X

5R0J106K

TDK

LR(N

U)

C93

10uF 6.3V 10%

SM

T0805 X5R

C2012X

5R0J106K

TDK

LR

C443

10uF 6.3V 10%

SM

T0805 X5R

C2012X

5R0J106K

TDK

LR(N

U)

C468

10uF 6.3V 10%

SM

T0805 X5R

C2012X

5R0J106K

TDK

LR

C450

10uF 6.3V 10%

SM

T0805 X5R

C2012X

5R0J106K

TDK

LR(N

U)

C462

10uF 6.3V 10%

SM

T0805 X5R

C2012X

5R0J106K

TDK

LR

C478

10uF 6.3V 10%

SM

T0805 X5R

C2012X

5R0J106K

TDK

LR(N

U)

C95

10uF 6.3V 10%

SM

T0805 X5R

C2012X

5R0J106K

TDK

LR

C108

10uF 6.3V 10%

SM

T0805 X5R

C2012X

5R0J106K

TDK

LR(N

U)

C440

10uF 6.3V 10%

SM

T0805 X5R

C2012X

5R0J106K

TDK

LR(N

U)

C495

0.1uF 16V 10%

SM

D0603 X

7R LR

12

C483

10uF 6.3V 10%

SM

T0805 X5R

C2012X

5R0J106K

TDK

LR(N

U)

C452

10uF 6.3V 10%

SM

T0805 X5R

C2012X

5R0J106K

TDK

LR(N

U)

R461100 1% 1/16W SMT0402 LR

C493

0.1uF 16V 10%

SM

D0603 X

7R LR

12

U8C


A7A9

A10A12A13A15A17A18A20B7B9

B10B12B14B15B17B18B20C9

C10C12C13C15C17C18D9

D10D12D14D15D17D18

E7E9

E10E12E13E15E17E18E20

F7F9

F10F12F14F15F17F18F20AA7AA9

AA10AA12AA13AA15AA17AA18AA20AB9

AC10AB10AB12AB14AB15AB17AB18

AB20AB7AC7AC9AC12AC13AC15AC17AC18AD7AD9AD10AD12AD14AD15AD17AD18AE9AE10AE12AE13AE15AE17AE18AE20AF9AF10AF12AF14AF15AF17AF18AF20

B26

J6K6M6J21K21M21N21N6R21R6T21T6V21W21

AF7

AD6AF5AE5AF4AE3AF3AE2

AE7

C26

G21V6

VCC[001]VCC[002]VCC[003]VCC[004]VCC[005]VCC[006]VCC[007]VCC[008]VCC[009]VCC[010]VCC[011]VCC[012]VCC[013]VCC[014]VCC[015]VCC[016]VCC[017]VCC[018]VCC[019]VCC[020]VCC[021]VCC[022]VCC[023]VCC[024]VCC[025]VCC[026]VCC[027]VCC[028]VCC[029]VCC[030]VCC[031]VCC[032]VCC[033]VCC[034]VCC[035]VCC[036]VCC[037]VCC[038]VCC[039]VCC[040]VCC[041]VCC[042]VCC[043]VCC[044]VCC[045]VCC[046]VCC[047]VCC[048]VCC[049]VCC[050]VCC[051]VCC[052]VCC[053]VCC[054]VCC[055]VCC[056]VCC[057]VCC[058]VCC[059]VCC[060]VCC[061]VCC[062]VCC[063]VCC[064]VCC[065]VCC[066]VCC[067]

VCC[068]VCC[069]VCC[070]VCC[071]VCC[072]VCC[073]VCC[074]VCC[075]VCC[076]VCC[077]VCC[078]VCC[079]VCC[080]VCC[081]VCC[082]VCC[083]VCC[084]VCC[085]VCC[086]VCC[087]VCC[088]VCC[089]VCC[090]VCC[091]VCC[092]VCC[093]VCC[094]VCC[095]VCC[096]VCC[097]VCC[098]VCC[099]VCC[100]

VCCA[01]

VCCP[03]VCCP[04]VCCP[05]VCCP[06]VCCP[07]VCCP[08]VCCP[09]VCCP[10]VCCP[11]VCCP[12]VCCP[13]VCCP[14]VCCP[15]VCCP[16]

VCCSENSE

VID[0]VID[1]VID[2]VID[3]VID[4]VID[5]VID[6]

VSSSENSE

VCCA[02]

VCCP[01]VCCP[02]

C470

10uF 6.3V 10%

SM

T0805 X5R

C2012X

5R0J106K

TDK

LR(N

U)

C460

10uF 6.3V 10%

SM

T0805 X5R

C2012X

5R0J106K

TDK

LR(N

U)

C448

10uF 6.3V 10%

SM

T0805 X5R

C2012X

5R0J106K

TDK

LR

C457

T220uF 2.5V 20% 9m SMT7343 H=1.9mm V CASE A705V227M002ASE009 SDK(SDK-CAP) LR

C94

10uF 6.3V 10%

SM

T0805 X5R

C2012X

5R0J106K

TDK

LR(N

U)

C109

10uF 6.3V 10%

SM

T0805 X5R

C2012X

5R0J106K

TDK

LR

C453

10uF 6.3V 10%

SM

T0805 X5R

C2012X

5R0J106K

TDK

LR(N

U)

C490

10uF 6.3V 10%

SM

T0805 X5R

C2012X

5R0J106K

TDK

LR

C434

0.1uF 16V 10%

SM

D0603 X

7R LR

12

C435

0.1uF 16V 10%

SM

D0603 X

7R LR

12

C515

0.01uF 16V 10%

SM

T0402 X7R

LR

C438

10uF 6.3V 10%

SM

T0805 X5R

C2012X

5R0J106K

TDK

LR(N

U)

R454100 1% 1/16W SMT0402 LR

C92

10uF 6.3V 10%

SM

T0805 X5R

C2012X

5R0J106K

TDK

LR(N

U)

C451

10uF 6.3V 10%

SM

T0805 X5R

C2012X

5R0J106K

TDK

LR(N

U)

U8D


P6

AE11

A8A11A14A16A19A23AF2

B6B8

B11B13B16B19B21B24C5C8

C11C14C16C19C2

C22C25D1D4D8

D11D13D16D19D23D26

E3E6E8

E11E14E16E19E21E24

F5F8

F11F13F16F19F2

F22F25G4G1

G23G26

H3H6

H21H24

J2J5

J22J25K1K4

K23K26

L3L6

L21L24M2M5

M22M25

N1N4

N23N26

P3 A25AF21AF19AF16AF13AF11AF8AF6A2AE26AE23AE19

P21P24R2R5R22R25T1T4T23T26U3U6U21U24V2V5V22V25W1W4W23W26Y3

Y21Y24AA2AA5AA8AA11AA14AA16AA19AA22AA25AB1AB4AB8AB11AB13AB16AB19AB23AB26AC3AC6AC8AC11AC14AC16AC19AC21AC24AD2AD5AD8AD11AD13AD16AD19AD22AD25AE1AE4

Y6

A4

AE14AE16

AE8

AF25

VSS[082]

VSS[148]

VSS[002]VSS[003]VSS[004]VSS[005]VSS[006]VSS[007]VSS[008]VSS[009]VSS[010]VSS[011]VSS[012]VSS[013]VSS[014]VSS[015]VSS[016]VSS[017]VSS[018]VSS[019]VSS[020]VSS[021]VSS[022]VSS[023]VSS[024]VSS[025]VSS[026]VSS[027]VSS[028]VSS[029]VSS[030]VSS[031]VSS[032]VSS[033]VSS[034]VSS[035]VSS[036]VSS[037]VSS[038]VSS[039]VSS[040]VSS[041]VSS[042]VSS[043]VSS[044]VSS[045]VSS[046]VSS[047]VSS[048]VSS[049]VSS[050]VSS[051]VSS[052]VSS[053]VSS[054]VSS[055]VSS[056]VSS[057]VSS[058]VSS[059]VSS[060]VSS[061]VSS[062]VSS[063]VSS[064]VSS[065]VSS[066]VSS[067]VSS[068]VSS[069]VSS[070]VSS[071]VSS[072]VSS[073]VSS[074]VSS[075]VSS[076]VSS[077]VSS[078]VSS[079]VSS[080]VSS[081] VSS[162]

VSS[161]VSS[160]VSS[159]VSS[158]VSS[157]VSS[156]VSS[155]VSS[154]VSS[153]VSS[152]VSS[151]

VSS[083]VSS[084]VSS[085]VSS[086]VSS[087]VSS[088]VSS[089]VSS[090]VSS[091]VSS[092]VSS[093]VSS[094]VSS[095]VSS[096]VSS[097]VSS[098]VSS[099]VSS[100]VSS[101]VSS[102]VSS[103]VSS[104]VSS[105]

VSS[107]VSS[108]VSS[109]VSS[110]VSS[111]VSS[112]VSS[113]VSS[114]VSS[115]VSS[116]VSS[117]VSS[118]VSS[119]VSS[120]VSS[121]VSS[122]VSS[123]VSS[124]VSS[125]VSS[126]VSS[127]VSS[128]VSS[129]VSS[130]VSS[131]VSS[132]VSS[133]VSS[134]VSS[135]VSS[136]VSS[137]VSS[138]VSS[139]VSS[140]VSS[141]VSS[142]VSS[143]VSS[144]VSS[145]VSS[146]

VSS[106]

VSS[001]

VSS[149]VSS[150]

VSS[147]

VSS[163]

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7

7

6

6

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

THERMAL SENSOR

20mil

10mil

10 milGND

GND

THERMDA

10 mil

10 milTHERMDC10 mil

Minimum

Confidential

30mil

1/29 EMI

30mil

8/9 EMI8/9 EMI

CPU Thermal 0.2


C


MR055 / MR056Title


Date: Sheet of


THRM_VCC

H_THERMDAQSMDAT_PMUQSMCLK_PMU

HOT_DOWN#

QSMCLK_PMU

QSMDAT_PMU

H_THERMDC

FAN1

SMDAT_PMU(43,46)

FAN_PWM(43)

H_THERMDC (8)

SMCLK_PMU(43,46)

H_THERMDA (8)

FAN_SPEED(43)

HOT_DOWN# (43)

3VDDM(12,15,17..20,22..27,29..31,33..35,37,43,45,48..51)

3VDDA(20..24,26,30,31,33..35,40,43,46,48..50)

5VDDM(23,25,27,29,30,36,38,39,48)

3VDDM

5VDDM

5VDDM

5VDDM

3VDDA

3VDDM

3VDDA

5VDDM

Q13

TRANS M-FET-P APM2301AAC-TRL -20V -3A SOT23 3PIN ANPEC LR

G

DS

U27

LNR-IC Temperation Sensor MAX6657MSA+T SOP-8 8PIN MAXIM LR

12

345

6

78 VCC

DXP

DXNOVERT1GND

ALERT

SMBDATASMBCLK

R519100 5% 1/16W SMT0402 LR

D11DIODE ZENER GLZ6.2B 6.2V 20mA MINI-MELF 2PIN PSI LR

PN

C5360.1uF 16V 80-20% SMT0402 Y5V LR

Q12NPN PDTC144EU SOT-323 PHILIPS LR

EC

B

R1111K 5% 1/16W SMT0402 LR

R5312.2K 5% 1/16W SMT0402 LR

R52010K 5% 1/16W SMT0402 LR

C647470pF 50V 10% SMT0402 X7R LR(NU)

CN10

CON HR A1250WV-S-03P SMD 3Pin P=1.25 Wire S/T LR20-24197-30

123

4

5

123

4

5

Q51

TRANS M-FET-N 2N7002 60V 115mA SOT-23 3PIN PSI LR

D S

G

C648

MO-CAP 1000pF 16V 10% SMT0402 X7R LR

Q52

TRANS M-FET-N 2N7002 60V 115mA SOT-23 3PIN PSI LR

D S

G

RP3110K 5% SMT1010 1/16W 4P2R LR

1 24 3

C5372200pF 50V 10% SMT0402 X7R LR

C751000pF 50V 10% SMT0402 X7R LR

C5540.1uF 16V 80-20% SMT0603 Y5V LR

R1121K 5% 1/16W SMT0402 LR

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

H H

G G

F F

E E

D D

C C

B B

A AConfidential

NB GM965 05-23798-01 (REV. C0)NB GL960 05-23843-01

Crestline Host (1/6) 0.2


C


MR055 / MR056Title


Date: Sheet of


H_A#15

H_A#5

H_A#11

H_A#9

H_A#13H_A#14

H_A#6

H_A#12

H_A#16

H_A#8

H_A#10

H_A#3H_A#4

H_A#7

H_A#23

H_A#26

H_A#21

H_A#30

H_A#25

H_A#28H_A#29

H_A#20

H_A#31

H_A#24

H_A#18H_A#17

H_A#27

H_A#19

H_A#22

H_A#[35..3]

H_REQ#0

H_REQ#2

H_REQ#4H_REQ#3

H_REQ#1

H_REQ#[4..0]

H_SWING

H_RCOMP

H_SCOMP#

H_SCOMP

H_SWINGH_RCOMP

H_SCOMP#H_SCOMP

H_AVREF

H_DVREF

H_A#32H_A#33H_A#34H_A#35

H_D#17

H_D#46

H_D#14

H_D#42

H_D#61

H_D#44

H_D#18

H_D#53

H_D#43

H_D#41

H_D#62

H_D#27H_D#28

H_D#8

H_D#31

H_D#34

H_D#19

H_D#47

H_D#45

H_D#55

H_D#[63..0]

H_D#48

H_D#22

H_D#38

H_D#32

H_D#12

H_D#56

H_D#13

H_D#37

H_D#25

H_D#3

H_D#1

H_D#54

H_D#29

H_D#9

H_D#33

H_D#24

H_D#57

H_D#59

H_D#49

H_D#40

H_D#2

H_D#21

H_D#0

H_D#52

H_D#60

H_D#6

H_D#16H_D#15

H_D#39

H_D#26

H_D#30

H_D#10

H_D#35

H_D#50

H_D#11

H_D#4H_D#5

H_D#36

H_D#51

H_D#58

H_D#7

H_D#63

H_D#20

H_D#23

H_ADSTB#0 (8)

H_DINV#3 (8)

H_DSTBP#1 (8)

H_BREQ# (8)

H_D#[63..0](8)

H_HITM# (8)

H_DSTBN#3 (8)

H_DINV#1 (8)

H_DBSY# (8)

H_DSTBP#2 (8)

H_HIT# (8)

H_DSTBN#1 (8)

H_DRDY# (8)

H_DINV#2 (8)

H_DINV#0 (8)

H_DSTBN#2 (8)

H_REQ#[4..0] (8)

H_DSTBP#0 (8)

H_DSTBN#0 (8)

H_ADS# (8)

H_ADSTB#1 (8)

H_A#[35..3] (8)

H_BNR# (8)

H_DSTBP#3 (8)

H_DPWR# (8)

CLK_MCH_BCLK (17)CLK_MCH_BCLK# (17)

H_LOCK# (8)

H_BPRI# (8)

H_CPURST#(8)

H_DEFER# (8)

H_RS#0 (8)H_RS#1 (8)H_RS#2 (8)

H_CPUSLP#(8)

H_TRDY# (8)

1.05VDDM(8,9,14,15,17,21,23,50)

1.05VDDM

1.05VDDM

1.05VDDM

1.05VDDM

1.05VDDM

C4260.1uF 10V 10% SMT0402 X5R LR

HOST

U9A

CRESTLINE_1p0

G17C14K16B13L16J17B14K19P15R17B16H20L19D17M17N16J19B18E19B17

J13

B15E17

B11C11M11C15F16L13

G12H17G20C8E8F12

AM7

B6

AM5

E2

A11H13

G2

M10

M3

W3

AB2

AJ14

AE5

N8H2

C10

N12N9H5

P13K9M2

W10Y8V4

G7

J1N5N3

W6W9N2Y7Y9P4

M6

N1AD12

AE3AD9AC9AC7

AC14AD11AC11

H7

AD7AB1

Y3AC6AE2AC5AG3AJ9AH8

H3

AE9AE11AH12

AJ5AH5AJ6AE7AJ7AJ2

G4

AJ3AH2

AH13

F3

D6

K5L2AD13AE13

H8K7

M7K3AD2AH11

L7K2AC2AJ10

W1

B9A9

B7

E4C6G10

M14E13

B12

C18A19B19N19

B3

E5

C2

E12D7D8

W2

H_A#_10H_A#_11H_A#_12H_A#_13H_A#_14H_A#_15H_A#_16H_A#_17H_A#_18H_A#_19H_A#_20H_A#_21H_A#_22H_A#_23H_A#_24H_A#_25H_A#_26H_A#_27H_A#_28H_A#_29

H_A#_3

H_A#_30H_A#_31

H_A#_4H_A#_5H_A#_6H_A#_7H_A#_8H_A#_9

H_ADS#H_ADSTB#_0H_ADSTB#_1

H_BNR#H_BPRI#

H_BREQ#

HPLL_CLK#

H_CPURST#

HPLL_CLK

H_D#_0

H_REQ#_2H_REQ#_3

H_D#_1

H_D#_10

H_D#_20

H_D#_30

H_D#_40

H_D#_50

H_D#_60

H_D#_8H_D#_9

H_DBSY#

H_D#_11H_D#_12H_D#_13H_D#_14H_D#_15H_D#_16H_D#_17H_D#_18H_D#_19

H_D#_2


H_D#_3


H_D#_4


H_D#_5


H_D#_6

H_D#_61H_D#_62H_D#_63

H_D#_7

H_DEFER#

H_DINV#_0H_DINV#_1H_DINV#_2H_DINV#_3

H_DPWR#H_DRDY#

H_DSTBN#_0H_DSTBN#_1H_DSTBN#_2H_DSTBN#_3

H_DSTBP#_0H_DSTBP#_1H_DSTBP#_2H_DSTBP#_3

H_SCOMP

H_AVREFH_DVREF

H_TRDY#

H_HIT#H_HITM#

H_LOCK#

H_REQ#_0H_REQ#_1

H_REQ#_4

H_A#_32H_A#_33H_A#_34H_A#_35

H_SWING

H_CPUSLP#

H_RCOMP

H_RS#_0H_RS#_1H_RS#_2

H_SCOMP#

R48954.9 1% 1/16W SMT0402 LR Sn

R448100 1% 1/16W SMT0402 LR

R48854.9 1% 1/16W SMT0402 LR Sn

R4531K 1% 1/16W SMT0402 LR

R4582K 1% 1/16W SMT0402 LR

12

R460RES 24.9 1% 1/16W SMT0402 LR

R452SPWR 0 5% 1/16W 0402

R451RES 221 1% 1/16W SMT0402 LR

C4300.1uF 10V 10% SMT0402 X5R LR

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10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

H H

G G

F F

E E

D D

C C

B B

A A

20miles

0 = Dynamic ODT Disabled

1 = DMI * 4 ( Default )

CFG19

CFG [12:13]

CFG [2:0]

1 = SDVO or PCIE X1 are operatingsimulaneously via the PEG port.

00 = Clock Gating Disable

011 = 667 MT/s ( 677MHz ) FSB

11 = Normal Operation ( Default )

CFG20

CFG5

0 = Only SDVO or PCIE X1 is operationl ( default )

001 = 533 MT/s ( 533MHz ) FSB

CFG9

10 = All Z Mode Enable

CFG16

01 = XOR Mode Enabled

0 = DMI * 21 = VCC->1.5V

GMCH Strapping Requirements

0 = Lane Reverse

1 = DMI Lane Reversal Enabled ( Default )

1 = Normal Operation ( Default )

For Crestline

R? , R?80.6 ohmFor Calero20 ohm

0 = VCC->1.05V ( Default )CFG18

(DMI lane)0 = Normal ( Default )1 = Lanes Reversed

(PCIE)

For TV-OUT disable

10mils

Crestline DMI/Graphic (2/6) 0.2


C


MR055 / MR056Title


Date: Sheet of


PM_EXTTS#0

MCH_CFG_19

PM_EXTTS#1

SM_RCOMP_VOH

DFGT_VID_3

MCH_CFG_16

RST_IN#_MCH

DFGT_VID_1DFGT_VID_2

MCH_CFG_13

DFGT_VID_0

SM_RCOMP_VOL

MCH_CFG_9

MCH_CFG_12

SM_RCOMP_VOH

SM_RCOMP_VOL

MCH_CFG_5

MCH_CFG_20

CLK_MCH_OE#

MCH_CFG_5

MCH_CFG_12MCH_CFG_9

MCH_CFG_19

MCH_CFG_16

MCH_CFG_20

MCH_CFG_13

SM_RCOMP#SM_RCOMP

DMI_TXP3DMI_TXP2DMI_TXP1DMI_TXP0

DMI_TXN2DMI_TXN3

DMI_TXN1DMI_TXN0

DMI_RXP1DMI_RXP2

DMI_RXP0

DMI_RXP3

DMI_RXN3DMI_RXN2DMI_RXN1DMI_RXN0

TV_DCONSEL0

PE

G_C

OM

P

TV_YTV_C

PM_EXTTS#0

TV_DCONSEL1

PM_EXTTS#1

TV_DCONSEL1TV_DCONSEL0

CLK_MCH_OE#

CL_REF

DDR_VREF(18,19,50)

MCH_BSEL0(17)

MCH_BSEL2(17)

CL_DATA0 (22)CL_CLK0 (22)

CL_RST#0 (22)

MCH_BSEL1(17)

DREFSSCLK# (17)DREFSSCLK (17)

DREFCLK (17)DREFCLK# (17)

H_DPRSTP#(8,21,45)

CLK_PCIE_3GPLL (17)

PM_DPRSLPVR(22,45)

PLT_RST#(20,22,33..36)

CLK_PCIE_3GPLL# (17)

PM_EXTTS#1(19)DELAY_VR_PWRGOOD(26,45)

PM_EXTTS#0(18)

MPWROK (22,26,43)

DMI_TXP1 (20)DMI_TXP2 (20)

DMI_TXP0 (20)

DMI_TXP3 (20)

DMI_TXN1 (20)

DMI_TXN3 (20)DMI_TXN2 (20)

DMI_TXN0 (20)

M_CLK_DDR#1 (18)M_CLK_DDR#0 (18)

M_CS#1 (18)

M_CS#3 (19)

M_CLK_DDR#4 (19)

M_ODT2 (19)

M_ODT0 (18)

M_CS#2 (19)

M_CLK_DDR#3 (19)

M_CKE3 (19)

M_ODT3 (19)

M_ODT1 (18)

M_CKE4 (19)

M_CLK_DDR1 (18)

MCH_ICH_SYNC# (22)

M_CS#0 (18)

M_CLK_DDR4 (19)

CLK_MCH_OE# (17)

DFGT_VID_0 (51)PM_BMBUSY#(22) DFGT_VID_1 (51)

DFGT_VID_2 (51)DFGT_VID_3 (51)

M_CKE0 (18)

DFGT_VR_EN (51)

M_CKE1 (18)

M_CLK_DDR3 (19)

M_CLK_DDR0 (18)

PM_THRMTRIP#(8,21)

DMI_RXP3 (20)

DMI_RXP0 (20)

DMI_RXP2 (20)DMI_RXP1 (20)

DMI_RXN2 (20)

DMI_RXN0 (20)

DMI_RXN3 (20)

DMI_RXN1 (20)

M_A_A14(18)M_B_A14(19)

LVDS_TXOUT_L2P(24)

LVDS_TXOUT_L0P(24)LVDS_TXOUT_L1P(24)

LVDS_TXCLK1_LN(24)

LVDS_ENABKL(43)

LVDS_TXOUT_L0N(24)

CRT_HSYNC(25)

LVDS_ENALCD(24)

CRT_RED(25)

CRT_GREEN(25)

CRT_BLUE(25)

CRT_VEDAT(25)

LVDS_TXCLK1_LP(24)

LVDS_TXOUT_L1N(24)

CRT_VSYNC(25)

LVDS_DDC_CLK(24)

LVDS_TXOUT_L2N(24)

LVDS_DDC_DATA(24)

CRT_VECLK(25)

1.25VDDM_PEG(15)

1.25VDDM(15,17,23,49)

1.8VDDS(14,15,18,19,50)

3VDDM(10,15,17..20,22..27,29..31,33..35,37,43,45,48..51)

1.8VDDS

1.8VDDS

1.25VDDM

3VDDM

3VDDM

1.25VDDM_PEG

DDR_VREF

DDR_VREF

1.25VDDM_PEG

1.25VDDM

1.8VDDS

3VDDM

R438 4.02K 1% 1/10W SMT0603 LR(NU)

R466 75 1% 1/16W SMT0402 LR

R477 2.2K 5% 1/16W SMT0402 LR

C549

0.01uF 16V 10%

SM

T0402 X7R

LR

R484

RE

S 24.9

1% 1/16W

SM

T0402 LR

R4971K 1% 1/16W SMT0402 LR

R125 RES 20 1% 1/16W SMT0402 LR

R465 150 1% 1/16W SMT0402 LR

R464 10K 5% 1/16W SMT0402 LR

R470 4.02K 1% 1/10W SMT0603 LR

R455 0 5% 1/16W SMT0402 LR

R5221K 1% 1/16W SMT0402 LR

C533

2.2uF 6.3V 80-20%

SM

T0603 Y5V

LR

R478 20K 1% 1/16W SMT0402 LR

C531

2.2uF 6.3V 80-20%

SM

T0603 Y5V

LR

R480 2.2K 5% 1/16W SMT0402 LR

R469 150 1% 1/16W SMT0402 LR

R475RES 2.4K 1% 1/16W SMT0402 LR

R498RES 392 1% 1/16W SMT0402 LR

R467100K 5% 1/16W SMT0402 LR

R5213.01K 1% 1/10W 0603 LR

R439 4.02K 1% 1/10W SMT0603 LR(NU)

C535

0.01uF 16V 10%

SM

T0402 X7R

LR

R441 4.02K 1% 1/10W SMT0603 LR(NU)

R471 SHW 0 5% 1/16W 0402

R437 4.02K 1% 1/10W SMT0603 LR(NU)

R473 150 1% 1/16W SMT0402 LR

R440 4.02K 1% 1/10W SMT0603 LR(NU)

R474 75 1% 1/16W SMT0402 LR

R479 4.02K 1% 1/10W SMT0603 LR(NU)

R459RES 1.3K 1% 1/16W SMT0402 LRC499

0.1uF 10V 10% SMT0402 X5R LR

R468 75 1% 1/16W SMT0402 LR

R501100 5% 1/16W SMT0402 LR

R124 RES 20 1% 1/16W SMT0402 LR

PM

MISC

NC

DDR

MUX

ING

CLK

DMICFG

RSVD

GRAP

HICS

VID

ME

U9B

CRESTLINE_1p0

AV29BB23

BF23

BA25

AW30BA23

BG23

AW25

BE29AY32BD39BG37

BG20BK16BG16BE13

BH39

BH18BJ15BJ14BE16

BL15BK14

AR49AW4

L32N33

N24

P27N27

L35

C21C23F23N23G23J20C20R24L23J23E23E20K23M20M24

G41

L36J36

AW49AV20

B42C42H48H47

AN47AJ38AN42AN46

AM47AJ39AN41AN45

AJ46AJ41AM40AM44

AJ47AJ42AM39AM43

AR37

AL36AM36

AM37

BJ20BK22BF19BH20BK18

L39

AV23

AW23

BC23BD24

AW20BK20

AR12AR13AM12AN13

P36P37R35N35

E35A39C38B39E36

BJ18

BK31BL31

N20G36

J12

AM49AK50AT43AN49AM50

C48D47B44C44

BJ29BE24

B51

BJ51BK51BK50BL50BL49BL3BL2BK1BJ1E1A5

C51B50A50A49

H35K36G39

D20

G40

H10

A35B37B36B34C34

K45K44

A37BK2 R32

SM_CK_0SM_CK_1

RSVD28

SM_CK_3

SM_CK#_0SM_CK#_1

RSVD29

SM_CK#_3

SM_CKE_0SM_CKE_1SM_CKE_3SM_CKE_4

SM_CS#_0SM_CS#_1SM_CS#_2SM_CS#_3

RSVD34

SM_ODT_0SM_ODT_1SM_ODT_2SM_ODT_3

SM_RCOMPSM_RCOMP#

SM_VREF_0SM_VREF_1

CFG_18CFG_19

CFG_2

CFG_0CFG_1

CFG_20

CFG_3CFG_4CFG_5CFG_6CFG_7CFG_8CFG_9CFG_10CFG_11CFG_12CFG_13CFG_14CFG_15CFG_16CFG_17

PM_BM_BUSY#

PM_EXT_TS#_0PM_EXT_TS#_1PWROKRSTIN#

DPLL_REF_CLKDPLL_REF_CLK#

DPLL_REF_SSCLKDPLL_REF_SSCLK#

DMI_RXN_0DMI_RXN_1DMI_RXN_2DMI_RXN_3

DMI_RXP_0DMI_RXP_1DMI_RXP_2DMI_RXP_3

DMI_TXN_0DMI_TXN_1DMI_TXN_2DMI_TXN_3

DMI_TXP_0DMI_TXP_1DMI_TXP_2DMI_TXP_3

RSVD10

RSVD12RSVD11

RSVD13

RSVD22RSVD23RSVD24RSVD25RSVD26

PM_DPRSTP#

SM_CK_4

SM_CK#_4

RSVD30RSVD31

RSVD35RSVD36

RSVD5RSVD6RSVD7RSVD8


GFX_VID_0GFX_VID_1GFX_VID_2GFX_VID_3

GFX_VR_EN

RSVD27

SM_RCOMP_VOHSM_RCOMP_VOL

THERMTRIP#DPRSLPVR

RSVD9

CL_CLKCL_DATA

CL_PWROKCL_RST#CL_VREF


RSVD32RSVD33

RSVD21

NC_1NC_2NC_3NC_4NC_5NC_6NC_7NC_8NC_9NC_10NC_11NC_12NC_13NC_14NC_15

SDVO_CTRL_CLKSDVO_CTRL_DATA

CLK_REQ#

RSVD14

ICH_SYNC#

RSVD20

RSVD41RSVD42RSVD43RSVD44RSVD45

PEG_CLK#PEG_CLK

TEST_1NC_16 TEST_2

LVDS

PCI-EXPRESS GRAPHICS

TVVGA

U9C

CRESTLINE_1p0

N43M43

J51L51N47T45T50U40Y44Y40AB51W49AD44AD40AG46AH49AG45AG41

J50L50M47U44T49T41W45W41AB50Y48AC45AC41AH47AG49AH45AG42

N45

AC46

N51R50T42Y43W46W38AD39

U39

AC49AC42AH39AE49AH44

U47

M45T38T46N50R51U43W42Y47Y39AC38AD47AC50AD43AG39AE50AH43

E39E40C37D35K40

L41L43N41N40D46C45

G51E51F49

E50F48

D44E42

G44B47B45

A47A45

H39

E27G27K27

F27J27L27

H32G32

K33G35

K29J29

F33C32

F29E29

E33

G50

E44

J40

M35P33

PEG_COMPIPEG_COMPO

PEG_RX#_0PEG_RX#_1PEG_RX#_2PEG_RX#_3PEG_RX#_4PEG_RX#_5PEG_RX#_6PEG_RX#_7PEG_RX#_8PEG_RX#_9

PEG_RX#_10PEG_RX#_11PEG_RX#_12PEG_RX#_13PEG_RX#_14PEG_RX#_15

PEG_RX_0PEG_RX_1PEG_RX_2PEG_RX_3PEG_RX_4PEG_RX_5PEG_RX_6PEG_RX_7PEG_RX_8PEG_RX_9

PEG_RX_10PEG_RX_11PEG_RX_12PEG_RX_13PEG_RX_14PEG_RX_15

PEG_TX#_0

PEG_TX#_10

PEG_TX#_3PEG_TX#_4PEG_TX#_5PEG_TX#_6PEG_TX#_7PEG_TX#_8PEG_TX#_9

PEG_TX#_1

PEG_TX#_11PEG_TX#_12PEG_TX#_13PEG_TX#_14PEG_TX#_15

PEG_TX#_2

PEG_TX_0PEG_TX_1PEG_TX_2PEG_TX_3PEG_TX_4PEG_TX_5PEG_TX_6PEG_TX_7PEG_TX_8PEG_TX_9

PEG_TX_10PEG_TX_11PEG_TX_12PEG_TX_13PEG_TX_14PEG_TX_15

L_CTRL_CLKL_CTRL_DATAL_DDC_CLKL_DDC_DATAL_VDD_EN

LVDS_IBGLVDS_VBGLVDS_VREFHLVDS_VREFLLVDSA_CLK#LVDSA_CLK

LVDSA_DATA#_0LVDSA_DATA#_1LVDSA_DATA#_2

LVDSA_DATA_1LVDSA_DATA_2

LVDSB_CLK#LVDSB_CLK

LVDSB_DATA#_0LVDSB_DATA#_1LVDSB_DATA#_2

LVDSB_DATA_1LVDSB_DATA_2

L_BKLT_EN

TVA_DACTVB_DACTVC_DAC

TVA_RTNTVB_RTNTVC_RTN

CRT_BLUECRT_BLUE#

CRT_DDC_CLKCRT_DDC_DATA

CRT_GREENCRT_GREEN#

CRT_HSYNCCRT_TVO_IREF

CRT_REDCRT_RED#

CRT_VSYNC

LVDSA_DATA_0

LVDSB_DATA_0

L_BKLT_CTRL

TV_DCONSEL_0TV_DCONSEL_1

RP22

10K 5% SMT1010 1/16W 4P2R LR

12

43

R5301K 1% 1/16W SMT0402 LR

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

H H

G G

F F

E E

D D

C C

B B

A A

MiniDIN7

2. RGB signals should be routed on the same layer, have a similar number of bends,same number of vias

0.5"

150ohm

1. The minimum spacing between each RGB is 40-mils while 50-mils is preferred

Zo=37.5

FilterTV DAC

Zo=75

0.5"

4. TV DAC route lengths should be lenght match to within 200 mi ls

TV DAC Routing Guideline

TV IRTN

150ohm

0.2"

3. All routing should be done with ground referencing as well

12"

Zo=50

GMCH

Confidential

Crestline DDR2 (3/6) 0.2


C


MR055 / MR056Title


Date: Sheet of


M_A_DQ0M_A_DQ1M_A_DQ2M_A_DQ3M_A_DQ4

M_A_DQ6M_A_DQ5

M_A_DQ7

M_A_DQ15M_A_DQ14M_A_DQ13

M_A_DQ8

M_A_DQ10M_A_DQ9

M_A_DQ11M_A_DQ12

M_A_DQ23M_A_DQ22

M_A_DQ31

M_A_DQ21

M_A_DQ24

M_A_DQ16

M_A_DQ27

M_A_DQ18M_A_DQ17

M_A_DQ19

M_A_DQ28

M_A_DQ30

M_A_DQ26

M_A_DQ20

M_A_DQ29

M_A_DQ25

M_A_DQ56

M_A_DQ39

M_A_DQ61

M_A_DQ53M_A_DQ54

M_A_DQ38

M_A_DQ60

M_A_DQ57

M_A_DQ47

M_A_DQ63

M_A_DQ48

M_A_DQ37

M_A_DQ40

M_A_DQ58

M_A_DQ32

M_A_DQ49

M_A_DQ52

M_A_DQ50

M_A_DQ43

M_A_DQ34M_A_DQ33

M_A_DQ62

M_A_DQ35

M_A_DQ44

M_A_DQ46

M_A_DQ42

M_A_DQ59

M_A_DQ36

M_A_DQ51

M_A_DQ45

M_A_DQ41

M_A_DQ55

M_A_DQ[63..0]

M_A_DM[7..0]

M_B_DQ[63..0]

M_B_DQ0M_B_DQ1M_B_DQ2M_B_DQ3

M_B_DQ7

M_B_DQ4M_B_DQ5M_B_DQ6

M_B_DQ11

M_B_DQ13M_B_DQ14

M_B_DQ8M_B_DQ9

M_B_DQ12

M_B_DQ10

M_B_DQ15

M_B_DQ30

M_B_DQ27

M_B_DQ25

M_B_DQ29

M_B_DQ19

M_B_DQ28

M_B_DQ21M_B_DQ22

M_B_DQ26

M_B_DQ16M_B_DQ17

M_B_DQ20

M_B_DQ18

M_B_DQ31

M_B_DQ23M_B_DQ24

M_B_DQ59

M_B_DQ50

M_B_DQ56

M_B_DQ63

M_B_DQ46

M_B_DQ48

M_B_DQ61

M_B_DQ43

M_B_DQ41

M_B_DQ45

M_B_DQ35

M_B_DQ54

M_B_DQ44

M_B_DQ53

M_B_DQ37M_B_DQ38

M_B_DQ60

M_B_DQ42

M_B_DQ32M_B_DQ33

M_B_DQ62

M_B_DQ52

M_B_DQ36

M_B_DQ58M_B_DQ57

M_B_DQ34

M_B_DQ51

M_B_DQ47

M_B_DQ39

M_B_DQ55

M_B_DQ40

M_B_DQ49

M_B_DM[7..0]

M_B_A[13..0]M_B_A0M_B_A1M_B_A2M_B_A3M_B_A4M_B_A5M_B_A6M_B_A7M_B_A8M_B_A9M_B_A10M_B_A11M_B_A12M_B_A13

M_A_A1M_A_A1

M_A_A5M_A_A5

M_A_A8M_A_A8

M_A_A0M_A_A0

M_A_A6M_A_A6

M_A_A2M_A_A2M_A_A3M_A_A4

M_A_A9

M_A_A12M_A_A13

M_A_A11

M_A_A7

M_A_A10

M_A_A[13..0]

M_A_DQS#3M_A_DQS#3

M_A_DQS4M_A_DQS4M_A_DQS3M_A_DQS3

M_A_DQS#5M_A_DQS#5

M_A_DQS#2M_A_DQS#2M_A_DQS#1M_A_DQS#1

M_A_DQS2M_A_DQS2M_A_DQS1M_A_DQS1

M_A_DQS#0M_A_DQS#0

M_A_DQS#7M_A_DQS#7

M_A_DQS0M_A_DQS0

M_A_DQS7M_A_DQS7

M_A_DQS#6M_A_DQS#6

M_A_DQS#4M_A_DQS#4

M_A_DQS6M_A_DQS6M_A_DQS5

M_A_DQS#[7..0]

M_A_DQS[7..0]

M_A_DM0M_A_DM0M_A_DM1M_A_DM1M_A_DM2M_A_DM2

M_A_DM4M_A_DM4M_A_DM3M_A_DM3

M_A_DM6M_A_DM6M_A_DM5M_A_DM5

M_A_DM7M_A_DM7

M_B_DQS0M_B_DQS1M_B_DQS2M_B_DQS3M_B_DQS4M_B_DQS5M_B_DQS6M_B_DQS7M_B_DQS#0M_B_DQS#1M_B_DQS#2M_B_DQS#3M_B_DQS#4M_B_DQS#5M_B_DQS#6M_B_DQS#7

M_B_DQS[7..0]

M_B_DQS#[7..0]

M_B_DM0M_B_DM1M_B_DM2M_B_DM3M_B_DM4M_B_DM5M_B_DM6M_B_DM7

M_A_DQ[63..0](18) M_B_DQ[63..0](19)

M_B_A[13..0] (19)M_A_A[13..0] (18)

M_A_DQS#[7..0] (18)

M_A_DQS[7..0] (18) M_B_DQS[7..0] (19)

M_B_DQS#[7..0] (19)

M_A_BS0 (18)M_A_BS1 (18)M_A_BS2 (18)M_A_CAS# (18)

M_A_DM[7..0] (18)

M_A_RAS# (18)

M_A_WE# (18)

M_B_BS2 (19)M_B_BS1 (19)M_B_BS0 (19)

M_B_RAS# (19)

M_B_WE# (19)

M_B_DM[7..0] (19)

M_B_CAS# (19)

DDR SYSTEM MEMORY A

U9D

CRESTLINE_1p0

AR43AW44

BG47BJ45BB47BG50BH49BE45

AW43BE44BG42BE40

BA45

BF44BH45BG40BF40AR40AW40AT39

AW36AW41AY41

AY46

AV38AT38AV13AT13

AW11AV11AU15AT11BA13BA11

AR41

BE10BD10BD8AY9

BG10AW9BD7BB9BB5AY7

AR45

AT5AT7AY6BB7AR5AR8AR9AN3AM8

AN10

AT42

AT9AN9AM9

AN11

AW47BB45BF48

BB19BK19BF29

BL17

AT45BD44BD42AW38AW13BG8AY5

AT46BE48BB43BC37BB16BH6BB2AP3

AN6

AT47BD47BC41BA37BA16BH7BC1AP2

BJ19BD20

BC19BE28BG30BJ16

BK27BH28BL24BK28BJ27BJ25BL28BA28

BE18AY20

BA19

SA_DQ_0SA_DQ_1

SA_DQ_10SA_DQ_11SA_DQ_12SA_DQ_13SA_DQ_14SA_DQ_15SA_DQ_16SA_DQ_17SA_DQ_18SA_DQ_19

SA_DQ_2


SA_DQ_3


SA_DQ_4


SA_DQ_5


SA_DQ_6

SA_DQ_60SA_DQ_61SA_DQ_62SA_DQ_63

SA_DQ_7SA_DQ_8SA_DQ_9

SA_BS_0SA_BS_1SA_BS_2

SA_CAS#

SA_DM_0SA_DM_1SA_DM_2SA_DM_3SA_DM_4SA_DM_5SA_DM_6

SA_DQS_0SA_DQS_1SA_DQS_2SA_DQS_3SA_DQS_4SA_DQS_5SA_DQS_6SA_DQS_7

SA_DM_7

SA_DQS#_0SA_DQS#_1SA_DQS#_2SA_DQS#_3SA_DQS#_4SA_DQS#_5SA_DQS#_6SA_DQS#_7

SA_MA_0SA_MA_1

SA_MA_10SA_MA_11SA_MA_12SA_MA_13

SA_MA_2SA_MA_3SA_MA_4SA_MA_5SA_MA_6SA_MA_7SA_MA_8SA_MA_9

SA_RAS#SA_RCVEN#

SA_WE#

DDR SYSTEM MEMORY B

U9E

CRESTLINE_1p0

AP49AR51

BA49BE50BA51AY49BF50BF49BJ50BJ44BJ43BL43

AW50

BK47BK49BK43BK42BJ41BL41BJ37BJ36BK41BJ40

AW51

BL35BK37BK13BE11BK11BC11BC13BE12BC12BG12

AN51

BJ10BL9BK5BL5BK9

BK10BJ8BJ6BF4BH5

AN50

BG1BC2BK3BE4BD3BJ2BA3BB3AR1AT3

AV50

AY2AY3AU2AT2

AV49BA50BB50

AY17BG18BG36

BE17

AR50BD49BK45BL39BH12BJ7BF3AW2

AT50BD50BK46BK39BJ12BL7BE2AV2AU50BC50BL45BK38BK12BK7BF2AV3

BC18BG28

BG17BE37BA39BG13

BG25AW17BF25BE25BA29BC28AY28BD37

AV16AY18

BC17

SB_DQ_0SB_DQ_1

SB_DQ_10SB_DQ_11SB_DQ_12SB_DQ_13SB_DQ_14SB_DQ_15SB_DQ_16SB_DQ_17SB_DQ_18SB_DQ_19

SB_DQ_2


SB_DQ_3


SB_DQ_4


SB_DQ_5


SB_DQ_6

SB_DQ_60SB_DQ_61SB_DQ_62SB_DQ_63

SB_DQ_7SB_DQ_8SB_DQ_9

SB_BS_0SB_BS_1SB_BS_2

SB_CAS#

SB_DM_0SB_DM_1SB_DM_2SB_DM_3SB_DM_4SB_DM_5SB_DM_6SB_DM_7

SB_DQS_0SB_DQS_1SB_DQS_2SB_DQS_3SB_DQS_4SB_DQS_5SB_DQS_6SB_DQS_7

SB_DQS#_0SB_DQS#_1SB_DQS#_2SB_DQS#_3SB_DQS#_4SB_DQS#_5SB_DQS#_6SB_DQS#_7

SB_MA_0SB_MA_1

SB_MA_10SB_MA_11SB_MA_12SB_MA_13

SB_MA_2SB_MA_3SB_MA_4SB_MA_5SB_MA_6SB_MA_7SB_MA_8SB_MA_9

SB_RAS#SB_RCVEN#

SB_WE#

hexa

inf@

hotm

ail.c

om

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

H H

G G

F F

E E

D D

C C

B B

A A

308mils

20mils

VIA=540mA / 40mils

VIA=2400mA / 100mils

VIA=1300mA /60mils

Confidential

VIA=7700mA / 320mils

1/29 EMI

02/07EMI

Crestline Power (4/6) 0.2


C


MR055 / MR056Title


Date: Sheet of


VCCSM_LF7VCCSM_LF6VCCSM_LF5VCCSM_LF4VCCSM_LF3VCCSM_LF2VCCSM_LF1

VGA_VDD(51)

1.05VDDM(8,9,11,15,17,21,23,50)

1.5VDDM(9,15,20,21,23,33..35,49)

1.8VDDS(12,15,18,19,50)

1.05VDDM

1.05VDDM

1.05VDDM

1.05VDDM

1.8VDDS

1.5VDDM

VGA_VDD

1.05VDDM

VGA_VDD

VGA_VDD

1.05VDDM

1.5VDDM

1.8VDDS

+

C82

220uF 2V 20%

15m

7343 PA

NA LR

C480

0.1uF 10V 10%

SMT0402 X5R

LR(N

U)

POWER

VCC

NCTF

VSS

NCTF

VSS

SCB

VCC

AXM

VCC

AXM

NCTF

U9F

CRESTLINE_1p0

AB33

AK37

AP35

U31

AF33AF36AH33AH35AH36AH37AJ33

AK33AK35AK36

AB36

AL33AL35

AB37

AP36AR35AR36

T30T34T35U29

AC33

U32U33U35U36

V33V36V37

AC35AC36AD35

T27T37U24U28V31V35

AB17AB35AD19

AD36

AA19

AD37AF17

AK17

AM24AP26

AR15AR19AR28

Y32

AK24AK23AJ26AJ23

AL24AL26AL28

AM26AM28AM29AM31

AP29AP31

AR31

Y33Y35Y36Y37 A3

B2C1BL1BL51A51

AA33AA35AA36

AJ35

AD33

AF35

AJ36

AK29

AL29AL31AL32

AM17

AM32AM33

AM35

AP28

AP32AP33

AR32AR33

AT31AT33

V32

VCC_NCTF_1

VCC_NCTF_20

VCC_NCTF_29

VCC_NCTF_42

VCC_NCTF_9VCC_NCTF_10VCC_NCTF_11VCC_NCTF_12VCC_NCTF_13VCC_NCTF_14VCC_NCTF_15

VCC_NCTF_17VCC_NCTF_18VCC_NCTF_19

VCC_NCTF_2

VCC_NCTF_24VCC_NCTF_25

VCC_NCTF_3


VCC_NCTF_38VCC_NCTF_39VCC_NCTF_40VCC_NCTF_41

VCC_NCTF_4

VCC_NCTF_43VCC_NCTF_44VCC_NCTF_45VCC_NCTF_46



VSS_NCTF_1VSS_NCTF_2VSS_NCTF_3VSS_NCTF_4VSS_NCTF_5VSS_NCTF_6

VSS_NCTF_8VSS_NCTF_9

VSS_NCTF_10

VCC_NCTF_8

VSS_NCTF_7


VSS_NCTF_14


VSS_NCTF_19VSS_NCTF_20VSS_NCTF_21

VCC_NCTF_33

VCC_AXM_4VCC_AXM_5VCC_AXM_6VCC_AXM_7

VCC_AXM_NCTF_1VCC_AXM_NCTF_2VCC_AXM_NCTF_3VCC_AXM_NCTF_4VCC_AXM_NCTF_5VCC_AXM_NCTF_6VCC_AXM_NCTF_7

VCC_AXM_NCTF_10VCC_AXM_NCTF_11

VCC_AXM_NCTF_17

VCC_NCTF_34VCC_NCTF_35VCC_NCTF_36VCC_NCTF_37 VSS_SCB1

VSS_SCB2VSS_SCB3VSS_SCB4VSS_SCB5VSS_SCB6


VCC_NCTF_16

VCC_NCTF_21

VSS_NCTF_13

VCC_NCTF_22

VCC_AXM_3

VCC_AXM_NCTF_14VCC_AXM_NCTF_15VCC_AXM_NCTF_16

VSS_NCTF_15


VCC_NCTF_23

VSS_NCTF_18



VCC_AXM_2VCC_AXM_1

VCC_NCTF_47

C461

10uF 10V +80-20%

SM

T0805 Y5V

LR(N

U)

C459

0.1uF 10V 10%

SM

T0402 X5R

LR(N

U)

C491

10uF 6.3V 10%

SM

T0805 X5R

C2012X

5R0J106K

TDK

LR(N

U)

C518

0.22uF 10V 10%

SMT0603 X7R

LR

C519

10uF 6.3V 10%

SM

T0805 X5R

C2012X

5R0J106K

TDK

LR(N

U)

C481

0.22uF 10V 10%

SM

T0603 X7R

LR

D13

DIODE SWITCHING 1SS355 80V 100mA SOD-323 2PIN PSI LR

N P

C516

1uF 10V +80-20%

SM

T0603 Y5V

LMK

107F105ZA-T TAIYO

LR

C514

10uF 6.3V 10%

SM

T0805 X5R

C2012X

5R0J106K

TDK

LR(N

U)

C488

1uF 10V +80-20%

0603 Y5V

LR(N

U)

C509

0.1uF 10V 10%

SM

T0402 X5R

LR

C456

0.1uF 16V 10%

SM

D0603 X

7R LR

C497

0.22uF 10V 10%

SM

T0603 X7R

LR

C521

0.47uF 10V 10%

SM

D0603 X

5R LR

12

POWER

VCC

CORE

VCC

SMVC

C GF

X

VCC

GFX

NCTF

VCC

SM L

F

U9G

CRESTLINE_1p0

AC32

AK32AJ31AJ28AH32AH31AH29AF32

AT34

AC31

BA35

BF33

BJ34

AW35AY35BA32BA33

BB33BC32BC33BC35BD32BD35BE32BE33BE35

AU33

BF34BG32BG33BG35BH32BH34BH35BJ32BJ33

AU35

BK32BK33BK34BK35

U17U19U20U21U23U26V16V17V19V20

T18

V21V23V24Y15Y16Y17Y19Y20Y21Y23

T19

Y24Y26Y28Y29AA16AA17AB16AB19AC16AC17

T21

AC19AD15AD16AD17AF16AF19AH15AH16AH17AH19

T22

AJ16AJ17AJ19AK16AK19AL16AL17AL19AL20AL21

T23

AL23AM15AM16AM19

AM21AM23AP15AP16AP17

T25

AP19AP20AP21

U15U16

BL33

AV33AW33

T17AT35

AU32

R20T14

W13W14Y12

AA20AA23AA26AA28AB21AB24AB29AC20AC21AC23AC24AC26AC28AC29AD20AD23AD24AD28AF21AF26

AH20AH21AH23AH24

AP23AP24AR20AR21AR23AR24AR26

R30

AH26

AJ20AN14

AW45BC39BE39BD17BD4AW8AT6

AA31

AD31

AH28

AM20

AU30

V26V28V29Y31

VCC_5

VCC_6VCC_7VCC_8VCC_9VCC_10VCC_11VCC_12

VCC_2

VCC_4

VCC_SM_10

VCC_SM_20

VCC_SM_30

VCC_SM_6VCC_SM_7VCC_SM_8VCC_SM_9

VCC_SM_11VCC_SM_12VCC_SM_13VCC_SM_14VCC_SM_15VCC_SM_16VCC_SM_17VCC_SM_18VCC_SM_19

VCC_SM_2

VCC_SM_21VCC_SM_22VCC_SM_23VCC_SM_24VCC_SM_25VCC_SM_26VCC_SM_27VCC_SM_28VCC_SM_29

VCC_SM_3

VCC_SM_31VCC_SM_32VCC_SM_33VCC_SM_34

VCC_AXG_NCTF_10VCC_AXG_NCTF_11VCC_AXG_NCTF_12VCC_AXG_NCTF_13VCC_AXG_NCTF_14VCC_AXG_NCTF_15VCC_AXG_NCTF_16VCC_AXG_NCTF_17VCC_AXG_NCTF_18VCC_AXG_NCTF_19

VCC_AXG_NCTF_2


VCC_AXG_NCTF_3


VCC_AXG_NCTF_4


VCC_AXG_NCTF_5


VCC_AXG_NCTF_6

VCC_AXG_NCTF_60VCC_AXG_NCTF_61VCC_AXG_NCTF_62VCC_AXG_NCTF_63

VCC_AXG_NCTF_65VCC_AXG_NCTF_66VCC_AXG_NCTF_67VCC_AXG_NCTF_68VCC_AXG_NCTF_69

VCC_AXG_NCTF_7

VCC_AXG_NCTF_70VCC_AXG_NCTF_71VCC_AXG_NCTF_72

VCC_AXG_NCTF_8VCC_AXG_NCTF_9

VCC_SM_35

VCC_SM_4VCC_SM_5

VCC_AXG_NCTF_1VCC_1

VCC_SM_1

VCC_AXG_1VCC_AXG_2VCC_AXG_3VCC_AXG_4VCC_AXG_5VCC_AXG_6VCC_AXG_7VCC_AXG_8VCC_AXG_9VCC_AXG_10VCC_AXG_11VCC_AXG_12VCC_AXG_13VCC_AXG_14VCC_AXG_15VCC_AXG_16VCC_AXG_17VCC_AXG_18VCC_AXG_19VCC_AXG_20VCC_AXG_21VCC_AXG_22VCC_AXG_23VCC_AXG_24VCC_AXG_25

VCC_AXG_27VCC_AXG_28VCC_AXG_29VCC_AXG_30

VCC_AXG_NCTF_73VCC_AXG_NCTF_74VCC_AXG_NCTF_75VCC_AXG_NCTF_76VCC_AXG_NCTF_77VCC_AXG_NCTF_78VCC_AXG_NCTF_79

VCC_13

VCC_AXG_31

VCC_AXG_33VCC_AXG_34

VCC_SM_LF1VCC_SM_LF2VCC_SM_LF3VCC_SM_LF4VCC_SM_LF5VCC_SM_LF6VCC_SM_LF7

VCC_AXG_26

VCC_AXG_32

VCC_3

VCC_AXG_NCTF_64

VCC_SM_36

VCC_AXG_NCTF_80VCC_AXG_NCTF_81VCC_AXG_NCTF_82VCC_AXG_NCTF_83

C505

1uF 10V +80-20%

SM

T0603 Y5V

LMK

107F105ZA-T TAIYO

LR

C471

0.47uF 10V 10%

SMD

0603 X5R LR

12

C487

0.1uF 16V 10%

SMD

0603 X7R LR

C482

0.1uF 10V 10%

SM

T0402 X5R

LR

R486

0 5% 1/16W SMT0402 LR

C105

10uF 6.3V 10%

SM

T0805 X5R

C2012X

5R0J106K

TDK

LR(N

U)

C496

0.1uF 10V 10%

SM

T0402 X5R

LR

C503

0.22uF 10V 10%

SM

T0603 X7R

LR

C489

10uF 6.3V 10%

SM

T0805 X5R

C2012X

5R0J106K

TDK

LR(N

U)

+

C81

220uF 2V 20%

15m

7343 PA

NA

LR(N

U)

C512

0.1uF 10V 10%

SMT0402 X5R

LR

C476

0.1uF 10V 10%

SMT0402 X5R

LR

R118

10 5% 1/16W SMT0402 LR

1 2

C520

0.22uF 10V 10%

SM

T0603 X7R

LR

C479

0.1uF 16V 10%

SM

D0603 X

7R LR

+

C552

220uF 2V 20%

15m

7343 PA

NA LR

C469

0.22uF 10V 10%

SM

T0603 X7R

LR

C474

0.1uF 10V 10%

SM

T0402 X5R

LR

C508

0.1uF 10V 10%

SM

T0402 X5R

LR

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

H H

G G

F F

E E

D D

C C

B B

A A

VIA=100mA / 10mils

VIA=250mA / 10mils

VIA=80mA / 10mils

VIA=200mA / 10mils

VIA=5mA / 10mils

VIA=1200mA / 60mils

0.1uf caps in 1.5VDDM_xPLLneed to be located as edge capswithin 200mils

10mils

VIA=80mA / 10mils

VIA=150mA / 10mils

VIA=200mA / 20mils

VIA=100mA / 10mils

VIA=100mA / 10mils

VIA=850mA / 40mils

20mils

20mils

(24mA)

VIA=200mA / 20mils

Caps used in 2.5VDDM_CRTDACshould be within 250mils ofedge

VIA=50mA / 10mils

VIA=350mA / 20mils

VIA=250mA / 10mils

(70mA)

VIA=100mA / 10mils

20060117A-EMI

20mils

(24mA)

Confidential

50mA

150mA

80mA

80mA

100mA

10mA

100mA

150mA

5mA

10mA

80mA

40mA

40mA

40mA

500mA

250mA

Caps used in 1.5VDDM_TVDACand 1.5VDDM_QTVDAC shouldbe within 250mils of edge

7/9 BOM

Crestline Power (5/6) 0.2


Custom


MR055 / MR056Title


Date: Sheet of


VTT_LF3VTT_LF2VTT_LF1

1.25VDDM_PEGPLL

1.05VDDM(8,9,11,14,17,21,23,50)

1.25VDDM_PEG(12)

1.25VDDM(12,17,23,49)

1.5VDDM(9,14,20,21,23,33..35,49)

1.8VDDS(12,14,18,19,50)

3VDDM(10,12,17..20,22..27,29..31,33..35,37,43,45,48..51)

1.05VDDM

1.05VDDM

1.05VDDM

1.05VDDM

1.5VDDM

1.25VDDM

1.25VDDM

1.25VDDM

3VDDM

1.25VDDM

1.25VDDM

1.25VDDM

3VDDM

1.25VDDM

1.25VDDM

1.8VDDS

1.25VDDM_PEG

1.25VDDM

1.25VDDM

1.25VDDM

1.25VDDM_MPLL

1.25VDDM_HPLL

1.25VDDM_DPLLB

1.25VDDM_DPLLA

1.25VDDM_MPLL

1.25VDDM_HPLL

3VDDM_HV

1.25VDDM_DPLLA

1.25VDDM_DPLLB3VDDM

1.8VDDS_TXLVDS

1.8VDDS

1.8VDDS

3VDDM_TVDACA

VCCA_TVDAC

3VDDM_TVDACA

3VDDM_TVDACC

3VDDM_TVDACB

3VDDM_TVDACC

3VDDM_TVDACB

VCCA_TVDAC

3VDDM

3VDDM

1.8VDDS_TXLVDS

3VDDM_HV

1.05VDDM

1.25VDDM_PEG

1.25VDDM

1.5VDDM

1.8VDDS

3VDDM

1.25VDDM_PEGPLL

1.25VDDM_PEGPLL

C467

10uF 10V 10%

SM

T0805 X5R T=1.25m

m C

2012X5R1A106KT TD

K LR

R5030 5% 1/10W SMT0603 LR

C4120.1uF 10V 10% SMT0402 X5R LR

L54 SPWR 0 5% 1/16W 0603

C528

0.1uF 10V 10% SMT0402 X5R LR

R4940 5% 1/10W SMT0603 LR(NU)

C4170.022uF 16V 10% SMT0402 X7R LR

C501

0.1uF 10V 10%

SM

T0402 X5R

LR

L52

100MHz 600 SMT0603 FCM1608KF-601T02 TAI-TECH LR

C507

1uF 10V +80-20% SMT0603 Y5V LMK107F105ZA-T TAIYO LR

C425

0.1uF 10V 10% SMT0402 X5R LR

R4900 5% 1/10W SMT0603 LR

C4310.1uF 10V 10% SMT0402 X5R LR

C4490.022uF 16V 10% SMT0402 X7R LR

C91

4.7uF 6.3V 10% SMT0805 X5R C2012X5R0J475KT TDK LR

+

C118T100uF 2V 20%

ES

R=18m

SM

T7343 EEFCD

0D101ER

PANASO

NIC

LR

C4270.1uF 10V 10% SMT0402 X5R LR

C4550.1uF 10V 10% SMT0402 X5R LR

C4390.1uF 10V 10% SMT0402 X5R LR

R444

10 5% 1/16W SMT0402 LR1 2

C1140.1uF 10V 10% SMT0402 X5R LR

C4650.022uF 16V 10% SMT0402 X7R LR

L48

SPWR 0 5% 1/16W 0603

R4821 1% 1/10W SMT0603 LR

C50010uF 10V 10% SMT0805 X5R T=1.25mm C2012X5R1A106KT TDK LR


C463

0.1uF 10V 10% SMT0402 X5R LR

C4460.1uF 10V 10% SMT0402 X5R LR

R446 0 5% 1/16W SMT0402 LR

R4910 5% 1/10W SMT0603 LR(NU)

C4450.1uF 10V 10% SMT0402 X5R LR

C1122.2uF 10V 10% SMT0603 X5R C1608X5R1A225KT TDK LR

R4920 5% 1/10W SMT0603 LR(NU)

R4570 5% 1/16W SMT0402 LR


C492

0.47uF 10V 10%

SMD

0603 X5R LR

12

C504

4.7uF 6.3V 10%

SM

T0805 X5R

C2012X

5R0J475K

T TDK LR


R4350 5% 1/10W SMT0603 LR

C4420.1uF 10V 10% SMT0402 X5R LR

C423

0.47uF 10V 10%

SM

D0603 X

5R LR

12

L55 SPWR 0 5% 1/16W 0603

C511

1uF 10V +80-20%

SM

T0603 Y5V

LMK

107F105ZA-T TAIYO

LR

C4440.1uF 10V 10% SMT0402 X5R LR

R447 0 5% 1/16W SMT0402 LR


POWER

CRT

PLL

A PE

GA

SMTV

D TV

/CRT

LVDS VT

TLF

PEG

SM C

KAX

DAX

FVT

T

DMI

HV

A CK

A LV

DS

U9H

CRESTLINE_1p0

T2R3R2R1

M32

K50

U51

A33B33

B49

H49

AL2

A41

AM2

C25B25C27B27B28A28

U48

T7T6T5T3

T11T10T9

J32

AN2

U13U12

U9U8U7U5U3U2U1T13

U11

BC29BB29

A30

L29

A7F2AH1

AH50AH51

BK24BK23BJ24BJ23

J41

N28

AU28AU24

AT25

B23B21A21

AW18AV19AU19AU18AU17

AT22AT21AT19

AJ50

A43

B32

B41

K49

C40B40

AD51

AT18AT17AR17AR16

H42

W50W51V49V50

AR29

AT29

AT30

AT23

VTT_19VTT_20VTT_21VTT_22

VCCD_CRT

VCCA_PEG_BG

VCCA_PEG_PLL

VCCA_CRT_DAC_1VCCA_CRT_DAC_2

VCCA_DPLLA

VCCA_DPLLB

VCCA_HPLL

VCCA_LVDS

VCCA_MPLL

VCCA_TVA_DAC_1VCCA_TVA_DAC_2VCCA_TVB_DAC_1VCCA_TVB_DAC_2VCCA_TVC_DAC_1VCCA_TVC_DAC_2

VCCD_PEG_PLL

VTT_15VTT_16VTT_17VTT_18

VTT_12VTT_13VTT_14

VCCSYNC

VCCD_HPLL

VTT_1VTT_2

VTT_4VTT_5VTT_6VTT_7VTT_8VTT_9

VTT_10VTT_11

VTT_3

VCCA_SM_CK_1VCCA_SM_CK_2

VCCA_DAC_BG

VCCD_TVDAC

VTTLF1VTTLF2VTTLF3

VCC_RXR_DMI_1VCC_RXR_DMI_2

VCC_SM_CK_1VCC_SM_CK_2VCC_SM_CK_3VCC_SM_CK_4

VCCD_LVDS_1

VCCD_QDAC

VCC_AXD_2VCC_AXD_3

VCC_AXD_5

VCC_AXF_1VCC_AXF_2VCC_AXF_3

VCCA_SM_1VCCA_SM_2VCCA_SM_3VCCA_SM_4VCCA_SM_5

VCCA_SM_7VCCA_SM_8VCCA_SM_9

VCC_DMI

VCC_TX_LVDS

VSSA_DAC_BG

VSSA_LVDS

VSSA_PEG_BG

VCC_HV_1VCC_HV_2

VCC_PEG_1

VCCA_SM_10VCCA_SM_11VCCA_SM_NCTF_1VCCA_SM_NCTF_2

VCCD_LVDS_2

VCC_PEG_2VCC_PEG_3VCC_PEG_4VCC_PEG_5

VCC_AXD_NCTF

VCC_AXD_4

VCC_AXD_6

VCC_AXD_1

C421 0.1uF 10V 10% SMT0402 X5R LR

C4290.1uF 10V 10% SMT0402 X5R LR

+ C97T100uF 2V 20% ESR=18m SMT7343 EEFCD0D101ER PANASONIC LR

R493

0 5% 1/10W SMT0603 LR

C4640.1uF 10V 10% SMT0402 X5R LR

C43210uF 10V 10% SMT0805 X5R T=1.25mm C2012X5R1A106KT TDK LR(NU)

C420

0.022uF 16V 10% SMT0402 X7R LR

L57 SPWR 0 5% 1/16W 0603

L50 SPWR 0 5% 1/16W 0603

DN1

DIODE SWITCHING 1SS355 80V 100mA SOD-323 2PIN PSI LR

N P

C485

10uF 10V 10% SMT0805 X5R T=1.25mm C2012X5R1A106KT TDK LR(NU)

C4190.1uF 10V 10% SMT0402 X5R LR

C4370.022uF 16V 10% SMT0402 X7R LR

C4180.1uF 10V 10% SMT0402 X5R LR

R472 0 5% 1/16W SMT0402 LR

C436

0.47uF 10V 10%

SM

D0603 X

5R LR

12

L51 SPWR 0 5% 1/16W 0603

C524

10uF 6.3V 10%

SM

T0805 X5R

C2012X

5R0J106K

TDK

LR(N

U)

R5001 1% 1/10W SMT0603 LR

C525

10uF 10V 10%

SM

T0805 X5R

T=1.25mm

C2012X

5R1A

106KT TD

K LR

R5281 1% 1/16W SMT0402 LR

C102

4.7uF 6.3V 10% SMT0805 X5R C2012X5R0J475KT TDK LR

R445

0 5% 1/16W SMT0402 LR

L56100MHz 300 25% SMT0603 HCB1608 KF-301T20 TAI-TECH LR(NU)

C4940.1uF 10V 10% SMT0402 X5R LR

L62INDUCTOR 1uH 5% 245mA SMT2*1.5*1.7mm LQN2015F-1R0JA-C01 TAI-TECH LR

1 2

C4280.022uF 16V 10% SMT0402 X7R LR

C4330.1uF 10V 10% SMT0402 X5R LR

C513

0.1uF 10V 10%

SM

T0402 X5R

LR

C41510uF 10V 10% SMT0805 X5R T=1.25mm C2012X5R1A106KT TDK LR(NU)

L49 SPWR 0 5% 1/16W 0603


C422

0.022uF 16V 10% SMT0402 X7R LR

C414

1uF 10V +80-20% SMT0603 Y5V LMK107F105ZA-T TAIYO LR


C4980.1uF 10V 10% SMT0402 X5R LR



C45410uF 10V +80-20% SMT0805 Y5V LR

C4240.1uF 10V 10% SMT0402 X5R LR

C111

0.47uF 10V 10% SMD0603 X5R LR

12

hexa

inf@

hotm

ail.c

om

88

7

7

6

6

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

55 +/- 15%

Parameter Breakout Guideline

Trace Length-LA (GMCH Breakout)


Trace Length-LB (GMCH Breakout to Via2)

DMI Routing Guideline

Inner Layer : 7 milsNominal Didderential Pair-Pitch

Max = 3600 mils

Max = 400 mils

Max = 3600 mils

Outer Layer : 37 milsInner Layer : 37 mils



Uncoupled Single End Impedance


Pair-to-Pair Pitch

Main Route Guideline

Reference Plane


LA

Nominal Trace Width


GMCH

55 +/- 15%

Ground Ground

Rx


LBTx

Tx

Rx

ICH8M

LC LD LE

LZ LXLY LW LV

Bus-to-Bus PitchOuter Layer : 20 milsInner Layer : 22 mils

Outer Layer : 12 milsInner Layer : 15 mils

Trace Length-LC (Via2 to Via3) Max = 5900 mils

Trace Length-LD (Via3 to ICH7m Breakout)

Trace Length-LE (ICH7m Breakout ) Max = 400 mils

Max = 400 mils

Trace Length-LY (V ia3 to GMCH Breakout) Max = 3600 mils

Max = 400 mils

Max = 5900 mils

Trace Length-LZ (GMCH Breakout)

Max = 3600 milsTrace Length-LW (ICH7m Breakout to Via2)

Trace Length-LX (Via2 to Via3)

Trace Length-LV ( ICH7m Breakout)

Trace Length-L2 (LV+LW+LX+LY+ LZ) Max = 8000 mils

Max = 8000 milsTrace Length-L1 (LA+LB+L C+LD+LE)

Breakout/inLA/LZ

Microstrip Same Routing layer as LA/LZ

LB/LYMain Route

LD/LW

Same Routing lay er as LE/LV

Main RouteLE/LV

Microstrip

Breakout/in

X O

S < 2S

>3W

S = SpacingS = Trace Width

*** When routing near the edge of their reference plane , trace should maintain at least 40mils space to the edge of the plane*** Match the trace lengths of the complementary signals within each differenti al pair to +/- 5 mils

Bus-to-Bus Pitch

LB


Parameter

55 +/- 15%

Breakout Guideline


Rx


LD/LWBreakout/in

Express/Mini Card




Tx

Uncoupled Single End Impedance


Main RouteLA/LZ



LE/LV

LA

Microstrip

LZ

Ground

Stripline

Nominal Trace Width

Pair-to-Pair Pitch

Ground

Outer Layer : 37 mils Outer Layer : 27 mils

PCIE Routing Guideline

Breakout/in


Microstrip

Rx

Main Route Guideline


Nominal Differential Trace S pace

LB/LC/LY


55 +/- 15%

LY

Reference Plane

GMCH

Main Route


Tx

LC

Same Routing layer as LA/LZ














Microstrip

Microstrip

Microstrip

Stripline

Stripline

Stripline

Stripline

Stripline

Stripline

Microstrip

Stripline

Microstrip

Stripline

Microstrip

No routing o

Documents

FIC MR055 MR056 - REV 0.2