DISENO Y ANALISIS DE CIRCUITOS DIGITALES CON VHDL

ALFONSO URQUIA, CARLA MARTIN-VILLALBA

EDITORIAL UNED - 7101201GR01A01

Figuras y Tablas

Material de apoyo a la tutorıa de la asignatura

Ingenierıa de Computadores III

del Grado en Ingenierıa Informatica de la UNED

TEMA 1

Fundamentos del diseno del hardware digital

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%&'(')*+ ),,)-.*)/0),0 1+223/40)0+5 6,708140)5975*+ 0+6,708114:/;<=>?@A BCD EFGHIJ KH LMNKOKHP O QOIRNI KHS TLOS UVWXVYYVZ RNHMH GHMJI TJPRH [LH \]^_B`D EFGHIJ KH LMNKOKHP O QOIRNI KHS TLOS aWVbcVYcdXee RNHMH GHMJI TJPRH [LH UVWX VYYVZ

B`DBCDFig. 1.2

Fig. 1.3

CARRY

buf f er0

CARRY

inst14

CARRY

inst1

CARRY

inst2

CARRY

inst3C

AR

RY

inst

17

CA

RR

Y

inst

4

CA

RR

Y

inst

5

CA

RR

Y

inst

6

CA

RR

Y

inst

7

CARRY

inst8

CARRY

inst9

CARRY

inst10

CARRY

inst11

CARRY

inst12

CARRY

inst13

CARRY

inst15C

AR

RY

inst

19

CA

RR

Y

inst

18

CA

RR

Y

inst

16

in_0 in_1

out

in_2 in_3

in_4

in_5

in_6

in_7

in_8

in_9

in_10

in_11

in_12in_13in_14in_15

Fig. 1.4

fghijgkl mnoil pq rhjqmnstuvwxywuxz{|}~}y��{y �}�{� �}wz{y}� �} z}�z UUTtuvwxywuxz{�} w{��y{v�wx�~�} �{� y}�u�z��{��}� z}�z���������� ��� ���������� ���

Fig. 1.5

��������������� ����

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Fig. 1.6

(not a(2)) and(not a(1)) and(not a(0))

(not a(2)) anda(1) anda(0)

a(2) and(not a(1)) and

a(0)

a(2) anda(1) and

(not a(0))

a(2)

a(1)

a(0)

(p1 or p2) or(p3 or p4)

p1

p2

p3

p4

par

Fig. 1.7

a(2) xor a(1) xor a(0)a(2)

a(1)

a(0)

impar parnot impar

Fig. 1.8

a(0)

a(1)

a(2)

XORXOR

NOT

unit1 unit2 unit3

pars1 s2

Fig. 1.9

process (a) variable tmp : std_logic;

begintmp := '0';for i in 2 downto 0 loop

tmp := tmp xor a(i);end loop;impar <= tmp;

end process;

a(2)

a(1)

a(0)

impar parnot impar

Fig. 1.10

process (a) variable suma, r : integer;

beginsuma := 0;for i in 2 downto 0 loop

if a(i) = '1' thensuma := suma + 1;

end if;end loop;r := suma mod 2;if (r = 0) then

par <= '1';else

par <= '0';end if;

end process;

a(2)

a(1)

a(0)

par

Fig. 1.11

vect_test: processbegin

test_in <= "000"; wait for 200 ns;test_in <= "001"; wait for 200 ns;test_in <= "010"; wait for 200 ns;test_in <= "011"; wait for 200 ns;test_in <= "100"; wait for 200 ns;test_in <= "101"; wait for 200 ns;test_in <= "110"; wait for 200 ns;test_in <= "111"; wait for 200 ns;

end process vect_test;

test_inA[2..0] par

ÉÉÊtest_out

verif : processvariable error_status : boolean;

beginwait on test_in;wait for 100 ns; if ( ( test_in = "000" and test_out = '1' ) or

( test_in = "001" and test_out = '0' ) or( test_in = "010" and test_out = '0' ) or( test_in = "011" and test_out = '1' ) or( test_in = "100" and test_out = '0' ) or( test_in = "101" and test_out = '1' ) or( test_in = "110" and test_out = '1' ) or( test_in = "111" and test_out = '0' ) )

thenerror_status := false;

elseerror_status := true;

end if;assert not error_status

report "Test fallado."severity note;

end process verif;

Fig. 1.12

E

ydd1

Z0

YE

b)a)

Fig. 1.13

Fig. 1.14

Fig. 1.15

Tabla 1.1

Tabla 1.2

TEMA 2

Conceptos basicos de VHDL

Fig. 2.1

bi

sig_in

sig_out

dir

Fig. 2.2

x

y

a

b

Fig. 2.3

xy

a

babx

ya

b

Interpretación del compilador de VHDL sobre el flujo de la señal

a) b)

Fig. 2.4

Fig. 2.5

+−

ËÌÍ ÎÎ

+

ÏÐÎÐÑÐÒ ÓÔÕÓÔÕÐÖÏÏ

×ØFig. 2.6

ÙÚÛÜÝÞßàááâÛãäãßÚÛÜÝÞßäåÛæáßæãâáÞßçÛèãâßÚÛÜÝÞßäåÛæáßæãâáÞßçÛèãâßé çÛèãâ

Fig. 2.7

êë

ìíîïðñòòóìôõôðë

ìíîïðõöì÷òð÷ôóòïðøìùôóðëìíîïðõöì÷òð÷ôóòïðøìùôóðú øìùôó

êëêëìíîïðñòòóìôõôðúìíîïðñòòóìôõôðûìíîïðõöì÷òð÷ôóòïðøìùôóðüìíîïðõöì÷òð÷ôóòïðøìùôóðû

Fig. 2.8

ýþÿ���ÿ������ÿ�ÿ���ÿ�����ÿ���� �����ÿ� ���ÿ�����ÿ���� �����ÿ� ��þ �ÿ� ���þÿ�����ÿ���� �����ÿ� ���

���... �

Fig. 2.9

���������������������������� ��!� ����"!��#��������� ��!� ����"!��$

��"!��%�&�#�$�'��������� ��!� ����"!��&

Fig. 2.10

i0i1

ds0

MUX 2:1

a) b)

Fig. 2.11

i0i1

ds0

()* +,-i0i1

ds0

()* +,-i0i1

ds0

()* +,-i0i1

ds0

()* +,-a3b3

a2b2

a1b1

a0b0

d3

d2

d1

d0

s0

Fig. 2.12

i0(0) i0(1) i0(2) i0(3) i0(4) i0(5) i0(6) i0(7)i1(0) i1(1) i1(2) i1(3) i1(4) i1(5) i1(6) i1(7)

y(0) y(1) y(2) y(3) y(4) y(5) y(6) y(7)

Fig. 2.13

parity_IN(0)xor_0

parity

parity_IN(7)

parity_IN(6)

parity_IN(5)

parity_IN(4)

parity_IN(3)

parity_IN(2)

parity_IN(1)

xor_1xor_2

xor_3xor_4

xor_5

xor_6

Fig. 2.14

0 V

1.5 V

3.5 V

5 V

0 lógico

1 lógico

Valor lógico

indefinido

Fig. 2.15

x

y

z

OR2_1

OR2_2NOT

f

xory

xoryorz

Fig. 2.16

x

not1 not2 not3

and1y

1ns 1ns 1ns

Fig. 2.17

0d

1d

2d

3d

0i

1i

en

0i

1ien 0

d1d

2d

3d

0 – – 0 0 0 0

1 0 0 0 0 0 1

1 0 1 0 0 1 0

1 1 0 0 1 0 0

1 1 1 1 0 0 0

Fig. 2.18

x

y

z

OR2_1

OR2_2NOT

f

xory

xoryorz

Fig. 2.19

01

y

=x0x1

1

0

a) b)

Fig. 2.20

./.. 0123/42354 6789 :9/. 76

01;;; < /. 0123/42354 67. 76

01.. 67/ 76 <3/4; <3.4;

Fig. 2.21

Fig. 2.22

= >??> @+

-

AB ACBDE AFBFG+E ACGH >I !=

+ >G=JHHKLI =CHJG=JH AMN H KLI

Fig. 2.23

OOOPPOPP QRSTUV WXYZFig. 2.24

[\]^]_`abcdeabfbg f^]_`abcdeabfbh [\^]_`abcdeab]bg^]_`abcdeab]bh

f``_c]ibcdeajk f``_c]ibcdea lmno] pq ^]_`abcdeab]bgrf pq ^]_`abcdeabfbgrnstn] pq ^]_`abcdeab]bhrf pq ^]_`abcdeabfbhrnou jkr

Fig. 2.25

vw xvwyxz{|}~��|}x}�yxz{|}~��|}x}��� �{{z~x�}~��|}� ������ �{{z~x�}~��|}� ����x �� yxz{|}~��|}x}������x �� yxz{|}~��|}x}����� ��������� �{{z~x�}~��|}� ����x �� yxz{|}~��|}x}������x �� yxz{|}~��|}x}����� ������ ��� vwyxz{|}~��|}x}�yxz{|}~��|}x}��{{z~x�}~��|}��{{z~x�}~��|}��{{z~x�}~��|}�Fig. 2.26

���� ��������� �� ¡�¢ �£ ¤¥� ¦¤ §�¨©���������£ª« ¦¤ §�¨©�������«�£ª ¡�¢ �¬¤¥� ¦¤ §�¨©���������¬ª« ¦¤ §�¨©�������«�¬ª ¡�¢ ­®¡�¯� ¤¥� ¦¤ §�¨©���������°ª« ¦¤ §�¨©�������«�°ª�¢± ����ª²³´³µ³¶³·³¸

¹²º»¼½¾¿À¼½²½Á¹²º»¼½¾¿À¼½²½·¹²º»¼½¾¿À¼½²½¸¾¿À¼½³²Â¾

ó´³µ³¶³·³¸¹²º»¼½¾¿À¼½Ã½Á¹²º»¼½¾¿À¼½Ã½·¹²º»¼½¾¿À¼½Ã½¸

Fig. 2.27

Tabla 2.1

Tabla 2.2

Tabla 2.3

Tabla 2.4

Tabla 2.5

TEMA 3

Simulacion del codigo VHDL

library IEEE;use IEEE.std_logic_1164.all;

entity resF isend entity resF;

architecture resF of resF issignal s : std_logic;

begin

p1 : processbegin

s <= '1';wait;

end process p1;

p2 : processbegin

s <= '0';wait;

end process p2;

end architecture resF;

std_logic’(‘1’)

std_logic’(‘0’)

s : std_logic

Resuelvestd_logic’(‘X’)

Fig. 3.1

x1

x2s y

retardo = 1 ns retardo = 2 ns

NAND2 OR2

Fig. 3.2

Fig. 3.3

x1

x2 yretardo = 10 ns retardo = 20 ns

AND2OR2x3

s

Fig. 3.4

Fig. 3.5

Fig. 3.6

Fig. 3.7

Fig. 3.8

Fig. 3.9

0δ2δ3δ4δ

Fig. 3.10

Fig. 3.11

Tabla 3.1

Tabla 3.2

Tabla 3.3

Tabla 3.3 (cont.)

TEMA 4

Diseno de logica combinacional

Fig. 4.1

i0i1i2i3

d

s0 s1

ÄÅÆ ÇÈÉ

Fig. 4.2

ÊËÌË

Fig. 4.3

Fig. 4.4

abacarreo_in

res

acarreo_out

d

e

f

cnot_a

g0g1

g2

g3

g4

g5

g6

Fig. 4.5

Fig. 4.6

ix

iy

ic is

1ic +

1n

2n

3n

4n

Fig. 4.7

Fig. 4.8

a

g

d

b

c

f

e

Fig. 4.9

ÍÎÏÐÑ ÒÓ ÔÕÔÖ×ØÙ +

ÍÎÏÐÑ ÒÓ ÔÕÚÛ×ØÙ +

ÍÎÏÜÝ Þß ÚàÚÛ×ØÙ +

ÍÎÏÜÝ ÒÓ ÔÕÔÖ×ØÙ +

áâ ãäåæ

çè éêëì

íî ïðñò

óè óäôõö÷øù åú ûü ñý þÿ�

Fig. 4.10

EQ

xN-1 yN-1

pNpN-1

EQ

x0 y0

p1 p0

EQ

xN-2 yN-2

‘1’

Fig. 4.11

sel(3)

y(7:0)

a(7:0)

b(7:0)

cin(0:0)

sel(3:0)

UnidadLógica

Unidadaritmética

Mux

Fig. 4.12

00000001111100000010011100000100101100001000001100010000110100100000010101000000100110000000000100000000XXX0Y0Y1Y2Y3Y4Y5Y6Y7A0A1A2E

A2

A1

A0

Y7Y6

Y5

Y4Y3

Y2Y1

Y0

Ea) b)

Fig. 4.13

Fig. 4.14

Tabla 4.1

Tabla 4.2

Tabla 4.3

Tabla 4.4

TEMA 5

Registros y memorias

�I �I �I �I�Q�Q�Q�Q

rst

Fig. 5.1

Fig. 5.2

3I 2I 1I 0I

0Q1Q2Q3Q

rst

_Shl In_Shr In

ShrShl

Ld

rst Shr ShlLd Operación

0 0 0 0 Mantiene valor

0 0 0 1 Desplaz. Izq.

0 0 1 – Desplaz. Drcha.

0 1 – – Carga paralelo

1 – – – Reset (carga “0000”)

Fig. 5.3

Fig. 5.4

0Q1Q

rst

_Shr In

Shr

…

31Q

rst Shr Operación

0 0 Mantiene valor

0 1 Desplaz. Drcha.

1 – Reset (carga X“00000000”)

Fig. 5.5

Fig. 5.6

��� ������������

������ ���� ! "#$%&"'( )*+* ,- ��������

���� ./ 011234 567895

:; <=>=

?@A

BCDEFBCDEFBCDEFGHDEFDEF IJ IJ

KLKL,-,-,-KL,-,-,-

Fig. 5.7

Ld

I

O

OE

rstrstLd

clk

Fig. 5.8

MNO PQRSOS PQSRRM PQTU VQSRRM VQTUW XYZ [\ XYZ] \ XYZ] W XYZ \ XYZ] W XYZFig. 5.9

Fig. 5.10

Fig. 5.11

Fig. 5.12

FFD FFD FFD FFD^_`abcde_fghiabcde_fdj

Fig. 5.13

Clock

Serial_out

Q3 Q2 Q1 Q0

D3 D2 D1 D0Serial_inSHSel1SHSel0

Fig. 5.14

ALU

+ - and or

A B

Sel(2..1)

ALU_output

zclk

Sel(0)Registro

Fig. 5.15

ROM

word 0

word 1

word 2

…

addr data

Fig. 5.16

RAM

word 0

word 1

word 2

…addr

data_out

data_in

clk wr_ena

Fig. 5.17

Tabla 5.1

Tabla 5.2

Tabla 5.3

Tabla 5.4

TEMA 6

Diseno de logica secuencial

Registro de estado

Lógica combinacional

clk

entradassalidas

estado actual

próximo estado

Fig. 6.1

0s

1s

2s

kl kmn o mn o

kl kpl pkl kFig. 6.2

x

clK

AD

BDBQ

AQ

y

Fig. 6.3

0 1

0– –0

–1

1–

J K Nuevo estado

0 0 Qt+1=Qt

0 1 Qt+1=0

1 0 Qt+1=1

1 1 Qt+1=not Qt

Fig. 6.4

0 1

qqrssrtt

qqrs srttuvwxy

z{|}Fig. 6.5

Fig. 6.6

~ / 0S � /1S� / 0S

0

1 00

1

1

Fig. 6.7

� / 0S � /1S� / 0S ��� �⋅

��� �⋅��� �

⋅��� �

⋅

��� �⋅ ��� �

⋅

������� ��� ���= =

���� �⋅

Fig. 6.8

Fig. 6.9

Fig. 6.10

�  � ¡¢ £�  �¡¢ £¤S ¥S ¦S§S�  � £¢ ¡ ¡¢ £¡¢ £

Fig. 6.11

Fig. 6.12

¨S ©S ªS«S1

2

3

4

5

6

7

89

10 11

12

13

Fig. 6.13

Fig. 6.14

¬ ­ ®¯ ° ± ²³´ µ ¶· ¸¹ ¸ º» ¹ ¼ ½ ¾¿ ° ± ²³´ µ ¶· ¸¹ ¸ ¸À ¹

Á µ ¶·ÂÃ ÄÃFig. 6.15

1 periodo

Fig. 6.16

ÅÆÇÈÉÊÉ clkÅÆÇÈÉÊÉout1 ÅÆÇÈÉÊÉout2

ÅÆÇÈÉÊÉout3

clk

out1

out2

out3

Fig. 6.17

reset

YY RY

GR

YR

RG

reset’

timeRY

timeRY’ timeYR’

timeGR’

timeGR

timeYR

timeRG’

timeRG

Fig. 6.18

reset

puertaAbierta

coccion

stop_Reset

puertaCerrada

alarmaActivada

puerta’puerta

marcha and t_coccion>0

stop_Reset

puerta

puerta

t_coccion=0

stop_Reset

stop_Reset

t_alarma=0

Fig. 6.19

Q = 0 Q = 1

SR = 10

SR = 01

SR = 00

SR = 01 SR = 10

SR = 00

reset_n0

1

23

5

4

6

Fig. 6.20

Q = 0 Q = 1

1– – –

01– –

0010

000–1– – –

0011

01– – 5

34

12

0011

0010

000–

1– – –

01– –

Fig. 6.21

0s 1s

2s

1

1

0 0

0 0

3s

reset

1

1

0

1

2

3

4

5

6

7

8

Fig. 6.22

cno

t_4

and_1

and_2

and_3

and_4

and_5

or_1

or_2

not_3

clock

reset reset_n

D

D

CLRN

CLRN

Q

Q

state(1)

state(0)

Q1

Q0

not_1

not_2

Q1

Q0

Q1_n

Q0_n

yor_1

yor_2

c_n

yand_1

yand_2

yand_3

yand_4

yand_5

Fig. 6.23

1 / 0S 2 /0S

0 / 0S

1

1 0

03 /1S

10 1

reset

0Fig. 6.24

1 / 0S 2 /0S

0 / 0S

10

03 /1S

10 1

reset

00

1

3

42

56

7 89

10

11

Fig. 6.25

S2 S3 S4

reset

S0 S1‘0’

‘1’ ‘1’ ‘0’ ‘1’ ‘1’

‘0’ ‘1’‘0’

‘0’

Fig. 6.26

reset

puertaAbierta

coccion

stop_Reset

puertaCerrada

alarmaActivada

puerta’ puerta

marcha and t_coccion>0

stop_Reset

puerta

puerta

t_coccion=0

stop_Reset

stop_Reset

t_alarma=0

170

58

10

9

1 6 11

7

3

2

14

16

4

1312

15

Fig. 6.27

Tabla 6.1

Tabla 6.2

Tabla 6.3

Tabla 6.4

Tabla 6.5

Tabla 6.6

TEMA 7

Metodologıa de transferencia entre registros

Lógica de control

Camino de datos

Señales de control

Señales de status

Fig. 7.1

Ë ÌÍÎÏÐÑÎÒ ËÎ ÓÔÕÖ×ÔÑ Ë ÌÓÑØ

Ù+

rÚrÛ+Ú ÜÝÞ

Fig. 7.2

ß àáâãäåæçèåéâ éêæèåëèìâíäèìêéèéââìçîæêïäâìæèëèìâíäèìêéèéââìçîæêïäâìæè ðìäéêéâåñ îìòäèìêóâåôõö÷ø ùúúûöüõùõ ôõö÷ø ùúøõýþùõß àáâãäåæçèéâ âåæêéè ÿ�ãäòê�êçêè�æâìâç óêåêóäéêÿ�ãäòê�êçêè�æâìâç âóåäãîäâìæâ âåæêéè

�ú�õý ùú øöõö�ø þûöúüûõ �ú�õý ùúøöõö�øú�öúüûõ�ú�õý ùú �÷ûöü÷ý�÷õûù÷øú�öúüû÷ø

��� � ô� ô���

����� ô� �� ����Fig. 7.3

Fig. 7.4

Tabla 7.1

Tabla 7.2

Tabla 7.3

Tabla 7.4