File = mux2a1_vhd_altera_131219.pptx

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boole.exe

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library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux2a1 isPort (

s: in std_logic;x: in std_logic;y: in std_logic;z: out std_logic);

end mux2a1;

architecture behavioral of mux2a1 isbegin

z<=((not(s) and x) or (s and y))end behavioral;

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File = mux2a1_131219.vhd

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library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux2a1 isPort (

s: in std_logic;x: in std_logic;y: in std_logic;z: out std_logic);

end mux2a1;

architecture behavioral of mux2a1 isbegin

z<=((not(s) and x) or (s and y))end behavioral;

File = mux2a1_131219.vhd

Manca ; dopo l’istruzione!!! z<=((not(s) and x) or (s and y)) ;

Sommario sintesi mux2a1 usando SW Boole-Deusto

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Per il progetto del MUX2a1 usando MAX+plusII

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