Filter Design HDL Coder User's Guide.pdf

Filter Design HDL Coder 2Users Guide

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The MathWorks, Inc.3 Apple Hill DriveNatick, MA 01760-2098For contact information about worldwide offices, see the MathWorks Web site.Filter Design HDL Coder Users Guide COPYRIGHT 20042010 by The MathWorks, Inc.The software described in this document is furnished under a license agreement. The software may be usedor copied only under the terms of the license agreement. No part of this manual may be photocopied orreproduced in any form without prior written consent from The MathWorks, Inc.FEDERAL ACQUISITION: This provision applies to all acquisitions of the Program and Documentationby, for, or through the federal government of the United States. By accepting delivery of the Programor Documentation, the government hereby agrees that this software or documentation qualifies ascommercial computer software or commercial computer software documentation as such terms are usedor defined in FAR 12.212, DFARS Part 227.72, and DFARS 252.227-7014. Accordingly, the terms andconditions of this Agreement and only those rights specified in this Agreement, shall pertain to and governthe use, modification, reproduction, release, performance, display, and disclosure of the Program andDocumentation by the federal government (or other entity acquiring for or through the federal government)and shall supersede any conflicting contractual terms or conditions. If this License fails to meet thegovernments needs or is inconsistent in any respect with federal procurement law, the government agreesto return the Program and Documentation, unused, to The MathWorks, Inc.

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The MathWorks products are protected by one or more U.S. patents. Please seewww.mathworks.com/patents for more information.

Revision HistoryJune 2004 Online only New for Version 1.0 (Release 14)October 2004 Online only Updated for Version 1.1 (Release 14SP1)March 2005 Online only Updated for Version 1.2 (Release 14SP2)September 2005 Online only Updated for Version 1.3 (Release 14SP3)March 2006 Online only Updated for Version 1.4 (Release 2006a)September 2006 Online only Updated for Version 1.5 (Release 2006b)March 2007 Online only Updated for Version 2.0 (Release 2007a)September 2007 Online only Revised for Version 2.1 (Release 2007b)March 2008 Online only Revised for Version 2.2 (Release 2008a)October 2008 Online only Revised for Version 2.3 (Release 2008b)March 2009 Online only Revised for Version 2.4 (Release 2009a)September 2009 Online only Revised for Version 2.5 (Release 2009b)March 2010 Online only Revised for Version 2.6 (Release 2010a)

Contents

Getting Started

1Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2Automated HDL Code Generation . . . . . . . . . . . . . . . . . . . . 1-2Expected Users . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3Key Features and Components . . . . . . . . . . . . . . . . . . . . . . 1-3Generate HDL Dialog Box the GUI . . . . . . . . . . . . . . . . . 1-5Command-Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6Quantized Filters the Input . . . . . . . . . . . . . . . . . . . . . . . 1-7Filter Properties Input Parameters . . . . . . . . . . . . . . . . . 1-9Generated HDL Files the Output . . . . . . . . . . . . . . . . . . 1-10

Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11Checking Product Requirements . . . . . . . . . . . . . . . . . . . . . 1-11Installing the Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11

Getting Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12Information Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12Online Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13Using Whats This? Context-Sensitive Help . . . . . . . . . . . 1-13Demos and Tutorials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14

Applying HDL Code Generation to the HardwareDesign Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15

Tutorials: Generating HDL Code for Filters

2Creating a Folder for Your Tutorial Files . . . . . . . . . . . . 2-2

Basic FIR Filter Tutorial . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3Designing a Basic FIR Filter in FDATool . . . . . . . . . . . . . . 2-3

v

Quantizing the Basic FIR Filter . . . . . . . . . . . . . . . . . . . . . . 2-5Configuring and Generating the Basic FIR Filters VHDLCode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

Getting Familiar with the Basic FIR Filters GeneratedVHDL Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

Verifying the Basic FIR Filters Generated VHDL Code . . 2-18

Optimized FIR Filter Tutorial . . . . . . . . . . . . . . . . . . . . . . 2-24Designing the FIR Filter in FDATool . . . . . . . . . . . . . . . . . 2-24Quantizing the FIR Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26Configuring and Generating the FIR Filters OptimizedVerilog Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29

Getting Familiar with the FIR Filters Optimized GeneratedVerilog Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39

Verifying the FIR Filters Optimized Generated VerilogCode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41

IIR Filter Tutorial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-48Designing an IIR Filter in FDATool . . . . . . . . . . . . . . . . . . 2-48Quantizing the IIR Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50Configuring and Generating the IIR Filters VHDLCode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-54

Getting Familiar with the IIR Filters Generated VHDLCode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-60

Verifying the IIR Filters Generated VHDL Code . . . . . . . . 2-62

Generating HDL Code for a Filter Design

3Overview of Generating HDL Code for a FilterDesign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

Opening the Generate HDL Dialog Box . . . . . . . . . . . . . . 3-4Opening the Generate HDL Dialog Box from FDATool . . . 3-4Opening the Generate HDL Dialog Box from thefilterbuilder GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

Opening the Generate HDL Dialog Box Using the fdhdltoolCommand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

vi Contents

What Is Generated by Default? . . . . . . . . . . . . . . . . . . . . . . 3-14Default Settings for Generated Files . . . . . . . . . . . . . . . . . . 3-14Default Generation of Script Files . . . . . . . . . . . . . . . . . . . . 3-15Default Settings for Register Resets . . . . . . . . . . . . . . . . . . 3-15Default Settings for General HDL Code . . . . . . . . . . . . . . . 3-15Default Settings for Code Optimizations . . . . . . . . . . . . . . . 3-17Default Settings for Test Benches . . . . . . . . . . . . . . . . . . . . 3-17

What Are Your HDL Requirements? . . . . . . . . . . . . . . . . . 3-19

Setting the Target Language . . . . . . . . . . . . . . . . . . . . . . . . 3-25

Setting the Names and Location for Generated HDLFiles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26Default File Names and Locations . . . . . . . . . . . . . . . . . . . . 3-26Setting Filter Entity and General File Naming Strings . . . 3-27Setting the Location of Generated Files . . . . . . . . . . . . . . . 3-29Setting the Postfix String for VHDL Package Files . . . . . . 3-30Splitting Entity and Architecture Code into SeparateFiles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31

Customizing Reset Specifications . . . . . . . . . . . . . . . . . . . 3-33Setting the Reset Type for Registers . . . . . . . . . . . . . . . . . . 3-33Setting the Asserted Level for the Reset Input Signal . . . . 3-34Suppressing Generation of Reset Logic . . . . . . . . . . . . . . . . 3-35

Customizing the HDL Code . . . . . . . . . . . . . . . . . . . . . . . . . 3-37Specifying a Header Comment . . . . . . . . . . . . . . . . . . . . . . . 3-38Specifying a Prefix for Filter Coefficients . . . . . . . . . . . . . . 3-39Setting the Postfix String for Resolving Entity or ModuleName Conflicts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41

Setting the Postfix String for Resolving HDL ReservedWord Conflicts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42

Setting the Postfix String for Process Block Labels . . . . . . 3-45Setting a Prefix for Component Instance Names . . . . . . . . 3-47Setting a Prefix for Vector Names . . . . . . . . . . . . . . . . . . . . 3-48Naming HDL Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49Specifying the HDL Data Type for Data Ports . . . . . . . . . . 3-50Suppressing Extra Input and Output Registers . . . . . . . . . 3-52Representing Constants with Aggregates . . . . . . . . . . . . . . 3-53Unrolling and Removing VHDL Loops . . . . . . . . . . . . . . . . 3-54Using the VHDL rising_edge Function . . . . . . . . . . . . . . . . 3-55

vii

Suppressing the Generation of VHDL InlineConfigurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-57

Specifying VHDL Syntax for Concatenated Zeros . . . . . . . 3-58Suppressing Verilog Time Scale Directives . . . . . . . . . . . . . 3-59Specifying Input Type Treatment for Addition andSubtraction Operations . . . . . . . . . . . . . . . . . . . . . . . . . . 3-60

Using Complex Data and Coefficients . . . . . . . . . . . . . . . . . 3-62Specifying Programmable Filter Coefficients for FIRFilters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-64

Specifying Programmable Filter Coefficients for IIRFilters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-77

Capturing Code Generation Settings to a Script . . . . . . 3-85

Generating Code for Multirate Filters . . . . . . . . . . . . . . . 3-86Supported Multirate Filter Types . . . . . . . . . . . . . . . . . . . . 3-86Generating Multirate Filter Code . . . . . . . . . . . . . . . . . . . . 3-86Code Generation Options for Multirate Filters . . . . . . . . . . 3-87

Generating Code for Cascade Filters . . . . . . . . . . . . . . . . 3-93Supported Cascade Filter Types . . . . . . . . . . . . . . . . . . . . . 3-93Generating Cascade Filter Code . . . . . . . . . . . . . . . . . . . . . 3-93

Generating Code for Polyphase Sample RateConverters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-97Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-97HDL Implementation for Polyphase Sample RateConverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-97

Generating Code for Multirate Farrow Sample RateConverters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-101Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-101Generating Code for mfilt.farrowsrc Filters at the CommandLine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-101

Generating Code for mfilt.farrowsrc Filters in the GUI . . . 3-103

Generating Code for Single-Rate Farrow Filters . . . . . . 3-105Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-105Code Generation Properties for Farrow Filters . . . . . . . . . . 3-105GUI Options for Farrow Filters . . . . . . . . . . . . . . . . . . . . . . 3-107Farrow Filter Code Generation Mechanics . . . . . . . . . . . . . 3-110

viii Contents

Customizing the Test Bench . . . . . . . . . . . . . . . . . . . . . . . . 3-112Renaming the Test Bench . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-112Specifying a Test Bench Type . . . . . . . . . . . . . . . . . . . . . . . . 3-114Splitting Test Bench Code and Data into Separate Files . . 3-115Configuring the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-117Configuring Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-119Setting a Hold Time for Data Input Signals . . . . . . . . . . . . 3-122Setting an Error Margin for Optimized Filter Code . . . . . . 3-125Setting an Initial Value for Test Bench Inputs . . . . . . . . . . 3-126Setting Test Bench Stimuli . . . . . . . . . . . . . . . . . . . . . . . . . 3-127Setting a Postfix for Reference Signal Names . . . . . . . . . . . 3-129Generating HDL Cosimulation Blocks for Use with HDLSimulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-130

Generating a Simulink Model for Cosimulation with anHDL Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-133

Generating the HDL Code . . . . . . . . . . . . . . . . . . . . . . . . . . 3-142

Generating Scripts for EDA Tools . . . . . . . . . . . . . . . . . . . 3-143Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-143Defaults for Script Generation . . . . . . . . . . . . . . . . . . . . . . . 3-143Custom Script Generation . . . . . . . . . . . . . . . . . . . . . . . . . . 3-144Properties for Controlling Script Generation . . . . . . . . . . . 3-145Controlling Script Generation with the EDA Tool ScriptsDialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-148

Mixed-Language Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-157

Optimizing Generated HDL Code

4Setting Optimizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

Optimizing Generated Code for HDL . . . . . . . . . . . . . . . . 4-3

Optimizing Coefficient Multipliers . . . . . . . . . . . . . . . . . . 4-4

Multiplier Input and Output Pipelining for FIRFilters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

ix

Optimizing Final Summation for FIR Filters . . . . . . . . . 4-8

Speed vs. Area Optimizations for FIR Filters . . . . . . . . . 4-10Overview of Speed vs. Area Optimizations . . . . . . . . . . . . . 4-10Parallel and Serial Architectures . . . . . . . . . . . . . . . . . . . . . 4-11Specifying Speed vs. Area Tradeoffs via generatehdlProperties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15

Selecting Parallel and Serial Architectures in the GenerateHDL Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19

Distributed Arithmetic for FIR Filters . . . . . . . . . . . . . . . 4-27Distributed Arithmetic Overview . . . . . . . . . . . . . . . . . . . . . 4-27Requirements and Considerations for GeneratingDistributed Arithmetic Code . . . . . . . . . . . . . . . . . . . . . . 4-29

DALUTPartition Property . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30DARadix Property . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34Distributed Arithmetic Options in the Generate HDLDialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35

Optimizing the Clock Rate with Pipeline Registers . . . 4-40

Setting Optimizations for Synthesis . . . . . . . . . . . . . . . . . 4-42

Testing a Filter Design

5Testing with an HDL Test Bench . . . . . . . . . . . . . . . . . . . . 5-2Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2Generating the Filter and Test Bench HDL Code . . . . . . . . 5-3Starting the Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6Compiling the Generated Filter and Test Bench Files . . . . 5-7Running the Test Bench Simulation . . . . . . . . . . . . . . . . . . 5-8

x Contents

Property Reference

6Language Selection Properties . . . . . . . . . . . . . . . . . . . . . 6-2

File Naming and Location Properties . . . . . . . . . . . . . . . . 6-2

Reset Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2

Header Comment and General Naming Properties . . . . 6-3

Port Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4

Advanced Coding Properties . . . . . . . . . . . . . . . . . . . . . . . 6-5

Optimization Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6

Test Bench Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7

Script Generation Properties . . . . . . . . . . . . . . . . . . . . . . . 6-9

xi

Properties Alphabetical List

7

Function Reference8

Examples

ATutorials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2

Basic FIR Filter Tutorial . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2

Optimized FIR Filter Tutorial . . . . . . . . . . . . . . . . . . . . . . A-2

IIR Filter Tutorial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2

Speed vs. Area Optimizations for FIR Filters . . . . . . . . . A-3

Index

xii Contents

1Getting Started

Product Overview on page 1-2 Installation on page 1-11 Getting Help on page 1-12 Applying HDL Code Generation to the Hardware Design Process on page1-15

1 Getting Started

Product Overview

In this section...

Automated HDL Code Generation on page 1-2Expected Users on page 1-3Key Features and Components on page 1-3Generate HDL Dialog Box the GUI on page 1-5Command-Line Interface on page 1-6Quantized Filters the Input on page 1-7Filter Properties Input Parameters on page 1-9Generated HDL Files the Output on page 1-10

Automated HDL Code GenerationHardware description language (HDL) code generation accelerates thedevelopment of application-specific integrated circuit (ASIC) and fieldprogrammable gate array (FPGA) designs and bridges the gap betweensystem-level design and hardware development.

Traditionally, system designers and hardware developers use HDLs, such asvery high speed integrated circuit (VHSIC) hardware description language(VHDL) and Verilog, to develop hardware designs. Although HDLs providea proven method for hardware design, the task of coding filter designs, andhardware designs in general, is labor intensive and the use of these languagesfor algorithm and system-level design is not optimal. Users of the FilterDesign HDL Coder product can spend more time on fine-tuning algorithmsand models through rapid prototyping and experimentation and less timeon HDL coding. Architects and designers can efficiently design, analyze,simulate, and transfer system designs to hardware developers.

In a typical use scenario, an architect or designer uses Filter Design ToolboxGUIs (FDATool or filterbuilder) to design a filter. Then, a designer usesthe Filter Design HDL Coder GUI or command-line interface to configure codegeneration options and generate a VHDL or Verilog implementation of thedesign and a corresponding test bench. The generated code adheres to a cleanHDL coding style that enables architects and designers to quickly address

1-2

Product Overview

customizations, as needed. The test bench feature increases confidence inthe correctness of the generated code and saves potential time spent on testbench implementation.

Expected UsersThe Filter Design HDL Coder software is a tool for system and hardwarearchitects and designers who develop, optimize, and verify hardware signalfilters. These designers are experienced with VHDL or Verilog, but canbenefit greatly from a tool that automates HDL code generation. The FilterDesign HDL Coder interface provides designers with efficient means forcreating test signals and test benches that verify algorithms, validatingmodels against standard reference designs, and translate legacy HDLdescriptions into system-level views.

Users are expected to have prerequisite knowledge in the following subjectareas:

Hardware design and system integration VHDL or Verilog HDL simulators

Users are also expected to have experience with the following products:

MATLAB

Filter Design Toolbox

Key Features and ComponentsKey features of the Filter Design HDL Coder software include the following:

Graphical user interface (GUI) accessible from Filter Design and AnalysisTool (FDATool), filterbuilder, or MATLAB command line

MATLAB command-line interface Support for the following discrete-time filter structures:- Finite impulse response (FIR)- Antisymmetric FIR

1-3

1 Getting Started

- Transposed FIR- Symmetric FIR- Second-order section (SOS) infinite impulse response (IIR) Direct Form I- SOS IIR Direct Form I transposed- SOS IIR Direct Form II- SOS IIR Direct Form II transposed- Discrete-Time Scalar- Delay filter- Farrow (fractional delay) filter

Support for the following multirate filter structures:- Cascaded Integrator Comb (CIC) interpolation- Cascaded Integrator Comb (CIC) decimation- Direct-Form Transposed FIR Polyphase Decimator- Direct-Form FIR Polyphase Interpolator- Direct-Form FIR Polyphase Decimator- FIR Hold Interpolator- FIR Linear Interpolator- Direct-Form FIR Polyphase Sample Rate Converter- Farrow sample rate converter

Support for cascade filters (multirate and discrete-time) Generation of code that adheres to a clean HDL coding style Options for optimizing numeric results of generated HDL code Options for specifying parallel, serial (fully, partly or cascade), ordistributed arithmetic architectures for FIR filter realizations

Options for controlling the contents and style of the generated HDL codeand test bench

Test bench generation for validating the generated HDL filter code

1-4

Product Overview

Test bench optionally partitioned into code, data, and helper function files Complex coefficients and complex input signals supported for fully parallelFIR, CIC, and some other filter structures

Support for programmable coefficients for FIR and IIR filter coefficients VHDL and Verilog test bench options Automatic generation of scripts for third-party simulation and synthesistools

Automatic generation of a script that captures all non-default GUI settingsfor HDL code and test bench generation

Automatic generation of HDL Cosimulation blocks for use with third-partyHDL simulators

Automatic generation of a Simulink model that is configured for bothSimulink simulation of your filter design, and cosimulation of your designwith an HDL simulator

Generate HDL Dialog Box the GUIYou access the Filter Design HDL Coder GUI from the FDATool Targetsmenu, the filterbuilder GUI, or the MATLAB command line. Given thatyou have designed a filter object, you can generate HDL code for that filterwith the Generate HDL dialog box. The main dialog box displays the filtersstructure and order in the title bar. The following figure indicates that theinput is a Direct Form FIR filter with an order of 50.

1-5

1 Getting Started

To learn how to use the GUI to customize HDL code generation to meetproject-specific requirements, see Chapter 3, Generating HDL Code fora Filter Design.

Command-Line InterfaceYou also have the option of generating HDL code for a filter with theFilter Design HDL Coder command-line interface. You can apply functionsinteractively at the MATLAB command line or programmatically in aMATLAB program. The following table lists available functions with briefdescriptions. For more detail, see Chapter 8, Function Reference.

1-6

Product Overview

Function Purpose

generatehdl Generate HDL code for quantized filterfdhdltool Open Generate HDL dialog box for quantized filtergeneratetb Generate test bench for quantized filtergeneratetbstimulus Generate and return test bench stimuli

Quantized Filters the InputThe input to the coder is a quantized filter that you design and quantizeusing one of the following products:

Filter Design Toolbox Signal Processing Toolbox

HDL code generation is supported for the following filter structures.

Discrete-time:- Finite impulse response (FIR)- Antisymmetric FIR- Transposed FIR- Symmetric FIR- Second-order section (SOS) infinite impulse response (IIR) Direct Form I- SOS IIR Direct Form I transposed- SOS IIR Direct Form II- SOS IIR Direct Form II transposed- Discrete-Time Scalar- Delay filter- Farrow (fractional delay) filter

Multirate:- Cascaded Integrator Comb (CIC) interpolation

1-7

1 Getting Started

- Cascaded Integrator Comb (CIC) decimation- Direct-Form Transposed FIR Polyphase Decimator- Direct-Form FIR Polyphase Interpolator- Direct-Form FIR Polyphase Decimator- FIR Hold Interpolator- FIR Linear Interpolator- Direct-Form FIR Polyphase Sample Rate Converter- Farrow sample rate converter

Cascade filters (multirate and discrete-time)

Each of these structures (with the exception of the CIC filter structures)supports fixed-point and floating-point (double) realizations.

The CIC filter types support only fixed-point realizations.

The FIR structures also support unsigned fixed-point coefficients.

Note The coder does not support zero order filters, both in FIR and IIRsections.

The quantized filter must have the following data format characteristics:

Fixed-point Double floating-point precision

However, use of complex input data and complex coefficients is supported forsome filter types. (See Using Complex Data and Coefficients on page 3-62.)

When designing a filter for HDL code generation, consider how filtercoefficients are specified. If the coefficients for a filter are small in value andthe word size and binary point are large, it is possible for the coder to computeinteger coefficients that are numerically inaccurate. Double-precisioncoefficients support up to 53 bits of precision.

1-8

Product Overview

For information on how to design filter objects and specify filter coefficients,see the documentation for the following products:

Filter Design Toolbox Signal Processing Toolbox

Filter Properties Input ParametersThe coder generates filter and test bench HDL code for a specified quantizedfilter based on the settings of a collection of property name and property valuepairs. The properties and their values

Contribute to the naming of language elements Specify port parameters Determine the use of advanced HDL coding features

All properties have default settings. However, you can customize the HDLoutput to meet project specifications by adjusting the property settings withthe GUI or command-line interface. The GUI enables you to set propertiesassociated with

The HDL language specification File name and location specifications Reset specifications HDL code customizations HDL code optimizations Test bench customizations Generation of script files for third-party Electronic Design Automation(EDA) tools

You can set the same filter properties by specifying property name andproperty value pairs with the functions generatehdl, generatetb, andgeneratetbstimulus interactively at the MATLAB command line or in aMATLAB program.

1-9

1 Getting Started

The property names and property values are not case sensitive and, whenspecifying them, you can abbreviate them to the shortest unique string.

For lists and descriptions of the properties and functions, see Chapter 6,Property Reference and Chapter 8, Function Reference, respectively.

Generated HDL Files the OutputBased on the options and input data you specify, the coder generates filterand filter test bench HDL files as output. If the filter design requires a VHDLpackage, the coder also generates a package file.

The GUI generates all output files at the end of a dialog session. If you chooseto use the command-line interface, you generate the filter and test bench HDLfiles separately with calls to the functions generatehdl and generatetb.

By default, the coder writes output files in a subfolder named hdlsrc, underthe current working folder, and names the files as follows, where name is thevalue of the Name property.

Language File Name

Verilog Filter name.vFilter test bench name_tb.v

VHDL Filter name.vhdFilter test bench name_tb.vhdFilter package (ifrequired)

name_pkg.vhd

1-10

Installation

Installation

In this section...

Checking Product Requirements on page 1-11Installing the Software on page 1-11

Checking Product RequirementsThe coder requires the following software from The MathWorks:

MATLAB Fixed-Point Toolbox Signal Processing Toolbox Filter Design Toolbox

VHDL and Verilog Language SupportThe coder generates code that is compatible with HDL compilers, simulatorsand other tools that support

VHDL versions 87, 93, and 02.Exception: VHDL test benches using double precision data types do notsupport VHDL version 87. (See also Compiling the Generated Filter andTest Bench Files on page 5-7.)

Verilog-2001 (IEEE 1364-2001) or later.

Installing the SoftwareFor information on installing the required software listed above, and optionalsoftware, see the Installation Guide for your platform.

1-11

1 Getting Started

Getting Help

In this section...

Information Overview on page 1-12Online Help on page 1-13Using Whats This? Context-Sensitive Help on page 1-13Demos and Tutorials on page 1-14

Information OverviewThe following information is available with this product:

Chapter 1, Getting Started Explains what the product is, how toinstall it, its applications in the hardwaredesign process, and how to access productdocumentation and online help.

Chapter 2, Tutorials:Generating HDL Code forFilters

Guides you through the process ofgenerating HDL code for a sampling offilters.

Chapter 3, Generating HDLCode for a Filter Design

Explains how to set code generationoptions and generate HDL code for a filterdesign.

Chapter 4, OptimizingGenerated HDL Code

Explains options and techniques youcan use to optimize generated HDLcode for speed, area, latency, and othercharacteristics, and the tradeoffs involvedin the use of optimizations.

Chapter 5, Testing a FilterDesign

Explains how to apply generated testbenches.

Chapter 6, PropertyReference

Lists filter properties by category.

1-12

Getting Help

Chapter 7, Properties Alphabetical List

Provides descriptions of propertiesorganized alphabetically by propertyname.

Chapter 8, FunctionReference

Provides descriptions of the functionsavailable in the products command-lineinterface.

Online HelpThe following online help is available:

Online help in the MATLAB Help browser. Click the Filter Design HDLCoder link in the browsers Contents pane.

Context-sensitive Whats This? help for options that appear in the FilterDesign HDL Coder GUI. Click a GUI Help button or right-click on a GUIoption to display help on that dialog, or item. For more information on usingthe context-sensitive help, see Using Whats This? Context-SensitiveHelp on page 1-13.

Help for the command-line interface functions generatehdl, generatetb,fdhdltool, and generatetbstimulus is accessible with the doc and helpcommands. For example:

doc generatehdlhelp generatehdl

Using Whats This? Context-Sensitive HelpWhats This? context-sensitive help topic is available for each dialog box,pane, and option in the GUI. Use the Whats This? help as needed whileusing the GUI to configure options that control the contents and style of thegenerated HDL code and test bench.

To use the Whats This? help, do the following:

1 Place your cursor over the label or control for an option or in the backgroundfor a pane or dialog box.

1-13

1 Getting Started

2 Right-click. A Whats This? button appears. The following display showsthe Whats This? button appearing after a right-click on the Folder optionin the Target pane of the Generate HDL dialog box.

3 Click Whats This? to view context-sensitive help that describes the option,or dialog box.

Demos and TutorialsDemos and tutorials provided with the product will help you get started. Thedemos give you a quick view of the products capabilities and examples of howyou might apply the product. You can run them with limited product exposure.

The tutorials provide procedural instruction on how to apply product features.The following topics, in Chapter 2, Tutorials: Generating HDL Code forFilters, guide you through three tutorials:

Basic FIR Filter Tutorial on page 2-3 Optimized FIR Filter Tutorial on page 2-24 IIR Filter Tutorial on page 2-48

1-14

Applying HDL Code Generation to the Hardware Design Process

Applying HDL Code Generation to the Hardware DesignProcess

The workflow for applying HDL code generation to the hardware designprocess requires the following steps:

1 Design a filter.

2 Quantize the filter.

3 Review the default property settings that the coder applies to generatedHDL code.

4 Adjust property settings to customize the generated HDL code, asnecessary.

5 Generate the filter and test bench code.

6 Consider and, if appropriate, apply optimization options.

7 Test the generated code in a simulation.

1-15

1 Getting Started

The following figure shows these steps in a flow diagram.

!

1-16

2Tutorials: Generating HDLCode for Filters

Creating a Folder for Your Tutorial Files on page 2-2 Basic FIR Filter Tutorial on page 2-3 Optimized FIR Filter Tutorial on page 2-24 IIR Filter Tutorial on page 2-48

2 Tutorials: Generating HDL Code for Filters

Creating a Folder for Your Tutorial FilesSet up a writable working folder outside your MATLAB installation folderto store files that will be generated as you complete your tutorial work. Thetutorial instructions assume that you create the folder hdlfilter_tutorialson drive C.

2-2

Basic FIR Filter Tutorial


In this section...

Designing a Basic FIR Filter in FDATool on page 2-3Quantizing the Basic FIR Filter on page 2-5Configuring and Generating the Basic FIR Filters VHDL Code on page 2-8Getting Familiar with the Basic FIR Filters Generated VHDL Code onpage 2-16Verifying the Basic FIR Filters Generated VHDL Code on page 2-18

Designing a Basic FIR Filter in FDAToolThis tutorial guides you through the steps for designing a basic quantizeddiscrete-time FIR filter, generating VHDL code for the filter, and verifyingthe VHDL code with a generated test bench.

This section assumes you are familiar with the MATLAB user interface andthe Filter Design & Analysis Tool (FDATool). The following instructionsguide you through the procedure of designing and creating a basic FIR filterusing FDATool:

1 Start the MATLAB software.

2 Set your current folder to the folder you created in Creating a Folder forYour Tutorial Files on page 2-2.

2-3


3 Start the FDATool by entering the fdatool command in the MATLABCommand Window. The Filter Design & Analysis Tool dialog box appears.

4 In the Filter Design & Analysis Tool dialog box, check that the followingfilter options are set:

2-4


Option Value

Response Type LowpassDesign Method FIR EquirippleFilter Order Minimum orderOptions Density Factor: 20Frequency Specifications Units: Hz

Fs: 48000Fpass: 9600Fstop: 12000

Magnitude Specifications Units: dBApass: 1Astop: 80

These settings are for the default filter design that the FDATool createsfor you. If you do not need to make any changes and Design Filter isgrayed out, you are done and can skip to Quantizing the Basic FIR Filteron page 2-5.

5 If you modified any of the options listed in step 4, click Design Filter. TheFDATool creates a filter for the specified design and displays the followingmessage in the FDATool status bar when the task is complete.

Designing Filter... Done

For more information on designing filters with the FDATool, see UsingFDATool with Filter Design Toolbox Software in the Filter Design Toolboxdocumentation.

Quantizing the Basic FIR FilterYou should quantize filters for HDL code generation. To quantize your filter,

1 Open the basic FIR filter design you created in Designing a Basic FIRFilter in FDATool on page 2-3 if it is not already open.

2-5


2 Click the Set Quantization Parameters button in the left-side toolbar.The FDATool displays a Filter arithmetic menu in the bottom half ofits dialog box.

3 Select Fixed-point from the Filter arithmetic list. Then select Specifyall from the Filter precision list. The FDATool displays the first of

2-6


three tabbed panels of quantization parameters across the bottom halfof its dialog box.

You use the quantization options to test the effects of various settings witha goal of optimizing the quantized filters performance and accuracy.

4 Set the quantization parameters as follows:

2-7


Tab Parameter Setting

Coefficients Numerator word length 16Best-precision fraction lengths SelectedUse unsigned representation ClearedScale the numerator coefficientsto fully utilize the entire dynamicrange

Cleared

Input/Output Input word length 16Input fraction length 15Output word length 16

FilterInternals

Rounding mode Floor

Overflow mode SaturateAccum. word length 40

5 Click Apply.

For more information on quantizing filters with the FDATool, see UsingFDATool with Filter Design Toolbox Software in the Filter Design Toolboxdocumentation.

Configuring and Generating the Basic FIR FiltersVHDL CodeAfter you quantize your filter, you are ready to configure coder optionsand generate the filters VHDL code. This section guides you through theprocedure for starting the Filter Design HDL Coder GUI, setting some options,and generating the VHDL code and a test bench for the basic FIR filter youdesigned and quantized in Designing a Basic FIR Filter in FDATool on page2-3 and Quantizing the Basic FIR Filter on page 2-5.

1 Start the Filter Design HDL Coder GUI by selecting Targets > GenerateHDL in the FDATool dialog box. The FDATool displays the GenerateHDL dialog box.

2-8


2 Find the Filter Design HDL Coder online help. Use the online help to learnabout product details or to get answers to questions as you work with thedesigner.a In the MATLAB window, click the Help button in the toolbar or clickHelp > Product Help.

b In the Help browsers Contents pane, select the Filter Design HDLCoder entry.

c Minimize the Help browser.

3 In the Generate HDL dialog box, click the Help button. A smallcontext-sensitive help window opens. The window displays informationabout the dialog box.

2-9


4 Close the Help window.

5 Place your cursor over the Folder label or text box in the Target paneof the Generate HDL dialog box, and right-click. A Whats This? buttonappears.

6 Click Whats This? The context-sensitive help window displaysinformation describing the Folder option. Use the context-sensitive helpas needed while using the GUI to configure the contents and style of thegenerated HDL code. A help topic is available for each option.

7 In the Name text box of the Target pane, replace the default name withbasicfir. This option names the VHDL entity and the file that is tocontain the filters VHDL code.

8 Select the Global settings tab of the GUI. Then select the General tab ofthe Additional settings section of the GUI. Type Tutorial - Basic FIRFilter in the Comment in header text box. The coder adds the commentto the end of the header comment block in each generated file.

2-10


9 Select the Ports tab of the Additional settings section of the GUI.

2-11


10 Change the names of the input and output ports. In the Input port textbox, replace filter_in with data_in. In the Output port text box,replace filter_out with data_out.

11 Clear the check box for the Add input register option. The Ports paneshould now look like the following.

2-12


12 Click on the Test Bench tab in the Generate HDL dialog box. In the Filename text box, replace the default name with basicfir_tb. This optionnames the generated test bench file.

2-13


13 Click Generate to start the code generation process.

The coder displays messages in the MATLAB Command Window as itgenerates the filter and test bench VHDL files:

### Starting VHDL code generation process for filter: basicfir

### Generating: C:\hdlfilter_tutorials\hdlsrc\basicfir.vhd

### Starting generation of basicfir VHDL entity

### Starting generation of basicfir VHDL architecture

### HDL latency is 2 samples

### Successful completion of VHDL code generation process for filter: basicfir

### Starting generation of VHDL Test Bench

### Generating input stimulus

### Done generating input stimulus; length 3429 samples.

### Generating Test bench: C:\hdlfilter_tutorials\hdlsrc\basicfir_tb.vhd

### Please wait ...

2-14


### Done generating VHDL Test Bench

>>

As the messages indicate, the coder creates the folder hdlsrc underyour current working folder and places the files basicfir.vhd andbasicfir_tb.vhd in that folder.

Observe that the messages include hyperlinks to the generated code andtest bench files. By clicking on these hyperlinks, you can open the code filesdirectly into the MATLAB Editor.

The generated VHDL code has the following characteristics: VHDL entity named basicfir. Registers that use asynchronous resets when the reset signal is activehigh (1).

Ports have the following names:

VHDL Port Name

Input data_inOutput data_outClock input clkClock enableinput

clk_enable

Reset input reset

An extra register for handling filter output. Clock input, clock enable input and reset ports are of type STD_LOGICand data input and output ports are of type STD_LOGIC_VECTOR.

Coefficients are named coeffn, where n is the coefficient number,starting with 1.

Type safe representation is used when zeros are concatenated: '0'& '0'...

Registers are generated with the statement ELSIF clk'event ANDclk='1' THEN rather than with the rising_edge function.

2-15


The postfix string _process is appended to process names.

The generated test bench: Is a portable VHDL file. Forces clock, clock enable, and reset input signals. Forces the clock enable input signal to active high. Drives the clock input signal high (1) for 5 nanoseconds and low (0) for5 nanoseconds.

Forces the reset signal for two cycles plus a hold time of 2 nanoseconds. Applies a hold time of 2 nanoseconds to data input signals. For a FIR filter, applies impulse, step, ramp, chirp, and white noisestimulus types.

14 When you have finished generating code, click Close to close the GenerateHDL dialog box.

Getting Familiar with the Basic FIR Filters GeneratedVHDL CodeGet familiar with the filters generated VHDL code by opening and browsingthrough the file basicfir.vhd in an ASCII or HDL simulator editor:

1 Open the generated VHDL filter file basicfir.vhd.

2 Search for basicfir. This line identifies the VHDL module, using thestring you specified for the Name option in the Target pane. See step 5in Configuring and Generating the Basic FIR Filters VHDL Code onpage 2-8.

3 Search for Tutorial. This is where the coder places the text you enteredfor the Comment in header option. See step 10 in Configuring andGenerating the Basic FIR Filters VHDL Code on page 2-8.

4 Search for HDL Code. This section lists coder options you modified inConfiguring and Generating the FIR Filters Optimized Verilog Codeon page 2-29.

2-16


5 Search for Filter Settings. This section describes the filter design andquantization settings as you specified in Designing a Basic FIR Filter inFDATool on page 2-3 and Quantizing the Basic FIR Filter on page 2-5.

6 Search for ENTITY. This line names the VHDL entity, using the stringyou specified for the Name option in the Target pane. See step 5 inConfiguring and Generating the Basic FIR Filters VHDL Code on page2-8.

7 Search for PORT. This PORT declaration defines the filters clock, clockenable, reset, and data input and output ports. The ports for clock, clockenable, and reset signals are named with default strings. The ports fordata input and output are named with the strings you specified for theInput port and Output port options on the Ports tab of the GenerateHDLdialog box. See step 12 in Configuring and Generating the Basic FIRFilters VHDL Code on page 2-8.

8 Search for Constants. This is where the coefficients are defined. They arenamed using the default naming scheme,coeffn, where n is the coefficientnumber, starting with 1.

9 Search for Signals. This is where the filters signals are defined.

10 Search for process. The PROCESS block name Delay_Pipeline_processincludes the default PROCESS block postfix string _process.

11 Search for IF reset. This is where the reset signal is asserted. The default,active high (1), was specified. Also note that the PROCESS block applies thedefault asynchronous reset style when generating VHDL code for registers.

12 Search for ELSIF. This is where the VHDL code checks for rising edgeswhen the filter operates on registers. The default ELSIF clk'eventstatement is used instead of the optional rising_edge function.

13 Search for Output_Register. This is where filter output is written to anoutput register. Code for this register is generated by default. In step13 in Configuring and Generating the Basic FIR Filters VHDL Codeon page 2-8, you cleared the Add input register option, but left theAdd output register selected. Also note that the PROCESS block nameOutput_Register_process includes the default PROCESS block postfixstring _process.

2-17


14 Search for data_out. This is where the filter writes its output data.

Verifying the Basic FIR Filters Generated VHDL CodeThis section explains how to verify the basic FIR filters generated VHDL codewith the generated VHDL test bench. Although this tutorial uses the MentorGraphics ModelSim software as the tool for compiling and simulating theVHDL code, you can use any VHDL simulation tool package.

To verify the filter code, complete the following steps:

1 Start your simulator. When you start the Mentor Graphics ModelSimsimulator, a screen display similar to the following appears.

2 Set the current folder to the folder that contains your generated VHDLfiles. For example:

cd c:/hdlfilter_tutorials/hdlsrc

3 If necessary, create a design library to store the compiled VHDL entities,packages, architectures, and configurations. In the Mentor GraphicsModelSim simulator, you can create a design library with the vlibcommand.

vlib work

2-18


4 Compile the generated filter and test bench VHDL files. In the MentorGraphics ModelSim simulator, you compile VHDL code with the vcomcommand. The following commands compile the filter and filter test benchVHDL code.

vcom basicfir.vhdvcom basicfir_tb.vhd

The following screen display shows this command sequence andinformational messages displayed during compilation.

5 Load the test bench for simulation. The procedure for doing this variesdepending on the simulator you are using. In the Mentor GraphicsModelSim simulator, you load the test bench for simulation with the vsimcommand. For example:

vsim work.basicfir_tb

2-19


The following figure shows the results of loading work.basicfir_tb withthe vsim command.

6 Open a display window for monitoring the simulation as the test benchruns. For example, in the Mentor Graphics ModelSim simulator, you canuse the following command to open a wave window to view the results ofthe simulation as HDL waveforms:

add wave *

2-20


The following wave window displays.

7 To start running the simulation, issue the appropriate command for yoursimulator. For example, in the Mentor Graphics ModelSim simulator, youcan start a simulation with the run command.

2-21


The following display shows the run -all command being used to start asimulation.

As your test bench simulation runs, watch for error messages. If anyerror messages appear, you must interpret them as they pertain to yourfilter design and the HDL code generation options you selected. You mustdetermine whether the results are expected based on the customizationsyou specified when generating the filter VHDL code.

Note The failure message that appears in the preceding display is notflagging an actual error. If the message includes the string Test Complete,the test bench has successfully run to completion. The Failure part of themessage is tied to the mechanism that the coder uses to end the simulation.

2-22


The following wave window shows the simulation results as HDLwaveforms.

2-23


Optimized FIR Filter Tutorial

In this section...

Designing the FIR Filter in FDATool on page 2-24Quantizing the FIR Filter on page 2-26Configuring and Generating the FIR Filters Optimized Verilog Codeon page 2-29Getting Familiar with the FIR Filters Optimized Generated Verilog Codeon page 2-39Verifying the FIR Filters Optimized Generated Verilog Code on page 2-41

Designing the FIR Filter in FDAToolThis tutorial guides you through the steps for designing an optimizedquantized discrete-time FIR filter, generating Verilog code for the filter, andverifying the Verilog code with a generated test bench.

This section assumes you are familiar with the MATLAB user interface andthe Filter Design & Analysis Tool (FDATool).



2-24



4 In the Filter Design & Analysis Tool dialog box, set the following filteroptions:

2-25


Option Value

Response Type LowpassDesign Method FIR EquirippleFilter Order Minimum orderOptions Density Factor: 20Frequency Specifications Units: Hz

Fs: 48000Fpass: 9600Fstop: 12000

Magnitude Specifications Units: dBApass: 1Astop: 80

These settings are for the default filter design that the FDATool creates foryou. If you do not need to make any changes and Design Filter is grayedout, you are done and can skip to Quantizing the FIR Filter on page 2-26.

5 Click Design Filter. The FDATool creates a filter for the specified design.The following message appears in the FDATool status bar when the taskis complete.



Quantizing the FIR FilterYou should quantize filters for HDL code generation. To quantize your filter,

1 Open the FIR filter design you created in Optimized FIR Filter Tutorialon page 2-24 if it is not already open.

2-26


2 Click the Set Quantization Parameters button in the left-side toolbar.The FDATool displays a Filter arithmetic menu in the bottom half ofits dialog box.

2-27


3 Select Fixed-point from the list. Then select Specify all from the Filterprecision list. The FDATool displays the first of three tabbed panels ofquantization parameters across the bottom half of its dialog box.


4 Set the quantization parameters as follows:

2-28


Tab Parameter Setting

Coefficients Numerator word length 16

Best-precision fraction lengths SelectedUse unsigned representation ClearedScale the numerator coefficientsto fully utilize the entire dynamicrange

Cleared

Input/Output Input word length 16Input fraction length 15Output word length 16

FilterInternals

Rounding mode Floor

Overflow mode SaturateAccum. word length 40

5 Click Apply.


Configuring and Generating the FIR Filters OptimizedVerilog CodeAfter you quantize your filter, you are ready to configure coder options andgenerate the filters Verilog code. This section guides you through the processfor starting the GUI, setting some options, and generating the Verilog codeand a test bench for the FIR filter you designed and quantized in Designingthe FIR Filter in FDATool on page 2-24 and Quantizing the FIR Filteron page 2-26.

2-29



2 Select Verilog for the Language option, as shown in the following figure.

2-30


3 In the Name text box of the Target pane, replace the default name withoptfir. This option names the Verilog module and the file that is tocontain the filters Verilog code.

4 In the Filter architecture pane, select the Optimize for HDL option.This option is for generating HDL code that is optimized for performance orspace requirements. When this option is enabled, the coder makes tradeoffsconcerning data types and might ignore your quantization settings toachieve optimizations. When you use the option, keep in mind that youdo so at the cost of potential numeric differences between filter resultsproduced by the original filter object and the simulated results for theoptimized HDL code.

5 Select CSD for the Coefficient multipliers option. This option optimizescoefficient multiplier operations by instructing the coder to replace themwith additions of partial products produced by a canonic signed digit (CSD)technique. This technique minimizes the number of addition operationsrequired for constant multiplication by representing binary numbers witha minimum count of nonzero digits.

6 Select the Add pipeline registers option. For FIR filters, this optionoptimizes final summation. The coder creates a final adder that performspair-wise addition on successive products and includes a stage of pipelineregisters after each level of the tree. When used for FIR filters, this optionalso has the potential for producing numeric differences between resultsproduced by the original filter object and the simulated results for theoptimized HDL code.

7 The Generate HDL dialog box should now appear as shown in the followingfigure.

2-31


8 Select the Global settings tab of the GUI. Then select the General tab ofthe Additional settings section.

In the Comment in header text box, type Tutorial - Optimized FIRFilter. The coder adds the comment to the end of the header commentblock in each generated file.

2-32


9 Select the Ports tab of the Additional settings section of the GUI.

2-33


10 Change the names of the input and output ports. In the Input port textbox, replace filter_in with data_in. In the Output port text box,replace filter_out with data_out.

2-34


11 Clear the check box for the Add input register option. The Ports paneshould now look like the following.

12 Click on the Test Bench tab in the Generate HDL dialog box. In the Filename text box, replace the default name with optfir_tb. This optionnames the generated test bench file.

2-35


13 In the Test Bench pane, click the Configuration tab. Observe that theError margin (bits) option is enabled. This option is enabled becausepreviously selected optimization options (such as Add pipeline registers)can potentially produce numeric results that differ from the resultsproduced by the original filter object. You can use this option to adjustthe number of least significant bits the test bench will ignore duringcomparisons before generating a warning.

2-36


14 In the Generate HDL dialog box, click Generate to start the codegeneration process. When code generation completes, click Close to closethe dialog box.

The coder displays the following messages in the MATLAB CommandWindow as it generates the filter and test bench Verilog files:

### Starting Verilog code generation process for filter: optfir

### Generating: C:\hdlfilter_tutorials\hdlsrc\optfir.v

### Starting generation of optfir Verilog module

### Starting generation of optfir Verilog module body


### Successful completion of Verilog code generation process for filter: optfir

### Starting generation of VERILOG Test Bench


2-37



### Generating Test bench: C:\hdlfilter_tutorials\hdlsrc\optfir_tb.v

### Please wait ...

### Done generating VERILOG Test Bench

As the messages indicate, the coder creates the folder hdlsrc under yourcurrent working folder and places the files optfir.v and optfir_tb.v inthat folder.


The generated Verilog code has the following characteristics: Verilog module named optfir. Registers that use asynchronous resets when the reset signal is activehigh (1).

Generated code that optimizes its use of data types and eliminatesredundant operations.

Coefficient multipliers optimized with the CSD technique. Final summations optimized using a pipelined technique. Ports that have the following names:

Verilog Port Name

Input data_inOutput data_outClock input clkClock enable input clk_enableReset input reset

An extra register for handling filter output. Coefficients named coeffn, where n is the coefficient number, startingwith 1.

2-38



The postfix string _process is appended to sequential (begin) blocknames.

The generated test bench: Is a portable Verilog file. Forces clock, clock enable, and reset input signals. Forces the clock enable input signal to active high. Drives the clock input signal high (1) for 5 nanoseconds and low (0) for5 nanoseconds.

Forces the reset signal for two cycles plus a hold time of 2 nanoseconds. Applies a hold time of 2 nanoseconds to data input signals. Applies an error margin of 4 bits. For a FIR filter, appplies impulse, step, ramp, chirp, and white noisestimulus types.

Getting Familiar with the FIR Filters OptimizedGenerated Verilog CodeGet familiar with the filters optimized generated Verilog code by opening andbrowsing through the file optfir.v in an ASCII or HDL simulator editor:

1 Open the generated Verilog filter file optcfir.v.

2 Search for optfir. This line identifies the Verilog module, using thestring you specified for the Name option in the Target pane. See step 3in Configuring and Generating the FIR Filters Optimized Verilog Codeon page 2-29.

3 Search for Tutorial. This is where the coder places the text you enteredfor the Comment in header option. See step 9 in Configuring andGenerating the FIR Filters Optimized Verilog Code on page 2-29.

2-39


4 Search for HDL Code. This section lists the coder options you modified inConfiguring and Generating the FIR Filters Optimized Verilog Codeon page 2-29.

5 Search for Filter Settings. This section of the VHDL code describesthe filter design and quantization settings as you specified in Designingthe FIR Filter in FDATool on page 2-24 and Quantizing the FIR Filteron page 2-26.

6 Search for module. This line names the Verilog module, using the stringyou specified for the Name option in the Target pane. This line alsodeclares the list of ports, as defined by options on the Ports pane of theGenerate HDLdialog box. The ports for data input and output are namedwith the strings you specified for the Input port and Output port optionson the Ports tab of the Generate HDLdialog box. See steps 3 and 11 inConfiguring and Generating the FIR Filters Optimized Verilog Codeon page 2-29.

7 Search for input. This line and the four lines that follow, declare thedirection mode of each port.

8 Search for Constants. This is where the coefficients are defined. They arenamed using the default naming scheme, coeffn, where n is the coefficientnumber, starting with 1.

9 Search for Signals. This is where the filters signals are defined.

10 Search for sumvector1. This area of code declares the signals forimplementing an instance of a pipelined final adder. Signal declarationsfor four additional pipelined final adders are also included. These signalsare used to implement the pipelined FIR adder style optimization specifiedwith the Add pipeline registers option. See step 7 in Configuring andGenerating the FIR Filters Optimized Verilog Code on page 2-29.

11 Search for process. The block name Delay_Pipeline_process includesthe default block postfix string _process.

12 Search for reset. This is where the reset signal is asserted. The default,active high (1), was specified. Also note that the process applies thedefault asynchronous reset style when generating code for registers.

2-40


13 Search for posedge. This Verilog code checks for rising edges when thefilter operates on registers.

14 Search for sumdelay_pipeline_process1. This block implements thepipeline register stage of the pipeline FIR adder style you specified instep 7 of Configuring and Generating the FIR Filters Optimized VerilogCode on page 2-29.

15 Search for output_register. This is where filter output is written to anoutput register. The code for this register is generated by default. In step12 in Configuring and Generating the FIR Filters Optimized VerilogCode on page 2-29 , you cleared the Add input register option, butleft the Add output register selected. Also note that the process nameOutput_Register_process includes the default process postfix string_process.

16 Search for data_out. This is where the filter writes its output data.

Verifying the FIR Filters Optimized Generated VerilogCodeThis section explains how to verify the FIR filters optimized generatedVerilog code with the generated Verilog test bench. Although this tutorialuses the Mentor Graphics ModelSim simulator as the tool for compiling andsimulating the Verilog code, you can use any HDL simulation tool package.


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1 Start your simulator. When you start the Mentor Graphics ModelSimsimulator, a screen display similar to the following appears.

2 Set the current folder to the folder that contains your generated Verilogfiles. For example:

cd hdlsrc

3 If necessary, create a design library to store the compiled Verilog modules.In the Mentor Graphics ModelSim simulator, you can create a designlibrary with the vlib command.

vlib work

4 Compile the generated filter and test bench Verilog files. In the MentorGraphics ModelSim simulator, you compile Verilog code with the vlogcommand. The following commands compile the filter and filter test benchVerilog code.

vlog optfir.vvlog optfir_tb.v

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vsim optfir_tb

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The following display shows the results of loading optfir_tb with thevsim command.

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6 Open a display window for monitoring the simulation as the test benchruns. For example, in the Mentor Graphics ModelSim simulator, you canuse the following command to open a wave window to view the results ofthe simulation as HDL waveforms:

add wave *

The following wave window opens:

7 To start running the simulation, issue the appropriate command for yoursimulator. For example, in the Mentor Graphics ModelSim simulator, youcan start a simulation with the run command.

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As your test bench simulation runs, watch for error messages. If anyerror messages appear, you must interpret them as they pertain to yourfilter design and the HDL code generation options you selected. You mustdetermine whether the results are expected based on the customizationsyou specified when generating the filter Verilog code.

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IIR Filter Tutorial

In this section...

Designing an IIR Filter in FDATool on page 2-48Quantizing the IIR Filter on page 2-50Configuring and Generating the IIR Filters VHDL Code on page 2-54Getting Familiar with the IIR Filters Generated VHDL Code on page 2-60Verifying the IIR Filters Generated VHDL Code on page 2-62

Designing an IIR Filter in FDAToolThis tutorial guides you through the steps for designing an IIR filter,generating Verilog code for the filter, and verifying the Verilog code with agenerated test bench.

This section guides you through the procedure of designing and creatinga filter for an IIR filter. This section assumes you are familiar with theMATLAB user interface and the Filter Design & Analysis Tool (FDATool).



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IIR Filter Tutorial


4 In the Filter Design & Analysis Tool dialog box, set the following filteroptions:

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Option Value

Response Type HighpassDesign Method IIR ButterworthFilter Order Specify order: 5Frequency Specifications Units: Hz

Fs: 48000Fc: 10800

5 Click Design Filter. The FDATool creates a filter for the specified design.The following message appears in the FDATool status bar when the taskis complete.



Quantizing the IIR FilterYou should quantize filters for HDL code generation. To quantize your filter,

1 Open the IIR filter design you created in Designing an IIR Filter inFDATool on page 2-48 if it is not already open.

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IIR Filter Tutorial

2 Click the Set Quantization Parameters button in the left-side toolbar.The FDATool displays the Filter arithmetic list in the bottom half ofits dialog box.

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3 Select Fixed-point from the list. The FDATool displays the first of threetabbed panels of its dialog box.


4 Select the Filter Internals tab and set Rounding mode to Floor andOverflow Mode to Saturate.

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IIR Filter Tutorial

5 Click Apply. The quantized filter appears as follows.


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Configuring and Generating the IIR Filters VHDL CodeAfter you quantize your filter, you are ready to configure coder optionsand generate the filters VHDL code. This section guides you through theprocedure for starting the Filter Design HDL Coder GUI, setting someoptions, and generating the VHDL code and a test bench for the IIR filter youdesigned and quantized in Designing an IIR Filter in FDATool on page 2-48and Quantizing the IIR Filter on page 2-50:


2 In the Name text box of the Target pane, type iir. This option names theVHDL entity and the file that will contain the filters VHDL code.

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IIR Filter Tutorial

3 Select the Global settings tab of the GUI. Then select the General tab ofthe Additional settings section.

In the Comment in header text box, type Tutorial - IIR Filter. Thecoder adds the comment to the end of the header comment block in eachgenerated file.

4 Select the Ports tab. The Ports pane appears.

5 Clear the check box for the Add output register option. The Ports paneshould now appear as in the following figure.

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6 Select the Advanced tab. The Advanced pane appears.

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IIR Filter Tutorial

7 Select the Use rising_edge for registers option. The Advanced paneshould now appear as in the following figure.

8 Click on the Test bench tab in the Generate HDL dialog box. In the Filename text box, replace the default name with iir_tb. This option namesthe generated test bench file.

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9 In the Generate HDL dialog box, click Generate to start the codegeneration process. When code generation completes, click OK to closethe dialog box.

The coder displays the following messages in the MATLAB CommandWindow as it generates the filter and test bench VHDL files:

### Starting VHDL code generation process for filter: iir


### Generating: H:\hdlsrc\iir.vhd

### Starting generation of iir VHDL entity

### Starting generation of iir VHDL architecture

### Second-order section, # 1


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IIR Filter Tutorial

### First-order section, # 3


### Successful completion of VHDL code generation process for filter: iir

### Starting generation of VHDL Test Bench



### Generating Test bench: H:\hdlsrc\filter_tb.vhd

### Please wait ...

### Done generating VHDL Test Bench



### Generating: H:\hdlsrc\iir.vhd

### Starting generation of iir VHDL entity

### Starting generation of iir VHDL architecture



### First-order section, # 3


### Successful completion of VHDL code generation process for filter: iir

As the messages indicate, the coder creates the folder hdlsrc under yourcurrent working folder and places the files iir.vhd and iir_tb.vhd inthat folder.


The generated VHDL code has the following characteristics: VHDL entity named iir. Registers that use asynchronous resets when the reset signal is activehigh (1).

Ports have the following default names:

VHDL Port Name

Input filter_inOutput filter_out

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VHDL Port Name

Clock input clkClock enable input clk_enableReset input reset

An extra register for handling filter input. Clock input, clock enable input and reset ports are of type STD_LOGICand data input and output ports are of type STD_LOGIC_VECTOR.

Coefficients are named coeffn, where n is the coefficient number,starting with 1.


Registers are generated with the rising_edge function rather than thestatement ELSIF clk'event AND clk='1' THEN.

The postfix string _process is appended to process names.

The generated test bench: Is a portable VHDL file. Forces clock, clock enable, and reset input signals. Forces the clock enable input signal to active high. Drives the clock input signal high (1) for 5 nanoseconds and low (0) for5 nanoseconds.

Forces the reset signal for two cycles plus a hold time of 2 nanoseconds. Applies a hold time of 2 nanoseconds to data input signals. For an IIR filter, applies impulse, step, ramp, chirp, and white noisestimulus types.

Getting Familiar with the IIR Filters Generated VHDLCodeGet familiar with the filters generated VHDL code by opening and browsingthrough the file iir.vhd in an ASCII or HDL simulator editor:

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IIR Filter Tutorial

1 Open the generated VHDL filter file iir.vhd.

2 Search for iir. This line identifies the VHDL module, using the stringyou specified for the Name option in the Target pane. See step 2 inConfiguring and Generating the IIR Filters VHDL Code on page 2-54.

3 Search for Tutorial. This is where the coder places the text you enteredfor the Comment in header option. See step 5 in Configuring andGenerating the IIR Filters VHDL Code on page 2-54.

4 Search for HDL Code. This section lists coder options you modifiedinConfiguring and Generating the IIR Filters VHDL Code on page 2-54.

5 Search for Filter Settings. This section of the VHDL code describesthe filter design and quantization settings as you specified in Designingan IIR Filter in FDATool on page 2-48 and Quantizing the IIR Filteron page 2-50.

6 Search for ENTITY. This line names the VHDL entity, using the stringyou specified for the Name option in the Target pane. See step 2 inConfiguring and Generating the IIR Filters VHDL Code on page 2-54.

7 Search for PORT. This PORT declaration defines the filters clock, clockenable, reset, and data input and output ports. The ports for clock, clockenable, reset, and data input and output signals are named with defaultstrings.

8 Search for CONSTANT. This is where the coefficients are defined. They arenamed using the default naming scheme, coeff_xm_sectionn, where x is aor b, m is the coefficient number, and n is the section number.

9 Search for SIGNAL. This is where the filters signals are defined.

10 Search for input_reg_process. The PROCESS block nameinput_reg_process includes the default PROCESS block postfix string_process. This is where filter input is read from an input register. Codefor this register is generated by default. In step 7 in Configuring andGenerating the Basic FIR Filters VHDL Code on page 2-8, you clearedthe Add output register option, but left the Add input register optionselected.

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11 Search for IF reset. This is where the reset signal is asserted. The default,active high (1), was specified. Also note that the PROCESS block applies thedefault asynchronous reset style when generating VHDL code for registers.

12 Search for ELSIF. This is where the VHDL code checks for rising edgeswhen the filter operates on registers. The rising_edge function is usedas you specified in the Advanced pane of the Generate HDLdialog box.See step 10 in Configuring and Generating the IIR Filters VHDL Codeon page 2-54.

13 Search for Section 1. This is where second-order section 1 data is filtered.Similar sections of VHDL code apply to another second-order section anda first-order section.

14 Search for filter_out. This is where the filter writes its output data.

Verifying the IIR Filters Generated VHDL CodeThis sections explains how to verify the IIR filters generated VHDL codewith the generated VHDL test bench. Although this tutorial uses theMentorGraphics ModelSim simulator as the tool for compiling and simulating theVHDL code, you can use any HDL simulation tool package.


1 Start your simulator. When you start theMentor Graphics ModelSimsimulator, a screen display similar to the following appears.

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IIR Filter Tutorial

2 Set the current folder to the folder that contains your generated VHDLfiles. For example:

cd hdlsrc

3 If necessary, create a design library to store the compiled VHDL entities,packages, architectures, and configurations. In theMentor GraphicsModelSim simulator, you can create a design library with the vlibcommand.

vlib work

4 Compile the generated filter and test bench VHDL files. In the MentorGraphics ModelSim simulator, you compile VHDL code with the vcomcommand. The following the commands compile the filter and filter testbench VHDL code.

vcom iir.vhdvcom iir_tb.vhd

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vsim work.iir_tb

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IIR Filter Tutorial

The following display shows the results of loading work.iir_tb with thevsim command.

6 Open a display window for monitoring the simulation as the test benchruns. For example, in the Mentor Graphics ModelSim simulator, you canuse the following command to open a wave window to view the results ofthe simulation as HDL waveforms.

add wave *

2-65


The following wave window displays.

7 To start running the simulation, issue the appropriate command for yoursimulator. For example, in theMentor Graphics ModelSim simulator, youcan start a simulation with the run command.

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IIR Filter Tutorial


As your test bench simulation runs, watch for error messages. If anyerror messages appear, you must interpret them as they pertain to yourfilter design and the HDL code generation options you selected. You mustdetermine whether the results are expected based on the customizationsyou specified when generating the filter VHDL code.

Note

The warning messages that note Time: 0 ns in the preceding displayare not errors and you can ignore them.

The failure message that appears in the preceding display is notflagging an error. If the message includes the string Test Complete,the test bench has successfully run to completion. The Failure part ofthe message is tied to the mechanism that the coder uses to end thesimulation.

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3Generating HDL Code for aFilter Design

Overview of Generating HDL Code for a Filter Design on page 3-2 Opening the Generate HDL Dialog Box on page 3-4 What Is Generated by Default? on page 3-14 What Are Your HDL Requirements? on page 3-19 Setting the Target Language on page 3-25 Setting the Names and Location for Generated HDL Files on page 3-26 Customizing Reset Specifications on page 3-33 Customizing the HDL Code on page 3-37 Capturing Code Generation Settings to a Script on page 3-85 Generating Code for Multirate Filters on page 3-86 Generating Code for Cascade Filters on page 3-93 Generating Code for Polyphase Sample Rate Converters on page 3-97 Generating Code for Multirate Farrow Sample Rate Converters on page3-101

Generating Code for Single-Rate Farrow Filters on page 3-105 Customizing the Test Bench on page 3-112 Generating the HDL Code on page 3-142 Generating Scripts for EDA Tools on page 3-143

3 Generating HDL Code for a Filter Design

Overview of Generating HDL Code for a Filter DesignConsider the following process as you prepare to use the Generate HDL dialogbox to generate VHDL code for your quantized filter:

1 Open the Generate HDL dialog box.

2 Review what the coder generates by default.

3 Assess whether the default settings meet your application requirements. Ifthey do, skip to step 6.

4 Review the customization checklist available in What Are Your HDLRequirements? on page 3-19 and identify required customizations.

5 Modify the Generate HDL dialog box options to address your applicationrequirements, as described in the sections beginning with Setting theTarget Language on page 3-25.

6 Generate the filters HDL code and test bench.

3-2

Overview of Generating HDL Code for a Filter Design

The following figure shows the steps in a flow diagram.

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%

&

"#$'

%

3-3


Opening the Generate HDL Dialog Box

In this section...

Opening the Generate HDL Dialog Box from FDATool on page 3-4Opening the Generate HDL Dialog Box from the filterbuilder GUI onpage 3-9Opening the Generate HDL Dialog Box Using the fdhdltool Commandon page 3-11

Opening the Generate HDL Dialog Box from FDAToolTo open the initial Generate HDL dialog box from FDATool, do the following:

1 Enter the fdatool command at the MATLAB command prompt. TheFDATool displays its initial dialog box.

3-4


2 If the filter design is quantized, skip to step 3. Otherwise, quantize the

filter by clicking the Set Quantization Parameters button . TheFilter arithmetic menu appears in the bottom half of the dialog box.

3-5


Note All supported filter structures allow fixed-point and floating-point(double) realizations.

3 If necessary, adjust the setting of the Filter arithmetic option. TheFDATool displays the first of three tabbed panes of its dialog.

3-6


4 Select Targets > Generate HDL. The FDATool displays the GenerateHDL dialog box.

3-7


If the coder does not support the structure of the current filter in theFDATool, an error message appears. For example, if the current filter is aquantized, lattice-coupled, allpass filter, the following message appears.

3-8


Opening the Generate HDL Dialog Box from thefilterbuilder GUIIf you are not familiar with the filterbuilder GUI, see Designing a Filterin the Filterbuilder GUI in the Filter Design Toolbox documentation.

To open the initial Generate HDL dialog box from the filterbuilder GUI,do the following:

1 At the MATLAB command prompt, type a filterbuilder commandappropriate to the filter response or filter object you want to design.

The following figure shows the default settings of the main pane of thefilterbuilder Lowpass Filter Design dialog box.

3-9


2 Set the filter design parameters as required.

3 Click the Code Generation tab. This activates the Code Generationpane, shown in the following figure.

4 In the Code Generation pane, click the Generate HDL button. Thisopens the Generate HDL dialog box, passing in the current filter objectfrom filterbuilder.

3-10


5 Set the desired code generation and test bench options and generate code inthe Generate HDL dialog box.

Opening the Generate HDL Dialog Box Using thefdhdltool CommandYou can use the fdhdltool command to open the Generate HDL dialog boxdirectly from the MATLAB command line. The syntax is:

fdhdltool(Hd)

3-11


where Hd is any type of filter object that is supported for HDL code generation.

The fdhdltool function is particularly useful when you need to use the FilterDesign HDL Coder GUI to generate HDL code for filter structures that arenot supported by FDATool or filterbuilder. For example, the followingcommands create a Farrow linear fractional delay filter object Hd, which ispassed in to the fdhdltool function:

D = .3;farrowfilt = dfilt.farrowlinearfd(D);farrowfilt.arithmetic = 'fi

Documents

Filter Design HDL Coder User's Guide.pdf