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Fingers : Advantages of fingering: Fingers reduces the resistance of the gate and parasitic capacitance of drain/source. Reducing the gate resistance will reduce the noise due to it, which dominate at higher frequency. Minimises the LOD effect. More useful in layout to realise for matching purpose. LOD effect: This effect is due to the stress caused by the Shallow trench isolation which affects the device Vt, Idsat, matching of the device and large error In the current mirror. As the distance from the edge of the poly gate to the boundary of diffusion area (SA, SB, SD)varies, so do the properties of the transistor. Let's say you have ten transistors on one stretch of diffusion. The transistors at the centre of the diffusion strip and the transistors at the sides have different properties e.g. vth may vary by 20mV. This in turn translates to offset and some other circuit imperfections. To avoid LOD effect, it is better to have multipliers instead of fingers, as the stress due to STI will be same for all the devices. Well proximity effect: CMOS technologies make use of high energy implants to form deep retrograde well profiles needed for latch up protection and supression of lateral punch through. During this implant process,

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Fingers :Advantages of fingering:

Fingers reduces the resistance of the gate and parasitic capacitance of drain/source. Reducing the gate resistance will reduce the noise due to it, which dominate at higher

frequency. Minimises the LOD effect. More useful in layout to realise for matching purpose.

LOD effect:

This effect is due to the stress caused by the Shallow trench isolation which affects the device Vt, Idsat, matching of the device and large error In the current mirror.

As the distance from the edge of the poly gate to the boundary of diffusion area (SA, SB, SD)varies, so do the properties of the transistor. Let's say you have ten transistors on one stretch of diffusion. The transistors at the centre of the diffusion strip and the transistors at the sides have different properties e.g. vth may vary by 20mV. This in turn translates to offset and some other circuit imperfections.

To avoid LOD effect, it is better to have multipliers instead of fingers, as the stress due to STI will be same for all the devices.

Well proximity effect:

CMOS technologies make use of high energy implants to form deep retrograde well profiles needed for latch up protection and supression of lateral punch through. During this implant process, atoms get scattered laterally and become embedded in the silicon surface in the vicinity of nwell edge.

This reults in the well surface concentratiob that changes with lateral distance from the mask edge over the range of 1um or more.

This lateral non uniformity causes the MOSFET Vt and oher electrical charateristics to vary with the distance of the transistor ito the well edge. This phenomenon is called well proximity effect.

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