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ASML’s customer magazine
First EUV test chips produced
How will you do 32?
The immersion pool becomes an ocean
2008
Spring E
dition
2
images | Colofon
Editorial Board
Don Crabtree, Peter Jenkins, Craig DeYoung
Publisher
Ryan Young
Managing Editor
Guus van der Meulen
Contributing Writers
Peter ten Berge, Martin van den Brink,
Stuart Cherry, Paul Derks, Jos Maas,
Frank van de Mast, Hans Meiling, Skip Miller,
Robert O’Neill, Christian Wagner
Circulation
Emily Leung, Michael Pullen, Guus van der Meulen
For more information, please see:
www.asml.com/images
© 2008, ASML Holding BV
ASML, ASM Lithography, TWINSCAN, PAS 5500,
PAS 5000, SA 5200, ATHENA, QUASAR, IRIS, ILIAS,
FOCAL, Micralign, Micrascan, 3DAlign, 2DStitching,
3DMetrology, Brion Technologies, LithoServer,
LithoGuide, Scattering Bars, LithoCruiser, Tachyon
2.0, Tachyon RDI, Tachyon LMC, Tachyon OPC+,
LithoCool, AGILE, ImageTuner, EFESE, Feature Scan,
T-ReCS and the ASML logo are trademarks of ASML
Holding N.V. or of affiliate companies. The trademarks
may be used either alone or in combination with
a further product designation. Starlith, AERIAL,
and AERIAL II are trademarks of Carl Zeiss. TEL is
a trademark of Tokyo Electron Limited. Sun, Sun
Microsystems, the Sun Logo, iForce, Solaris, and the
Java logo are trademarks or registered trademarks of
Sun Microsystems, Inc. in the United States and other
countries. Bayon is a trademark of Kureha Chemical
Industry Co. Ltd. Nothing in this publication is intended
to make representations with regard to whether any
trademark is registered or to suggest that any sign
other than those mentioned should not be considered
to be a trademark of ASML or of any third party.
ASML lithography systems are Class 1 laser products.
8 12 163 Editor’s note
4 ASML in the News
6 A better way to increase
your profitability
8 First EUV test chips produced
10 Lithography goes holistic
12 How will you do 32?
16 PAS 5500/8TFH-A:
the 700 Gbpsi system
18 The immersion pool becomes
an ocean
20 An introduction to
photolithography - Productivity
3
ASML Images, Spring Edition 2008
Editor’s note
Do you know all the ingredients of
Coca Cola? Neither do I. The recipe is
one of the best kept trade secrets in
the world and only a very few people at
Coca Cola know it. It’s a complicated
formula of flavors – including sugar,
vanilla, lime, caffeine and others. Leave
out one ingredient or get the quantities
slightly wrong and, well, it just isn’t Coke
anymore. It doesn’t taste as good and it
doesn’t have the quality people demand.
So now, you’re probably asking
yourself what Coke has to do with
photolithography.
Well, like the Coca Cola recipe,
photolithography is a complicated
process where a large number of
ingredients come together. And each
one must be just right to create a
successful end product. For lithography,
those ingredients include things like the
light source, the lens, temperature and
humidity control, reticle enhancement,
metrology and many others.
However, unlike Coca Cola,
photolithography needs to evolve
and continually improve. If the industry
is to maintain Moore’s Law, we need
new techniques and new ingredients.
One technique that is currently attracting
a lot of attention as the industry starts
looking towards 32-nm production is
double patterning.
Double patterning actually refers to
a number of different techniques.
Each has its pros and cons, so IC
manufacturers need to look carefully
at their product range and business
goals before deciding which one (or ones)
to adopt. One thing they have in common
is the increased demands they put on
lithography. ASML is answering those
demands, in part, through a roadmap
of system enhancements for our
cutting-edge immersion scanners.
But the challenges of double patterning
and other ultra-low k1 techniques are
driving a more fundamental change in
the lithography recipe. The individual
ingredients of IC manufacturing (design,
mask creation, lithography and metrology)
will have increasing impact on each other.
It will no longer be enough to consider
each ingredient in isolation. Instead,
they will need to be blended into
one integrated approach we call
‘Holistic Lithography’.
That recipe was introduced by
Martin van den Brink, our Executive Vice
President Technology and Marketing,
at the recent SPIE conference. And it will
be increasingly important to the success
of the semiconductor industry as feature
sizes shrink past 32-nm to 22-nm and
beyond. You can find out more about
it inside.
If you have any comments or
suggestions on this, or any other
aspect of Images, please contact me
Happy reading
Guus
Improving the recipe, continuing the success By Guus van der Meulen, Marketing Communications Manager
4
ASMLin the News
TOKYO, SEMICON Japan 2007,
December 05, 2007 – ASML Holding NV
(ASML) today announces rapid industry
adoption of the TWINSCAN™ XT:1900i,
which began shipping in July 2007.
The XT:1900i enables volume production
of logic devices down to 32-nanometers
(nm) and memory devices at 40-nm.
Chipmakers need to produce ever smaller
and denser integrated circuits to improve
the functionality of their chip designs to
power today’s computing and consumer
electronics products.
Early Success of the TWINSCAN XT:1900i Scanner Reinforces ASML’s Immersion Leadership Around the World
ASML’s Martin van den Brink and Mircea Dusa honored at SPIE 2008 06 March 2008 – At the annual SPIE Advanced Lithography symposium,
which took place 24 – 29 February 2008 in San Jose, California, the organizing
committee traditionally honors scientific and technical contributors to the lithography
field with SPIE Fellowships and the prestigious Frits Zernike Award for Microlithography.
This year, some of ASML’s own were honored. Mircea Dusa, senior scientist at
the Technology Development Center, was awarded a SPIE Fellowship, while
Martin van den Brink, Executive Vice President Marketing and Technology,
received the 2008 Frits Zernike Award.
4
Fastest filing again shows ASML’s financial leadership01 February 2008 – On Friday, January 25,
ASML once again was the fastest company
in the world to file its annual report (on Form
20-F) with the U.S. Securities and Exchange
Commission (SEC). This shows the effect
of ASML’s clear, transparent and efficient
financial processes.
5
ASML Images, Spring Edition 2008
For complete information regarding these press announcements, please refer to the press section of www.asml.com.
Strong Q4 Leads ASML to Record 2007 Full Year Earnings; Technology Leadership to Provide Robust H1 Sales and Profit Amid Market Uncertainty“Even though the global semiconductor industry was under pressure in 2007,
we confirmed the robustness of the company’s market position and managed to
close the year with record sales and net income,” said Eric Meurice, president and
CEO of ASML. “Unit demand for our systems remained stable in 2007 and in the fourth
quarter. At the same time, the value of our systems increased as a result of product
improvements throughout our portfolio and the need of our customers for leading
edge technology, specifically immersion. Worldwide, customers have now processed
over 8 million wafers on ASML immersion machines, enabling a new wave of more
powerful chips and exciting electronic applications. This strong year has allowed us
to start expanding our production facilities and boost our research and development
investments worldwide. (Extract from the press release 16 January 2008)
Water is the focus at SEMICON JapanSEMICON hosts the world’s largest
semiconductor equipment events, held
at various locations throughout the year.
The first week of December 2007 was the
turn of SEMICON Japan, and the ASML
roadshow was there with its theme of
“Focus on Water.”
ASML, Zeiss and Canon Cross-license Lithography Equipment Patent Portfolios VELDHOVEN, the Netherlands/OBERKOCHEN, Germany, December 21, 2007
– ASML Holding NV (ASML) and Carl Zeiss SMT (Zeiss) today announce that each has
signed an agreement with Canon Inc. (Canon) for the global cross-license of patents in
their respective fields of semiconductor lithography and optical components, used to
manufacture integrated circuits, or chips.
To support the “Focus on Water” campaign, more
than 25,000 specially designed ASML water
bottles were distributed at the booth and the train
station leading to the convention center.
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DRAM WW ASP
FLASH ASP
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6
Abstract | ASML has launched a range
of customized Output Improvement
Service products to help IC manufacturers
increase the profitability of their fabs.
By analyzing and optimizing fab operation,
these programs help boost output value
by enhancing the productivity, overlay or
imaging performance of the manufacturer’s
existing litho cell equipment.
The Customized Productivity Improvement
(CPI) program is already up and running,
and has played a key role in enabling recent
productivity world records.
A better way to increase your profitabilityBy Jos Maas, Marketing Director Customer Support
Price pressure. It’s everywhere in the
semiconductor industry. Just take a look at
the way memory prices have fallen over the
years. This erosion of end product prices is
leading to huge pressure within organizations
to cut costs in order to maintain profitability.
However, there is another way to make your
bottom line healthier – maximize your output
value. In fact, this is a much more effective
way of increasing profits. After all, increasing
your output value by just 1% can boost your
overall profitability by much more than let’s
say a 10% OpEx cost reduction. What’s
more, the output improvements can often be
achieved more quickly and less painfully.
Output value can be improved by enhancing
productivity, overlay or imaging performance.
Obviously, buying new equipment or system
enhancements help your fab improve in all
these areas, but there are often gains to be
made by optimizing your operations.
Of course, this is easier said than done, and
a typical fab will already have invested huge
numbers of man-hours on it.
Our expertise at your service
ASML offers a range of Output Improvement
Service products to help you squeeze out
those few more good wafers per day that
will put you ahead of your competitors.
Each Service focuses on one of the key
output areas (productivity, overlay or
imaging). Our experts in that area come into
your fab to analyze how you use your ASML
systems in the context of your whole process
line and help you get the most from your
existing litho cell equipment.
In doing so, they draw on our vast
experience working with real processes
in real fabs and our unique knowledge of
our systems – after all, who knows more
Memory Average Selling Price (ASP) trend over last years. Source WSTS.
Increasing your output
value by 1% can boost
your overall profitability
by much more than
a 10% cost reduction
7
ASML Images, Spring Edition 2008
about getting the most from a tool than the
people who designed and built it.
Boosting productivity
The first of these products is the Customized
Productivity Improvement (CPI) program.
This two-stage process aims to improve
the Overall Equipment Effectiveness (OEE)
of your ASML tools and your entire litho area.
In phase 1, our experts review your litho
area performance, benchmarking it against
productivity targets for the specific tools you
have. In phase 2, we identify and quantify
existing bottlenecks and recommend ways
to minimize or eliminate them.
Following the review, the fab manager
receives a detailed report outlining our
recommended improvements for track,
scanner and operational efficiencies.
The recommendations are grouped
according to the effort they require
(low, medium or high), and each one is
accompanied by a predicted productivity
gain. The report also includes an
implementation plan showing the best
order for carrying out the recommendations.
Of course, the decision on implementing the
recommendations stays with you. But ASML
can provide support on any actions you
choose to implement.
The productivity improvement experts at work
It enabled individual
TWINSCAN systems to
process over 1 million
wafers in a year.
Excellent results
The CPI program is a well-established
service product, built on our extensive
experience helping customers around the
world improve their productivity.
Over the last few years, we’ve carried out
more than 25 such projects. In fact, the CPI
program has enabled individual TWINSCAN
systems to process more than 1 million
wafers in a single year.
On average, the “low implementation
effort” recommendations have improved
productivity by an impressive 10%.
Meanwhile, implementing all our
recommendations could have boosted
output by over 30%. To put that into context,
for an average-sized memory fab, increasing
output by just a few percent can generate
tens of millions of dollars in extra revenue
and improve operating margins.
8
First EUV test chips produced By Christian Wagner and Hans Meiling, Senior Product Managers EUV
EUV lithography took a big step forward
towards production in February this year
when the Albany Alliance announced
the world’s first working full-field EUV
test chips. Located at the University
of Albany’s NanoTech Institute (CNSE),
the Alliance used EUV lithography for
the critical first layer of metal connections
across an entire 22 mm x 33 mm chip.
The EUV processing was carried out
on an ASML EUV alpha demo tool
(ADT). ASML shipped two ADTs in
2006: one to CNSE and one to IMEC
in Belgium. And over recent months
these two leading next-generation
nanoelectronics research centers
have been collaborating on a number
of experiments to accelerate the
introduction of EUV into manufacturing.
Building a solid platform
The ADTs are full-field EUV step-and-scan
systems designed to help R&D institutes
and semiconductor manufacturers start
The Albany Alliance
announced the world’s
first working full-field
EUV test chips
investigations into commercializing EUV
lithography. With an NA of 0.25, they
lay the foundation for our EUV roadmap
which is built around our modular platform
philosophy of system development.
Our platform philosophy aims to keep
as much as possible of the ‘fundamental’
system the same between generations,
only changing ‘node-specific’ modules
like the optics. ASML has invested a great
deal of time and effort in developing an
EUV platform. This enables consistent
advances in robustness while following
the shrink roadmap to beyond 10 nm in
an effective manner through individual
system generations.
In addition, we are seeing the benefits
of choosing an extendible optical
concept. The ‘six mirror’ design principle
used in the ADTs can reach 0.32 NA.
This is high enough for production at
22-nm, and could be combined with
off-axis illumination for resolutions down
to 16 nm. Beyond that, a similar optical
concept using 8 mirrors could take EUV
below 10 nm.
Tin sources get ready to shine
Of course, there is still work to do
regarding EUV light sources. Our ADTs
are fitted with discharge-produced-
plasma (DPP) tin sources, so customers
can gain early experience in designing
8
Abstract | In February 2008, the world’s
first full-field EUV test chips were exposed
on ASML alpha demo tools. In parallel with
these breakthroughs, ASML is developing
an EUV system platform and roadmap to
bring EUV lithography into full production
at the 22-nm node.
Res 2010 2011 2012 2013 2014 2015
11nm
16nm
22nm
27nm
0.4xNA
0.32NA + off axis illumination
0.32NA, 3nm OVL, >100wph
0.25NA, 4nm OVL
implementation volume production
EUVL Roadmap down to 11nm, support 22nm and 16 nm node with a single lens
10mJ/cm2
60wph
10mJ/cm2
100wph
0
100
200
300
400
7H1 7H2 8H1 8H2 9H1 9H2 10H1 10H2 11H1 11H2 12H1
Po
wer
at
IF (W
)
Supplier ASupplier BSupplier C
Source deliveries on critical path for TPT roadmapWafer processed on the ASML EUV AD-tool
9
ASML Images, Spring Edition 2008
and optimizing the tin-based sources
that are the most likely candidate for final
production systems.
However, today’s sources can’t yet
deliver the in-band EUV power required
for volume production. The delivery
of suitable sources is on the critical
path for EUV development, and we
have developed a roadmap for laser-
produced-plasma (LPP) source concepts
that will allow EUV to enter production
on time.
Along with source power, resist dose
sensitivity is also a key element in
delivering high productivity. Data
presented at SPIE Advanced Lithography
2008 showed 22-nm dense line resolution
at a 10 mJ/cm2 resist dose. At this resist
dose, a source with around 200 W of
EUV power would enable a production
throughput of 100 wafers per hour.
On track for 22 nm
Looking back to the introduction of
immersion, it took around two years from
the delivery of pre-production tools to the
start of production. And we’re aiming to
follow a similar cycle for EUV.
Based on our platform roadmap,
NA = 0.25 EUV system will be operating
at customer sites in 2010. To date, five
customers have placed orders for this
system, including multiple non-memory
customers. The pre-production tool
will be followed by 0.32 NA volume
production systems in the second
half of 2011, enabling EUV production
to come online in 2011 / 2012.
Depending on the actual shrink route
taken, that timeline puts EUV on
schedule for the 22-nm node.
10
Abstract | The move to the 32-nm node
and beyond presents unique challenges
for the semiconductor industry. Ultra-low
k1 production techniques mean it will no
longer be enough to consider IC design,
mask creation, lithography and metrology
in isolation. Instead we will need a new,
complete and tightly integrated approach
to IC manufacture. We look at the steps
needed to make this so-called ‘holistic’
approach a reality.
Lithography goes holisticBy Martin van den Brink, Executive Vice President Technology and Marketing
We all know feature shrink is essential
for continuing the cost reductions and
performance improvements the industry
needs to keep moving forward. And each
step, brings new challenges.
Looking at the 32-nm node and beyond,
there are challenges around the design of
transistors. These include obstacles such
as power-density and the single-electron
problem. Through extensive effort across
the industry, we have a number of ways
to tackle these design issues – in theory,
at least.
Once the transistors are designed,
we then face the challenge of how to
make them: known as the lithography
scaling issue. Thanks to immersion, ArF
lithography has reached as far as 40-nm
production. And ultra-low k1 techniques
such as double patterning (see page 12)
will extend its use to the 32-nm node.
However, implementing these techniques
brings its own challenges, and will require
much more accurate lithography with
significantly tighter overlay and CDU
performance. This is particularly true
for double patterning. Answering this
challenge will take a new approach to
manufacturing that blends IC design,
mask creation, lithography and metrology
into one comprehensive and tightly
integrated process. We call this
‘holistic’ manufacturing.
Holistic manufacturing
Why do we need a holistic approach?
Because low k1 lithography techniques
tie all aspects of IC together much more
closely than ever before. It is no longer
possible to carry out these activities in
isolation. Each one feeds into the others.
Lithography systems must have the
technical specifications to print new
low k1 designs, but the characteristics
of the lithography system will constrain
the design rules that can be used.
Masks need to be optimized for the
source used, while the system will need
tuning for the specific application and
mask. Finally, designs will need to be
created to take full advantage of the
possibilities for creating and optimizing
Figure 1: ‘Low k1: High Design to Wafer Integration
Low k1: High design to wafer integrationLow k1 (<0.4): Integration of design, mask and lithography processes
Design For Manufacturing
DFM
Application Specific
Manufacturing
Design space Manufacturing space
Litho aware design constraints
OPC & R
ETs: P
SM, DPT,
Scatte
rbars
, DDL v
erific
ation
Application specific tuning
Source-Mask
Optimization
11
ASML Images, Spring Edition 2008
masks. And in the case of double
patterning, that means producing
designs that can be easily split
between multiple masks. (See Fig. 1)
This will require more integration
between lithography development,
scanner optimization and computational
lithography. However, before holistic
manufacturing becomes a real possibility,
developments are needed in a number
of areas.
Expanding computational lithography
Traditionally, computational lithography
tools have targeted the optical proximity
correction (OPC) and verification markets.
However, low k1 production demands
significantly more computational power,
and the use of computational lithography
has grown to include lithography
optimization capabilities such as single
machine overlay, CDU and application-
specific scanner tuning.
Returning to our example of double
patterning, ASML estimates it will require
3.5 times more raw computational power
than for single exposure production.
Sophisticated software is needed to split
a single chip design into two separate
mask patterns that must then be precisely
overlaid and recombined on the wafer.
This software has to ‘know’ which gates
and connections on the chip have the
most relaxed overlay requirements so
it can take maximum advantage of the
tolerances of the lithography system.
Computational lithography software
is also needed to adjust the split masks
and optimize the stitching of the patterns
back together on the wafer. Moving
forward, improvements in source-mask
optimization software are needed to
better handle differentiated design
Holistic: looking at complete
systems as a whole rather
than individual parts in
isolation
elements such as combined logic and
SRAM. Meanwhile, the introduction of
unconstrained source-mask optimization
could substantially improve depth of
focus and, therefore, overall productivity.
Measuring up
Controlling the fine tuning of lithography
systems will require more and better
metrology data. Consequently, angle-
resolved scatterometry (ARS) will
increasingly replace spectroscopic
scatterometry. As it uses more of the
available light, ARS can deliver faster,
more accurate metrology, enabling higher
productivity and the quicker feedback
loops required for application-specific
scanner tuning. Moreover, lab tests using
ARS in a 32-nm lithography patterning
process have shown that CDU for lines
can be trimmed to less than 4 nm and
even below 3 nm in some cases.
(See Fig. 2)
Making things happen
Clearly, investment is still needed to
make this holistic approach a reality
and bring double patterning into full
production. However, progress is being
made all the time.
For example, ASML subsidiary
Brion Technologies recently announced
a dedicated double patterning solution
for its Tachyon Computational
Lithography platform, Tachyon DPT
offers full-chip conflict-free pattern
split, model-based OPC, model-based
stitching compensation and automatic
density balancing. Keep an eye on
upcoming issues of images for
further developments.
High precision and productive metrology: angle-resolved scatterometry vs spectroscopic
Multi wavelength 2D vs 1D pupil detection for angle-resolved scatterometry for more process robust metrology
I( )
30x more photons for angle-based
scatterometry for more
productivity
Spectrometer grating
Beam splitter
1D CCD
light source
wafer
Pupil stop
light source
wafer
Interference filter
2D CCD camera
Beam splitter
Angle-resolved scatterometry Spectroscopic scatterometry
I( 1)
I( 2)
Figure 2: ARS diagram
1212
13
ASML Images, Spring Edition 2008
Production at 32-nm half-pitch will
involve some form of double patterning
How will you do 32? By Frank van de Mast, Senior Product Manager, and Skip Miller, Director Strategic Marketing
Abstract | Double patterning is widely
seen as the technology required for
32 nm memory and 22 nm logic production.
However, there are 3 competing techniques
that come under the double patterning
banner. Here we take a look at the
different options, their strengths and
their weaknesses.
It doesn’t matter which sector of the
semiconductor industry you’re in, the drive
for smaller features never slows down.
The next step will take the minimum half
pitch towards 32 nm. Many manufacturers
have already started process development
for these nodes or are planning to over
the coming year.
The commonly accepted technology
to deliver these nodes is double patterning.
However, double patterning actually
describes a number of techniques, each
with its own benefits and weaknesses.
So which will be the ‘best’ one for you?
Three faces of double patterning
There are two main categories of double
patterning techniques commonly called
13
ASML Images, Spring Edition 2007
lithography and spacer double patterning.
Lithography double patterning is often
further split into two techniques known
as intermediate pattern accumulation
or litho-etch-litho-etch (LELE) and
heterogeneous mask or litho-freeze-
litho-etch (LFLE).
Both lithography double patterning
techniques involve splitting the dense
design pattern (k1 < 0.25) into two less
dense mask patterns (k1 > 0.25) which
are then interleaved on the wafer in
separate exposure steps. The difference
between the two approaches is what
happens to the wafer between exposures.
In LELE, the wafer leaves the litho-cell
to have the first pattern etched. In LFLE,
14
Table 1: Lithography requirements for different technology options
* depending on cd control of the sacrifical line
Litho exposure Equipment parameter as percentage of CD
Single exposure
Litho double patterning
Spacer double patterning
CD 7% 3,5% 3%
Overlay (depending on DFM)
20% 7% 7-20%*
# mask steps 1 2 2-3
# process steps relative to single exposure
1 2 3-4
Application 2D, All 2D, All 1D, Mainly Memory
Dual line(litho-etch-litho etch)
first imagek1 > 0.25
second imagek1 > 0.25
final imagek1 > 0.25
Litho 1Standard resist
Litho 2Coat, expose, developed 2nd pattern
“Freeze” process first developed image:1) Coat first developed (shown)2) Thermal treatment3) Pos/Neg resist
Spacer (litho-etch-deposit-etch back trim)
sacrificial image:k1 > 0.25
final imagek1 > 0.25
the wafer stays in the litho-cell and the
pattern is transferred to an underlying
hardmask (frozen) to be etched onto
the wafer after the second exposure.
(See Fig. 1 and 2)
By contrast, spacer double patterning
is a self-aligning process. A first mask
pattern is exposed and etched into a
sacrificial layer. A spacer material is then
deposited onto this pattern. The excess
spacer material and then the sacrificial
pattern are etched away leaving behind
two spacer features for each line originally
printed. These features are then trimmed
using a second (non-critical) exposure
step and etched into the wafer giving a
final pattern twice as dense as the optical
pattern exposed. A third patterning layer
is often required to expose the periphery
circuit area. (See Fig. 3)
Strengths and weaknesses
As Table 1 shows, spacer double
patterning has less stringent overlay
requirements than lithography double
patterning but more challenging CD
control requirements. With the less
critical overlay requirements, spacer
processes are already being developed
with current lithography systems. In fact,
the TWINSCAN XT:1900Gi ArF immersion
scanner is being used for 32 nm process
development today.
Spacer is best suited to those applications
with regular and unidirectional patterns,
such as NAND Flash. For the more irregular
Figure 1: LELE double patterning Figure 2: LFLE double patterning Figure 3: Spacer double patterning
15
ASML Images, Spring Edition 2008
patterns typical in other IC applications,
spacer process integration becomes much
harder. In contrast, lithography double
patterning is more widely applicable as
it can be more easily applied to irregular
patterns, and is therefore more critical for
IC applications. (See Table 1)
And then there is the question of cost.
All double patterning techniques require
at least two exposure steps and have more
complicated process stacks. Therefore,
layer costs will be higher than for the
single exposure technologies used to
date. Of the three, spacer has the most
complicated process and so would be the
most expensive option. LFLE, where the
wafer doesn’t leave the litho-cell between
exposures, is the simplest and therefore
least expensive double patterning option.
The additional costs from multiple
exposures and process steps plus the
challenges of working at low k1 values are
key reasons why the industry is pushing for
EUV. EUV not only allows manufacturers
to get back to single-exposure techniques
and higher k1 values, it also offers greater
extendibility. (See Fig. 4 and 5)
The right choice
While it is inevitable that production
at 32-nm half pitch will involve some form
of double patterning, the ‘best choice’ will
depend strongly on your business model.
Flash memory makers will need 32 nm
earliest to meet their aggressive shrink
roadmaps. They may consider using
spacer double patterning and hope
to recoup the higher costs by being
first to market with the next generation
of products. To minimize costs, they
will probably also continue to investigate
the alternatives.
For other applications, where spacer
is difficult to implement, lithography
double patterning seems to be a more
attractive option offering a balance
between time-to-market and layer costs.
At the moment, the freeze step needed
for LFLE double patterning does not give
sufficient process control to meet imaging
requirements, making LELE the current
front runner. However, if the freeze process
can be improved to meet requirements,
LFLE’s lower costs could make it the most
popular choice.
In practice, most manufacturers will
probably need to adopt some mix of the
various techniques with some lines running
spacer and others running lithography
double patterning. Determining the exact
composition of that mix will require a
detailed analysis of the company’s product
range and business goals.
Reticle cost based on 5000 wafers / mask usage
Fixed Operating Source Chemical CVD
Metrology Etch Clean Reticle
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Figure 5: Lithography cost per layer estimates for 32 nm
No
rmal
ized
lith
o c
ost
per
laye
r
45 nm ArFi 32 nm 193 nm Spacer DPT
32 nm 193 nm Litho DPT
Figure 4: Options to print below immersion single exposure limit
Single exposure
Liho double patterning Spacer DPTMetrology
LFLE LELEWafer not leaving the litho cluster
CleanStrip
Film EtchStrip HM #2MetrologyOzide Etch
Metrology Ozide DepClean Org Etch
HM #2Strip Metrology
Metrology Film Etch DevelopClean Clean Expose-ArFStrip Strip Resist
Film Etch SiON / HM Etch
BARC
Clean Metrology Org Etch HM #1
Strip Develop MetrologySiON / HM
EtchExpose Poly Wet Strip
Metrology Top Coat Ozide EtchDevelop Resist Ozide Dep
Metrology Expose BARC MetrologyClean Top Coat Clean CleanStrip Resist Strip Strip
Film Etch Metrology SiON / HM Etch
Poly Etch
Metrology Freeze Step Metrology Metrology
Develop Develop Develop DevelopExpose Expose Expose Expose-ArF
Top Coat Top Coat Top Coat ResistResist Resist Resist BARCBARC BARC BARC Ploy Dep
SiON / SiC SiON / SiC SiON / SiC SiON / SiCHard Mask Hard Mask Hard Mask Hard MaskDevice Film Device Film Device Film Device Film
Si Si Si Si
ArFi SE45nm / 32nm
ArFi PF32nm / 28nm
ArFi DPT32nm / 22nm
SPCR 32 / 22nm
Figure 5: Lithography cost per layer
estimates for 32 nm
Co
st, c
om
ple
xity
an
d c
ycle
tim
e
16
Abstract | A tried-and-trusted partner in
thin-film-head (TFH) production, ASML is
releasing the new PAS 5500/8TFH-A later
this year. This advanced KrF lithography
stepper is dedicated to TFH production and
draws on ASML’s extensive experience in
AlTiC wafer handling. It will enable hard disk
manufacturers to achieve areal densities up
to 700 Gbpsi, keeping them at the forefront
of the high-capacity storage market and
enabling laptops that feature 2.5-inch hard
drives with up to 1Tbytes capacity.
In the world of high-capacity storage,
areal density is the key to success.
Hard-disk drives (HDDs) have higher
areal densities than solid-state rivals,
so they still dominate the market.
But with Flash drives redefining the
boundary between high- and low-
capacity, HDD manufacturers need to
push areal density further. Supporting
this trend, ASML is launching the PAS
5500/8TFH-A: a dedicated thin film head
(TFH) KrF lithography system enabling
areal densities up to 700 Gigabits per
square inch (Gbpsi).
Areal density is the amount of information
that can be stored in a given area. It is
governed by two parameters: the bit
length and the track pitch. Reader head
improvements have pushed bit length
about as small as it can go. So further
areal density advances based on the
head design depend almost entirely
on reducing the track pitch, which in turn
depends on improved lithography. This is
sometimes referred to as “areal density
hyperscaling”. (See Fig. 1)
Unique machines for unique challenges
TFH production presents a unique set
of lithography challenges. For example,
the alumina-titanium-carbide (AlTiC)
wafers used are much thicker and more
sensitive to thermal fluctuations than
silicon wafers. In addition, back-end
processing requirements mean TFH dies
must be very accurately aligned across
multiple exposure fields (co-linearity).
The new PAS 5500/8TFH-A is designed
specifically to meet these challenges.
And in creating it, ASML has drawn on
over 10 years’ experience developing
dedicated TFH machines handling
millions of AlTiC wafers.
TFH production requires longer wafer
processing on the resist coating track
than for ICs. Consequently, TFH wafer
throughput requirements for the exposure
tool are relatively much lower. The PAS
5500/8TFH-A exploits the extra time
available for wafer exposures to deliver
overlay performance far in advance
of that available to silicon-processing
KrF systems.
For example, it includes a unique
active and passive accommodation
system to maximize the thermal stability
of the tool and wafer, and dynamic
wafer measurement to determine any
remaining thermal effects. Together with
several hardware improvements, these
features enable single machine overlay
of 6 nm on AlTiC wafers under standard
TFH conditions (compared to the 10 nm
10 years’ experience
developing dedicated TFH
machines handling millions
of AlTiC wafers
PAS 5500/8TFH-A:
The 700 Gbpsi systemBy Peter ten Berge, Product Marketing Manager for TFH systems
17
ASML Images, Spring Edition 2008
achievable under ATP conditions on
a standard PAS 5500 ArF or KrF tool
with all overlay upgrades). (See Fig. 2)
The PAS 5500/8TFH-A also features an
ultra-low-aberration lens and illuminator
proven on our TWINSCAN KrF tools,
enabling a CD uniformity specification
better than 5 nm at best focus for 90 nm
isolated lines. Such high isolated-feature
imaging performance allows the use of
KrF lithography in TFH production to be
extended. This is particularly important
as KrF resist formulas seem better suited
to non-lithography TFH processes like
ion milling and etching than ArF resists.
Furthermore, the excellent imaging plus
a stage grid verification specification of
just 6 nm ensures world-class co-linearity
performance well within TFH back-end
processing requirements.
In addition, the optional CLEAR! wafer
table cleaner provides fully automated,
fast and highly effective spot removal
between batches. This improves long-
term tool stability, enabling potential
overlay improvements due to the long
time between critical layers. And as the
cleaning is automated, your system is up
and productive for longer.
Ready for the future
Scheduled for delivery in Q3 2008,
the PAS 5500/8TFH-A will initially
enable industry-leading areal densities
around 250-300 Gbpsi. However, its high
performance allows HDD manufacturers
0.0
25
50
75
100
125
150
tra
ck p
itch
[nm
]
0 500 1000 1500 2000
areal density [Gbpsi]
0
300
200
100
400
500
600
# o
f sam
ples
-5 -4 -3 -2 -1 0 1 2 3 4 5
Overlay [nm]
X (mean +3s)
Y (mean +3s)
Figure 1: Industry roadmap of track pitch vs. areal density
Figure 2: Typical overlay data on proto PAS 5500/8TFH-A tool (lot of 3 AlTiC wafers)
Specifications
Resolution ISO lines 90 nm
NA 0.55-0.80
CDU @ 90 nm ISO BF 5 nm
Single machine overlay 6 nm
Stage grid verification 6 nm
Throughput (6-inch wafers) 30 wph
to adopt an aggressive technology
roadmap that will keep them at the
forefront of the storage market. With the
industry’s expected adoption of discrete
track recording, the PAS 5500/8TFH-A
will allow you to deliver areal densities up
to 700 Gbpsi.
18
Abstract | Immersion lithography has well
and truly become a volume production
technology with over 10 million wafers
exposed on ASML immersion systems
alone. In the second half of 2007, ASML
shipped 20 TWINSCAN XT:1900i systems.
And it will soon be releasing upgrade
packages that push productivity and
performance even further.
In July 2007, ASML shipped the first
TWINSCAN XT:1900Gi. By the end
of 2007, we had shipped 20 of these
fifth-generation immersion lithography
systems to customers around the world.
This is the fastest advanced product
ramp up ASML has ever experienced!
It’s also clear proof that immersion
lithography has entered high-volume
production. The XT:1900Gi systems join
our extensive immersion installed base
which now comprises more than 70 tools.
As of April 2008, these systems had
exposed a total of 10 million wafers at
a global production rate of over 1 million
immersion wafers per month and rising.
(See Fig. 1)
Setting new standards
The TWINSCAN XT:1900Gi is an
NA=1.35 immersion ArF scanner.
Pushing water-based immersion to its
limits, it is the only currently available
system capable of resolving features
down to 36.5 nm. It also offers industry-
leading overlay of 6 nm (SMO) and
throughput of 131 wafers per hour
(under ATP conditions).
ASML is planning a series of system
enhancements that will push productivity,
overlay and defectivity performance even
further. Thanks to our modular system
architecture, these same upgrades will
also be made available for XT:1700i
systems (generally one quarter later).
The immersion pool becomes an oceanBy Hans Bakker, Product Manager TWINSCAN Advanced
19
ASML Images, Spring Edition 2008
Specifications
Standard XT:1900Gi
XT:1900Gi + TOP & PEP upgrades
Numerical aperture 0.85-1.35 0.85-1.35
Resolution 40 nm 40 nm
Dedicated chuck overlay - 4 nm
Single machine overlay 6 nm 5 nm
Matched machine overlay 10 nm 8 nm
Throughput (125 exposures, 30 mJ/cm2) 131 wph 140 wph
Clean and precise
The first of these upgrades, called
iClean, will be released in Q4 2008 for
the XT:1900i (Q4 for the XT:1700i).
iClean maintains system cleanliness by
adding a cleaning agent to the existing
auto-flush system in the immersion hood.
This makes inline cleaning much more
efficient, reducing cleaning time to around
an hour per week while providing the
same low contamination levels as current
megasonic cleaning. Consequently, iClean
increases your overall yield by reducing
the number of defects printed and
increasing system availability.
The next upgrade on our roadmap is
the TOP XT:1900Gi overlay enhancement
package, to be released in Q1 2009.
This upgrade features a new wafer table
providing better thermal control of the
wafer. It also brings improved TIS and
reticle alignment reproducibility and
other enhancements. The TOP XT:1900Gi
package boosts SMO performance from
6 to 5 nm, and enables a dedicated chuck
overlay of just 4 nm.
Individual production rates up to 2800 wafers per day
0
6
4
2
8
10
12
num
ber
of im
mer
sion
waf
ers
in m
illio
ns
Cumulative number of exposed wafers on ASML immersion equipment
Jan-
06Fe
b-06
Mar
-06
Apr
-06
May
-06
Jun-
06Ju
l-06
Aug
-06
Sep
-06
Oct
-06
Nov
-06
Dec
-06
Jan-
07Fe
b-07
Mar
-07
Apr
-07
May
-07
Jun-
07Ju
l-07
Aug
-07
Sep
-07
Oct
-07
Nov
-07
Dec
-07
Jan-
08Fe
b-08
Mar
-08
Figure 1: Graph
PEP it up!
Also scheduled for release in Q1 2009
is the PEP XT:1900Gi productivity
upgrade package which increases
ATP throughput to 140 wafers per hour.
The key feature of this upgrade is a new
immersion hood design that improves the
meniscus stability of the immersion pool.
This enables faster closing disc take over,
higher stage accelerations and faster
scan speeds.
Besides improving productivity,
the PEP package also reduces defect
levels. The higher meniscus stability
means less water escapes the immersion
pool. Meanwhile, large extraction holes
allow contaminants like particles and
resist-stack flakes to escape easily,
preventing contamination build up.
These features alleviate two major
causes of immersion defects.
In addition, ASML will be offering an inline
particle counter for systems fitted with the
new immersion hood. This allows early
detection of contamination incidents, and
can be used to trigger iClean (if installed).
Surging forward
The total and monthly numbers
of immersion wafers show that the
immersion pool that started in 2001 has
now become a full fledged manufacturing
ocean. Many of the shipped XT:1900Gi
systems are already being used in volume
manufacturing, particularly for NAND
Flash at the 5x and 4x nodes, delivering
individual production rates up to 2800
wafers per day. Our scheduled upgrades
on the roadmap for later this year will
enable manufacturers to boost production
levels even further and begin process
development for double patterning at
the 32-nm node.
20
Abstract | In the fourth and last of
our ‘Introduction to photolithography’
articles, we look at productivity or the
number of wafers a system can produce.
Lithography productivity governs the
output and profitability of the entire fab.
Higher lithography productivity means
manufacturers can produce more wafers
at lower cost.
An introduction to photolithography
Productivity By Paul Derks, Product Manager Productiv i ty for 300-mm fabs
20
21
ASML Images, Spring Edition 2008
21
In the previous articles of this series,
we looked at imaging and overlay – two
key lithography system characteristics
governing the quality and performance
of the final IC. The last key characteristic
of a lithography system is its productivity
– defined by the number of wafers it can
process in a given time. If imaging and
overlay provide the technology boosts
that keep the IC industry moving forward
on track, you can think of productivity as
the way to pay for those improvements.
For a wafer fab, profitability is directly
linked to productivity. Semiconductor
manufacturing is a very capital intensive
industry, and much of the investment
in a fab goes into the manufacturing
equipment. So fixed costs are high,
and equipment depreciation accounts
for a large part of the final wafer cost.
In fact, equipment depreciation amounts
to about half the lithography layer cost
for ArF and KrF, and over 70% for i-Line.
By spreading these fixed costs over
more wafers, higher productivity reduces
individual wafer cost and improves your
return on investment.
Higher productivity reduces individual wafer cost
and improves your ROI
To look at this another way, consider
the capital expenditure (capex): the
initial investment when building a new
fab. By using very high productivity
systems, you need fewer litho-cells
(lithography systems, tracks, etc) for
a given fab capacity. Hence the capex
is lower.
It’s worth noting that lithography
throughput governs the productivity
of the entire fab. As lithography systems
are the most expensive equipment in a
fab, fabs are designed so that lithography
is the bottleneck. This maximizes the
usage of lithography resources, and
means lithography output increases
translate directly into higher fab output.
System throughput
In a lithography system’s specifications,
the key productivity figure is its
throughput. This is the number of
wafers the tool can process in an
hour and is usually measured and
quoted under standardized conditions.
The actual throughput achieved in
production will depend on a number
of process or design variables beyond
22
World beaters
As a result of these efforts and the high
throughput of our systems, ASML systems
are regularly used to set wafer processing
world records. For example, in Q4 2007,
one of our customers processed a
massive 3689 wafers per day (wpd)
on an TWINSCAN XT:400F i-Line system.
That’s an average of almost 154 wph
(19 wph more than the spec for this type
of system) for 24 consecutive hours.
For KrF and ArF, other customers have
set records of 3603 wpd on an
TWINSCAN XT:850F and 3429 wpd on
an TWINSCAN XT:1400F respectively.
Moving to real “endurance” production,
the last edition of Images highlighted
the achievement of Korean memory
manufacturer Hynix who had processed
a staggering 1 million wafers in a year
on a single TWINSCAN XT:400E. We now
know of at least 41 i-Line, KrF and ArF
TWINSCAN systems that have joined
the “One Million Wafer Club”.
But it’s not just these world record holders
who benefit from ASML’s high productivity
systems. As Dan Hutcheson of VLSI
Research points out “Many manufacturers
have told us that, with ASML systems,
they need fewer tools to meet the
output targets.”
the lithography supplier’s control (such
as the field size and number of shots per
wafer), and so could be lower or higher
than the specification.
Different lithography suppliers often
use different standardized conditions
when measuring and quoting system
throughputs. For example, the specified
field size, dose and number of shots can
vary from one manufacturer to the next,
which means it is not always possible
to compare system specs directly.
ASML has always been a leader in system
throughput. Our systems feature the fastest
reticle and wafer stages in the industry, so
they spend less time moving things around
and more time exposing. They also offer
the latest in smart metrology technologies
to minimize lens idle time. Moreover, they
are built using a modular architecture
which means throughput improvement
features designed for new generations are
typically available as retro-fit upgrades for
previous generations in our installed base.
The ASML throughput advantage
was reinforced at the start of the new
millennium when, with the launch of the
TWINSCAN platform, we became the
first company to use a true dual-stage
lithography architecture. This architecture
allows our TWINSCAN systems to expose
one wafer while already performing the
necessary metrology measurements on
the next. As a result, our latest TWINSCAN
systems offer ATP throughputs up to 165
300-mm wafers per hour (wph) for dry
lithography1 and 131 wph for immersion2.
Sustained productivity
Lithography suppliers quote the
throughput of their tools because that
is something that can be measured at
their own facilities. However, lithography
customers are often more interested in
the production over a sustained period
such as a day, month or year. Naturally,
high throughput is essential for high
sustained productivity but it is not the
only factor. System uptime and the fab’s
way of working also play a key role.
ASML puts considerable effort into
helping customers increase their overall
productivity. We are constantly reviewing
our systems to maximize availability
and reliability. At the same time, our
extensive customer support organization
is deploying ‘e-tools’ to intelligently
schedule periodic maintenance and
reduce downtime.
In addition, we offer the Customized
Productivity Improvement program (see
‘A better way to increase your profitability’
page 6) to help fab managers optimize
operations for the litho-cell and entire
fab, often leading to productivity gains
of 10-30%.
ASML puts considerable
effort into helping
customers increase their
overall productivity
1 The XT:1000H
(125 shots, 50 mJ/cm2, 26 x 33 mm)
2 The XT:1900Gi
(125 shots, 30 mJ/cm2, 26 x 33 mm)
23
ASML Images, Spring Edition 2008
The lithography triangle
The performance of a photolithography tool is characterized by three key capabilities. Imaging, or the ability to consistently
resolve small features, governs the IC’s size (hence cost) and performance. Overlay describes how accurately a system can
print consecutive layers on top of each other. This affects the performance of the IC and the yield of good dies per wafer.
Finally productivity, measured by how many wafers a system can process in a fixed time, impacts on the cost of the IC and
the manufacturer’s profitability.
This was the last article in a series of four on an introduction to photolithography.
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